Patent Grant
11809141
The invention generally relates to a time-to-digital converter (TDC) that uses voltage as a representation of time offset.
A time-to-digital converter (TDC) captures the time difference between two signals and produces a digital output value representative of the time difference. One common type of TDC is the Vernier delay line (VDL) type of time-to-digital converter (TDC).
In accordance with one embodiment of the invention, a time-to-digital conversion system comprises first circuitry configured to capture the time difference between the two signals as the voltage and second circuitry configured to produce a digital output value representative of the time difference between the two signals based on the voltage. In various alternative embodiments, the first circuitry may include a time-to-voltage converter circuit configured to output a voltage signal that is proportional to the time difference between the two signals and a voltage measurement circuit configured to output a voltage measurement value based on the voltage signal, and the second circuitry may include a mapping circuit configured to output a time value based on the voltage measurement value. The time-to-voltage converter circuit may include an integrate-and-dump circuit. Alternatively, the time-to-voltage converter circuit may include a controllable current source (e.g., a flip-flop circuit or a latch circuit) configured to start an output current flow in response to a first signal of the two signals and to stop the current output flow in response to a second signal of the two signals and a capacitive circuit (e.g., a capacitor, a capacitor network, or an integrate-and-dump circuit) coupled to the controllable current source and configured to store voltage based on the current output flow from the controllable current source. Alternatively, the time-to-voltage converter circuit may include a flip-flop circuit configured to produce a start signal in response to a first signal of the two signals and to produce a stop signal in response to a second signal of the two signals and an integrate-and-dump circuit configured to begin integrating on the start signal and to stop integrating on the stop signal. The voltage measurement circuit may include an analog-to-digital converter to quantize the voltage signal. The mapping circuit may implement a transfer function circuit that maps the voltage measurement value to a corresponding time value or may include a mapping table that maps voltage measurement values to corresponding time values such that the mapping table can be indexed by the voltage value to obtain the corresponding time value. The captured voltage may correspond to a voltage increase during the time difference or may correspond to a voltage drop during the time difference. The voltage measurement value and the digital output value may correspond to a phase offset between the two signals. The system may include an integrated circuit that includes the first circuitry and the second circuitry or may include an integrated circuit that includes first circuitry and a separate apparatus that includes the second circuitry.
In accordance with another embodiment of the invention, a time-to-digital conversion method comprises capturing a time difference between two signals as a voltage and producing a digital output value representative of the time difference between the two signals based on the voltage.
In various alternative embodiments, capturing a time difference between two signals as a voltage comprises producing a voltage signal that is proportional to the time difference between the two signals, and producing a digital output value representative of the time difference between the two signals based on the voltage comprises producing a voltage measurement value based on the voltage signal and outputting a time value based on the voltage measurement value. Producing a voltage signal that is proportional to the time difference between the two signals may involve starting a voltage capture operation in response to a first signal of the two signals and stopping the voltage capture operation in response to a second signal of the two signals. The captured voltage may correspond to a voltage increase during the time difference or may correspond to a voltage drop during the time difference. The digital output value may correspond to a phase offset between the two signals.
Additional embodiments may be disclosed and claimed.
Those skilled in the art should more fully appreciate advantages of various embodiments of the invention from the following “Description of Illustrative Embodiments,” discussed with reference to the drawings summarized immediately below.
It should be noted that the foregoing figures and the elements depicted therein are not necessarily drawn to consistent scale or to any scale. Unless the context otherwise suggests, like elements are indicated by like numerals.
Embodiments of the present invention implement a time-to-digital converter (TDC) using voltage as a representation of time offset. Specifically, a voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function (e.g., T=F(V), where T is time, V is the final voltage measurement, and F(V) is the transfer function) or using a mapping table that provides a time value for each possible voltage measurement value.
In certain exemplary embodiments, the TVC circuit is implemented using a new integrate-and-dump sampler in which a charge pump sinks the charge on a sampling capacitor during the time between the start signal and the stop signal (e.g., the phase offset between the two signals), which makes the delta in voltage proportional to the time between the start and stop signals. In certain exemplary embodiments, a conventional analog-to-digital converter (ADC) is used to quantize the voltage signal.
It is anticipated that TDCs of the types described herein will provide high-speed phase offset (time) sampling with lower power consumption, smaller circuit area, better linearity, and better noise performance than conventional delay line based TDCs.
It is anticipated that TDCs of the types described herein can be configured for use in a wide range of applications (e.g., for phase synchronization in high-performance 5G systems such as discussed in 4181.12901, which was incorporated by reference above, and for phase synchronization in clock distribution systems such as in high-speed wireline-like data center I/O systems) and in virtually any form (e.g., implemented as stand-alone TDC integrated circuit devices, implemented as part of larger integrated circuits, implemented using discrete components, etc. For example, it is envisioned that TDCs of the types described herein can be used as part of the phase measurement circuit described in 4181-12901 and 4181-12903, which were incorporated by reference above, to measure the time difference between a reference signal and a synthesizer output signal where a first event, such as a rising edge of the reference signal, acts as the start signal and a second event, such as a subsequent rising edge of the synthesizer output signal, acts as the stop signal. The TDC outputs a digital value representing the time difference between the two events. It also is envisioned that TDC calibration techniques discussed in 4181-13403, which was incorporated by reference above, can be applied to TDCs of the types described herein such as to configure the mapping table that provides a time value for each possible voltage measurement value, e.g., as described with reference to
It should be noted that time-to-digital converters and related calibration and operational systems and methods can be used in a wide variety of applications. Various embodiments can be used in the context of active electronically steered antenna (AESA) systems also called Active Antenna, although the present invention is in no way limited to AESA systems. AESA systems form electronically steerable beams (sometimes referred to as “beam forming” or “BF”) that can be used for a wide variety of applications. Generally speaking, a “beam-formed signal” is a signal produced by or from a plurality of beam forming elements. A “beam forming element” (sometimes referred to simply as an “element” or “radiating element”) is an element that is used to transmit and/or receive a signal for beam forming. Different types of beam forming elements can be used for different beam forming applications. For example, the beam forming elements may be RF antennas for RF applications (e.g., radar, wireless communication system such as 5G applications, satellite communications, etc.), ultrasonic transducers for ultrasound applications, optical transducers for optical applications, microphones and/or speakers for audio applications, etc. Typically, the signal provided to or from each beam forming element is independently adjustable, e.g., as to gain/amplitude and phase. In the context of the present invention, there is no requirement that a beam-formed signal have any particular characteristics such as directionality or coherency. Although certain details of various embodiments of an AESA system are discussed below, those skilled in the art can apply some embodiments to other AESA systems. Accordingly, discussion of an AESA system does not necessarily limit certain other embodiments.
Of course, those skilled in the art use AESA systems 10 and other phased array systems in a wide variety of other applications, such as RF communication, optics, sonar, ultrasound, etc. Accordingly, discussion of satellite, radar, and wireless communication systems are not intended to limit all embodiments of the invention.
The satellite communication system may be part of a cellular network operating under a known cellular protocol, such as the 3G, 4G (e.g., LTE), or 5G protocols. Accordingly, in addition to communicating with satellites, the system may communicate with earth-bound devices, such as smartphones or other mobile devices, using any of the 3G, 4G, or 5G protocols. As another example, the satellite communication system may transmit/receive information between aircraft and air traffic control systems. Of course, those skilled in the art may use the AESA system 10 in a wide variety of other applications, such as broadcasting, optics, radar, etc. Some embodiments may be configured for non-satellite communications and instead communicate with other devices, such as smartphones (e.g., using 4G or 5G protocols). Accordingly, discussion of communication with orbiting satellites 12 is not intended to limit all embodiments of the invention.
In certain exemplary embodiments, the beam forming elements may be implemented as patch antennas that are formed on one side of a laminar printed circuit board, although it should be noted that the present invention is not limited to patch antennas or to a laminar printed circuit board. In exemplary embodiments, a phased array includes X beam forming integrated circuits (BFICs), with each BFIC supporting Y beam forming elements (e.g., 2 or 4 beam forming elements per BFIC, although not limited to 2 or 4). Thus, such a phased array includes (X*Y) beam forming elements.
Specifically, the AESA system 10 of
As a patch array, the elements 18 have a low profile. Specifically, as known by those skilled in the art, a patch antenna (i.e., the element 18) typically is mounted on a flat surface and includes a flat rectangular sheet of metal (known as the patch and noted above) mounted over a larger sheet of metal known as a “ground plane.” A dielectric layer between the two metal regions electrically isolates the two sheets to prevent direct conduction. When energized, the patch and ground plane together produce a radiating electric field. Illustrative embodiments may form the patch antennas using conventional semiconductor fabrication processes, such as by depositing one or more successive metal layers on the printed circuit board 16. Accordingly, using such fabrication processes, each radiating element 18 in the phased array 10A should have a very low profile. It should be noted that embodiments of the present invention are not limited to rectangular-shaped elements 18 but instead any appropriate shape such as circular patches, ring resonator patches, or other shape patches may be used in other particular embodiments.
The phased array 10A can have one or more of any of a variety of different functional types of elements 18. For example, the phased array 10A can have transmit-only elements 18, receive-only elements 18, and/or dual mode receive and transmit elements 18 (referred to as “dual-mode elements 18”). The transmit-only elements 18 are configured to transmit outgoing signals (e.g., burst signals) only, while the receive-only elements 18 are configured to receive incoming signals only. In contrast, the dual-mode elements 18 are configured to either transmit outgoing burst signals, or receive incoming signals, depending on the mode of the phased array 10A at the time of the operation. Specifically, when using dual-mode elements 18, the phased array 10A generally can be in either a transmit mode, or a receive mode.
The AESA system 10 has a plurality of the above noted integrated circuits 14 (mentioned above with regard to
As an example, depending on its role in the phased array 10A, each integrated circuit 14 may include some or all of the following functions:
Indeed, some embodiments of the integrated circuits 14 may have additional or different functionality, although illustrative embodiments are expected to operate satisfactorily with the above noted functions. Those skilled in the art can configure the integrated circuits 14 in any of a wide variety of manners to perform those functions. For example, the input amplification may be performed by a low noise amplifier, the phase shifting may use conventional active phase shifters, and the switching functionality may be implemented using conventional transistor-based switches. Additional details of the structure and functionality of integrated circuits 14 are discussed below.
In illustrative embodiments, multiple elements 18 share the integrated circuits 14, thus reducing the required total number of integrated circuits 14. This reduced number of integrated circuits 14 correspondingly reduces the cost of the AESA system 10. In addition, more surface area on the top face of the printed circuit board 16 may be dedicated to the elements 18.
To that end, each integrated circuit 14 preferably operates on at least one element 18 in the array and typically operates on a plurality of elements 18. For example, as discussed above, one integrated circuit 14 can operate on two, three, four, five, six, or more different elements 18. Of course, those skilled in the art can adjust the number of elements 18 sharing an integrated circuit 14 based upon the application. For example, a single integrated circuit 14 can control two elements 18, three elements 18, four elements 18, five elements 18, six elements 18, seven elements 18, eight elements 18, etc., or some range of elements 18. Sharing the integrated circuits 14 between multiple elements 18 in this manner reduces the required total number of integrated circuits 14, correspondingly reducing the required size of the printed circuit board 16 and cost of the system.
As noted above, dual-mode elements 18 may operate in a transmit mode, or a receive mode. To that end, the integrated circuits 14 may generate time division diplex or duplex waveforms so that a single aperture or phased array 10A can be used for both transmitting and receiving. In a similar manner, some embodiments may eliminate a commonly included transmit/receive switch in the side arms (discussed below) of the integrated circuit 14. Instead, such embodiments may duplex at the element 18. This process can be performed by isolating one of the elements 18 between transmit and receive by an orthogonal feed connection. Such a feed connection may eliminate about a 0.8 dB switch loss and improve G/T (i.e., the ratio of the gain or directivity to the noise temperature) by about 1.3 dB for some implementations.
RF interconnect and/or beam forming lines 26 electrically connect the integrated circuits 14 to their respective elements 18. To further minimize the feed loss, illustrative embodiments mount the integrated circuits 14 as close to their respective elements 18 as possible. Specifically, this close proximity preferably reduces RF interconnect line lengths, reducing the feed loss. To that end, each integrated circuit 14 preferably is packaged either in a flip-chipped configuration using wafer level chip scale packaging (WLCSP) or other configuration such as extended wafer level ball-grid-array (eWLB) that supports flip chip, or a traditional package, such as quad flat no-leads package (QFN package).
It should be reiterated that although
It should be noted that embodiments of the present invention may employ conventional components such as conventional programmable logic devices (e.g., off-the shelf FPGAs or PLDs) or conventional hardware components (e.g., off-the-shelf ASICs or discrete hardware components) which, when programmed or configured to perform the non-conventional functions described herein, produce non-conventional devices or systems. Thus, there is nothing conventional about the inventions described herein because even when embodiments are implemented using conventional components, the resulting devices and systems (e.g., TDC devices and circuits) are necessarily non-conventional because, absent special programming or configuration, the conventional components do not inherently perform the described non-conventional functions.
While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.
Various inventive concepts may be embodied as one or more methods, of which examples have been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
As used herein in the specification and in the claims, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.
Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention. Any references to the “invention” are intended to refer to exemplary embodiments of the invention and should not be construed to refer to all embodiments of the invention unless the context otherwise requires. The described embodiments are to be considered in all respects only as illustrative and not restrictive.
This patent application claims the benefit of United States Provisional Patent Application No. 63/155,376 entitled TIME-TO-DIGITAL CONVERTER USING VOLTAGE AS A REPRESENTATION OF TIME OFFSET filed Mar. 2, 2021, which is hereby incorporated herein by reference in its entirety. The subject matter of this patent application may be related to the subject matter of commonly-owned U.S. Patent Application No. 62/875,984 entitled PHASE-ALIGNING MULTIPLE SYNTHESIZERS filed on Jul. 19, 2019, and U.S. patent application Ser. No. 16/932,187 PHASE-ALIGNING MULTIPLE SYNTHESIZERS filed on Jul. 17, 2020 published as U.S. Patent Application Publication No. US 2021/0021402, both of which are hereby incorporated herein by reference in their entireties. The subject matter of this patent application also may be related to the subject matter of commonly-owned U.S. Patent Application No. 63/155,374 entitled CALIBRATING A TIME-TO-DIGITAL CONVERTER filed on Mar. 2, 2021, which is hereby incorporated herein by reference in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 10725433 | Fujimoto | Jul 2020 | B2 |
| 20180005579 | Brahma | Jan 2018 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20220283550 A1 | Sep 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| 63155376 | Mar 2021 | US |
