This application is related to signal converters and more particularly to signal conversion using time-to-voltage converters.
In general, a time-to-voltage converter measures an interval of time between events, e.g., a time between a rising edge of a signal and a falling edge of the signal. Integrated circuit applications use time-to-voltage converter circuits in time-to-digital converters and digital-to-time converters. A typical time-to-voltage converter charges a capacitor during an interval of interest to generate an output voltage that is linearly related to the interval. That output voltage may be measured using an analog-to-digital converter of a time-to-digital converter or may be compared to a predetermined threshold voltage by a comparator of a digital-to-time converter.
Referring to
Referring to
Time-to-digital converter 100 and digital-to-time converter 400 each use charging intervals of time that guarantee linear operation. For example, a minimum charging interval is defined by the current source switching speed and a maximum time interval is defined by the voltage required across the current source to ensure sufficiently high output impedance. In general, current sources generate substantial noise due to a relatively low overdrive voltage. Such designs in applications that require accurate measurement of a relatively fixed time interval are susceptible to flicker noise. In addition, the gain of time-to-digital converter 100 and digital-to-time converter 400 may be sensitive to variations in manufacturing process, temperature, strain, and/or aging, which may impact performance of an application including those circuits. Accordingly, improved techniques for signal conversion using time-to-voltage converters are desired.
In at least one embodiment of the invention, an apparatus includes a time-to-voltage converter configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals. The apparatus may include a phase detector configured to generate the input time signal indicative of an input interval. The apparatus may include an analog-to-digital converter configured to generate a digital code corresponding to the output voltage signal using the correlated reference voltage signal. The phase detector, the time-to-voltage converter, and the analog-to-digital converter may be configured as a time-to-digital converter. The apparatus may include a digital-to-analog converter configured to use the correlated reference voltage signal to generate the input time signal in response to an input digital code and a reference time signal. The apparatus may include a comparator configured to generate an output time signal in response to a comparison of the output voltage signal and a threshold voltage level of the comparator. The time-to-voltage converter, the digital-to-analog converter, and the comparator may be configured as a digital-to-time converter.
In at least one embodiment of the invention, a method includes generating a bias current and generating an output voltage signal that is linearly related to an input time signal based on the bias current during a first interval. The method includes generating a correlated reference voltage signal. Generation of the correlated reference voltage signal includes sampling the bias current during a second interval to generate a bias current sample. Generation of the correlated reference voltage signal includes updating the correlated reference voltage signal using the bias current sample to generate the correlated reference voltage signal. The first interval and the second interval are non-overlapping intervals. The method may include converting an input interval between a time representation and a digital signal representation based on the output voltage signal and the correlated reference voltage signal.
In at least one embodiment of the invention, a data converter includes a time-to-voltage converter configured to generate an output voltage signal in response to an input interval and a correlated reference voltage signal in response to a reference interval. The data converter is a time-to-digital converter or a digital-to-time converter. If the data converter is the time-to-digital converter, the data converter further includes a phase detector configured to generate the input interval in response to a first input signal and a second input signal and an analog-to-digital converter configured to generate a digital code corresponding to the output voltage signal using the correlated reference voltage signal. If the data converter is the digital-to-time converter, the data converter further includes a digital-to-analog converter configured to use the correlated reference voltage signal to generate the input interval in response to an input digital code and an input time signal and a comparator configured to generate an output time signal in response to a comparison of the output voltage signal and a threshold voltage level of the comparator.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
Referring to
v
OUT
=t
IN
×I
SLEW
/C
SLEW.
During a hold interval (e.g., RESET==‘0’ and SLEW==‘0’), time-to-voltage converter 104 holds voltage vOUT, as needed. Analog-to-digital converter 106 is a conventional voltage-mode analog-to-digital converter that generates digital output code DOUT based on input voltage VIN provided to the analog-to-digital converter as follows:
where vREF,ADC is a reference voltage provided to analog-to-digital converter 106, NADC is the number of bits of digital output code DOUT, and εq is the quantization error. Since time-to-voltage converter 104 provides voltage vOUT and input voltage vIN to analog-to-digital converter 106, the relationship becomes:
Note that the gain of time-to-digital converter 100 is defined by current ISLEW and reference voltage vREF,ADC.
Current source 306 is a conventional current source, as illustrated in
I
SLEW
=v
REF
×n×G
REF,
where n is the ratio of transistor sizes in the current mirror and GREF is the conductance of the reference resistor. Thus, the digital output code may be represented as:
As a result, the gain of the time-to-digital converter 100 of
a resistor-capacitor component ratio
and a transistor ratio (n). Similarly, the digital-to-time converter 400 of
where voltage vIN is the output of digital-to-analog converter 402 and vTH is the threshold voltage of comparator 406. As a result, the gain of digital-to-time converter 400 is also defined by a voltage ratio
a resistor-capacitor component ratio
and a transistor ratio (1/n). The voltages of the voltage ratios of time-to-digital converter 100 of
A time-to-voltage converter using correlated double sampling of a current generates the output voltage using a capacitor in response to the input interval and generates a correlated reference voltage using a predetermined reference interval and a second capacitor. The two different capacitors sample the output of the same current source to reduce or eliminate effects of the current source. The time-to-voltage converter provides that correlated reference voltage to a related circuit. Use of the correlated voltage reference in the related circuit increases gain accuracy and reduces or eliminates flicker noise in time-to-digital converters and digital-to-time converters by eliminating the gain dependence on one or more of a voltage ratio, resistor-capacitor component ratio, and/or the transistor ratio described above for conventional time-to-digital converters and digital-to-time converters. Inclusion of those time-to-digital converters and digital-to-time converters in timing circuits (e.g., fractional frequency counters and interpolative dividers) that use the output voltage and correlated voltage reference have improved close-in phase noise and deterministic jitter. The time-to-digital converters and digital-to-time converters that implement a time-to-voltage converter using correlated double sampling voltage reference generation have increased modularity, resulting in less complex systems.
Referring to
Referring to
Signal DUMP_N and signal REF_N include a reference interval tREF, which is generated using a predetermined number NREF of periods of a precise reference clock having period TVCO:
t
REF
=N
REF
×T
VCO.
The precise reference clock may be a well-defined voltage-controlled oscillator clock signal that tracks a crystal oscillator or LC oscillator (e.g., +/−100 ppm) and may be otherwise available in the system. For example, reference interval tREF is a precise time pulse generated from eight or 16 periods of an LC oscillator output signal. An exemplary reference interval tREF is 10 ns, which is much greater (e.g., at least two orders of magnitude greater) than input interval tIN being converted (e.g., 10 ps). The resulting correlated reference voltage vREF,C varies as a function of reference interval tREF:
Thus, the digital output code generated by a time-to-digital converter that uses correlated reference voltage vREF,C generated by time-to-voltage converter 504 as the reference voltage for the analog-to-digital converter may be represented as:
Digital output code DOUT, generated using correlated reference voltage vREF,C and provided by time-to-voltage converter 504 as the reference voltage for the analog-to-digital converter, is well-behaved and has reduced (e.g., negligible) low-frequency bias noise. However, voltage vOUT, generated by time-to-voltage converter 504, varies as a function of the period of reference interval tREF and may be limited to a narrow frequency range to obtain target performance, which may be unacceptable in some applications.
Referring to
Referring to
Thus, time-to-voltage converter 504 can be adjusted to increase headroom over a wider frequency range. Since reference voltage VREF varies by less than +/−5%, capacitance ratio CREF/CS,R is fixed, and n has negligible variation as a function of temperature, a simple counter may be used to generate reference interval tREF and implement a fixed ratio for tREF/TIN for a particular correlated reference voltage vREF,C to reduce or eliminate frequency-dependent effects. Multiple switched-capacitor resistors may be coupled in parallel and may operate in different intervals to smooth voltage ripple for operation at higher frequencies.
Rather than using a switched-capacitor resistor load to extend the frequency range of operation, in at least one embodiment of time-to-voltage converter 504, current source 524 receives correlated reference voltage vREF,C as feedback, which also eliminates the current mirror and associated error (
which is independent of the voltage ratio described above.
Referring to
Referring to
Q
IN
=t
IN
×I
SLEW,
where tIN is the input interval of signal SLEW_N and signal DUMP_N. The output switched-capacitor charge injected into virtual ground by COS and CREF,C is:
Q
OUT=−(dOUTCREF,C+COS)vREF,C.
Digital output signal dOUT is a digital bit stream such that dOUT∈[1,0], and the correlated reference voltage vREF,C is:
where tREFis the reference interval of signal REF_N and signal DUMP_N and CTOTAL is the total capacitance configured in parallel when delivering charge to node 1600. Average output charge QOUT equals input charge QIN, thus the average digital output signal is defined by the following relationship:
and QREF is the total charge delivered by current ISLEW node REF,C during reference interval tREF. Different charge delivery intervals based on the reference interval tREF correspond to each of the capacitors and each of the capacitors holds a different amount of charge according to size. In general, charge Q equals current I times interval of current delivery t (i.e., Q=t×I), and
Accordingly, the average digital output signal is defined by the following relationship:
tFS is the full-scale time (e.g., the total input time range of an associated time-to-digital converter or the total output time range supported by an associated digital-to-time converter), and QFS is the full-scale charge in the charge domain (e.g., the maximum amount of charge that can be removed from the virtual ground in each conversion cycle of a comparator of an associated sigma-delta modulator).
Note that in practice, tON and tOFF are not instantaneous, but rather have non-zero values (i.e., tON>0 and tOFF>0), which contribute to nonlinearity in the output of the time-to-voltage converter. Referring to
Supplying correlated reference voltage vREF,C,P and correlated reference voltage vREF,C,M to a positive reference voltage terminal and a negative reference voltage terminal of analog-to-digital converter 106 of time-to-digital converter 500 of
Capacitive digital-to-analog converter 1902 selectively enables each bit cell according to a corresponding input bit bn. If bn has a low logic value (i.e., bn==‘0’), then capacitive bit cell 1904 provides constant signals to decouple the capacitive bit cell from the positive voltage reference and couple the capacitive bit cell to ground, thereby discharging the switched-capacitor node.
If bn has a high logic value (i.e., bn==‘1’), then capacitive bit cell 1904 provides the charge control signal to selectively couple the switched-capacitor node scn to the positive voltage reference node and provides the shift control signal to selectively couple the switched-capacitor node scn to the negative voltage reference node. The charge control signal and the shift control signal charge switched-capacitor node scn to voltage vREF,DAC in a first interval (CHARGE==‘1’ and SHIFT==‘0’), thereby pre-charging switched-capacitor node scn to a pre-charge voltage. During a second interval, the charge control signal and the shift control signal (CHARGE==‘0’ and SHIFT==‘1’) shift the voltage on switched-capacitor node scn to a second voltage
vRESET−ΔvREF,DAC′,
where ΔvREF,DAC′=(vREF,DAC)×CT/(CT+COUT) and
CT is the sum of capacitances Cn for each bit cell having bn==‘1’. As a result, voltage vOUT,DAC becomes VRESET−ΔvREF,DAC′, which is an analog value corresponding to the value of DIN and based on vREF,C. Since the output voltage of the capacitive digital-to-analog converter on node 1920, voltage vOUT,DAC, is generated using correlated voltage reference vREF,C, the output signal, used to generate output time signal STOP has improved gain accuracy and negligible by eliminating the gain dependence on one or more of the voltage ratio, resistor-capacitor component ratio, and/or the transistor ratio described above for digital-to-time converters.
Thus, correlated double sampling techniques for generating a correlated reference voltage in a time-to-voltage converter have been described. The correlated reference voltage vREF,C (or correlated reference voltage vREF,C,M and correlated reference voltage vREF,C,P) generated as described above can be provided as the reference voltage to analog-to-digital converter 106 of time-to-digital converter 500 of
The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which a sigma-delta analog-to-digital converter and a capacitor digital-to-analog converter are used, one of skill in the art will appreciate that the teachings herein can be utilized with other types of analog-to-digital converters, other types of digital-to-analog converters, or other companion circuits are used with the correlated reference voltage. In addition, other time-to-voltage converters that use correlated double sampling to generate a correlated reference voltage consistent with the invention have different reset voltage levels, discharge a capacitor from the reset voltage level, and may generate an output signal that is linearly related to a time delay between a falling edge of the control signal and a rising edge of the control signal. Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.