Time-variant antenna enabled by switched capacitor array on silicon

Abstract

A time-variant antenna is disclosed that uses a switched capacitor array in silicon to improve the performance and integration options of the time-variant antenna. Parasitic effects of the interface between the on-board antenna and on-silicon switched capacitor array are considered and the antenna is tuned to compensate for these effects. The switched capacitor array provides high linearity, lower cost, and reduced size, relative to prior art antenna implementations.

Description

TECHNICAL FIELD

This application relates to antennas and, in particular, to a switched capacitor array implemented on silicon.

BACKGROUND

Antennas are used in a variety of devices to transmit electrical currents, converted into radio waves, to a remote device that also has an antenna. Antennas come in many types, but each one has a metallic surface for radiating and receiving the electromagnetic energy. Recently, antennas are even being embedded into printed circuit boards.

Typically, antennas are designed to send and receive signals within a particular range of frequencies. An antenna designed for broadband use may not necessarily be suited to a narrowband device. Despite this limitation, some antennas may be adjusted to operate under different applications.

A simplified system 100 with a prior art antenna 44 is depicted in FIG. 1. The antenna 44 is connected to a transceiver 40, which converts electrical signals to radio waves, making them suitable for transmission over air. Likewise, the transceiver converts received radio waves into electrical signals. The antenna 44 is also connected to a varactor 46 and a waveform generator 42.

The waveform generator 42 drives the varactor 46 (a variable capacitor), which adjusts the properties of the antenna 44 so as to change the resonant frequencies and the antenna bandwidth in which the antenna operates. This makes the antenna 44 more flexible in its operation, but the waveform generator 42 and varactor 46 also increase the cost, size, and complexity of the system 100. In addition to this, an off-the-shelf variable capacitor is a non-linear device, which has the potential to generate undesired intermodulation in the transceiver 40.

Thus, there is a continuing need for a time-variant antenna that overcomes the shortcomings of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this document will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views, unless otherwise specified.

FIG. 1 is a simplified block diagram of a system using an antenna, according to the prior art;

FIG. 2 is a simplified block diagram of a system using a time-variant antenna enabled by a switched capacitor array, according to some embodiments;

FIG. 3 is detailed diagram of the time-variant antenna system of FIG. 2, according to some embodiments;

FIG. 4 is a schematic diagram of the interface 56, according to some embodiments;

FIG. 5 is an itemized circuit model of the parasitic elements found in FIG. 4, according to some embodiments;

FIG. 6 is a simplified circuit model of the parasitic elements found in FIG. 4, according to some embodiments;

FIG. 7 is a simplified block diagram of a multi-antenna system using time-variant antennas enabled by switched capacitor arrays, according to some embodiments;

FIG. 8 is a simplified block diagram of a processor-based system implementing the time-variant antenna enabled by the switched capacitor array of FIG. 2, according to some embodiments;

FIG. 9 is a simplified diagram showing the antenna response for the system of FIG. 1, according to some embodiments; and

FIG. 10 is a simplified diagram showing the antenna response for the time-variant antenna system of FIG. 2, according to some embodiments.

DETAILED DESCRIPTION

In accordance with the embodiments described herein, a time-variant antenna is disclosed that uses a switched capacitor array in silicon to improve the performance and integration options of the time-variant antenna. Parasitic effects of the interface between the on-board antenna and on-silicon switched capacitor array are considered and the antenna is tuned to compensate for these effects. The switched capacitor array provides high linearity, lower cost, and reduced size, relative to prior art antenna implementations.

In the following detailed description, reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the subject matter described herein may be practiced. However, it is to be understood that other embodiments will become apparent to those of ordinary skill in the art upon reading this disclosure. The following detailed description is, therefore, not to be construed in a limiting sense, as the scope of the subject matter is defined by the claims.

The time-variant antenna (TVA) is disclosed in United States Patent Application No. PCT/US2011/065629, entitled, “Wireless Communication Device Using Time-Variant Antenna Module”, filed on Dec. 16, 2011. The TVA design provides several benefits over prior art antenna designs, not the least of which is a significant improvement in performance. However, the non-linearity of the waveform generator 42 and varactor 46 (FIG. 1) may cause intermodulation in the transceiver 40, an undesirable property of the prior art system 100.

A novel time-variant antenna system 200 is depicted in FIG. 2, according to some embodiments. The system 200 includes an antenna board 60 and silicon substrate 52, connected by an interface 56. The antenna board 60 includes the antenna 44, which is connected to the transceiver 40. A switched capacitor logic unit 300 is disposed on the silicon 52. The switched capacitor logic 300 replaces the varactor 46 and waveform generator 42 of the prior art system 100. The switched capacitor logic 300 includes a switched capacitor array of parallel capacitors 58 driven by control logic input, which is described in more detail below. In some embodiments, the time-variant antenna system 200 provides high linearity, low cost, and reduced size, relative to the prior art system 100.

FIG. 3 is a detailed diagram of the time-variant antenna system 200 of FIG. 2, according to some embodiments. The switched capacitor logic 300 consists of control logic 70 and a capacitor array 80, which consists of N switchable capacitors 58 for integer N, as well as N switches 62. The control logic 70 is able to independently turn on or turn off each capacitor 58 in the capacitor array 80 by activating or deactivating its respective switch 62.

In some embodiments, the number of switched capacitors 58 is determined based on how much resolution is needed for a given application. The control logic 70 may thus configure the capacitor array 80 such that one or more of its capacitors 58 is enabled, with the remaining capacitors in the capacitor array being dormant. Further, the control logic 70 turns on or off the enabled capacitors, as needed, to create the desired capacitance variation for a given application. Thus, the control logic 70 both 1) enables or disables the capacitors 58 within the capacitor array 80 and 2) is able to turn on or off the enabled capacitors, based on the desired capacitance.

In some embodiments, the switched capacitor logic 300 is able to generate various forms of capacitor variation in digital format via a simple register within the control logic 70, obviating the need for the waveform generator 42 and varactor 46 (FIG. 1). In some embodiments, this implementation reduces the cost and size of the system 200, while maintaining similar or better performance than the prior art solution. As radio functions are being integrated into single chip or package solutions with more conventional digital functions, the time-variant antenna system 200 is well suited to such implementations. Further, the time-variant antenna system 200 design may also enable self-calibration or compensation to offset part-to-part variation of the capacitor array and antenna elements.

As illustrated in FIG. 2, the switched capacitor logic 300 of the time-variant antenna system 200 is implemented in silicon 52. A parasitic effect is thus likely in the interface 56 between the antenna 44 (on the antenna board 60) and the switched capacitor logic 300 (on the silicon 52).

Each switched capacitor consists of the capacitor 58 and its respective switch 62, which, in some embodiments, is a transistor element. There are different kinds of switched capacitors that may be used in the switched capacitor array 80. For example, metal oxide semiconductor (MOS) capacitors, metal finger capacitors (MFCs), and metal insulator metal (MIM) capacitors are all available as switched capacitors. Each type of capacitor has different characteristics, so a selection of one type may be made in view of considerations such as performance, size, and cost.

One of the characteristics of a switched capacitor is that it is linear in nature. Thus, replacing the varactor 46 with the switched capacitor logic 300 eliminate the potential intermodulation issues that occur with the former, in some embodiments. Typically the switched capacitor elements provide a capacitance/area of about 3.3 fF/μm² (e.g., MIM capacitor).

To support wireless communications, such as LTE, cellular, WiFi, WiMAX, and so on, the time-variant antenna 44 will need a capacitance range of about 1-30 pF for antenna tunability. Therefore, a total required area for the switched capacitor for these applications is be only 8820 μm² (example: 42 μm×210 μm) approximately when N=5, that is, there are five switched capacitor elements 58 in the array 80. Thus, in some embodiments, the switched capacitor array 80 occupies an extremely small space in the silicon 52. The five switched capacitor elements 58 generate 31 different states (2⁵−1), which provides the resolution of the prior art implementation, using less space.

Since this switched capacitor is implemented in silicon, in some embodiments, the parasitic effect that may be generated along the interface 56 between the antenna 44 and the switched capacitor logic 300 is considered. FIG. 4 is a schematic diagram depicting different elements or entities of the interface 56 to be considered when studying parasitic effects, according to some embodiments. The switched capacitor array 80 is connected to the antenna 44 through a transmission line 76, a land pad 72, a controlled collapse chip connection (C4) 84, an electrostatic discharge (ESD) protection diode 78, and a metal line 82. Each of these elements is considered in the itemized circuit model of FIG. 5, below.

The ESD protection diode 78 is included to protect the switched capacitor array 80 from an electrostatic discharge. In some embodiments, the capacitance of the ESD diode 78 is approximately 220 fF. The impedance values of the other interface elements for one implementation of the time-variant antenna system 200 are summarized in Table 1, below. In Table 1, the transmission line is a micro-strip line and the metal line has a length of approximately 100 μm. In some embodiments, the effect of the metal line impedance may be minimized if the switched capacitor array 80 is designed next to the solder bumps (not shown), the C4 84, and the ESD protection diode 78.

TABLE 1
estimated impedance values of interface 56
interface	resistance, R	inductance, L	capacitance, C
transmission line	NA	L1 = 7.5 nH/inch	C1 = 3 pF/inch
76
land pad 72	NA	NA	CL = 0.2~0.4 pF
C4 84	NA	L2 = 500 pH	C2 = 0.2 pF
ESD protection	NA	NA	C3 = 220 fF
diode 78
metal line 82	R = 17 ohm	L4 = 4.83 fH	C4 = 25.3 fF
simplified circuit	Rp = 16.4 ohm	Lp = 15.5 nH	Cp = 3.77 pF
model

The above parasitic elements are also depicted as an itemized circuit model 400 in FIG. 5, and its simplified model 500 in FIG. 6, according to some embodiments. In FIG. 5, between the switched capacitor array 80 and the antenna 44 are disposed the potentially parasitic elements, the transmission line 76, the land pad 72, the C4 84, the ESD diode 78, and the metal line 82. The transmission line 76 provides inductance, L₁, and capacitance, C₁, the land pad 72 provides capacitance, C_L, the C4 84 provides inductance, L₂ and capacitance, C₂, the ESD diode 78 provides capacitance, C₃, and the metal line 82 provides inductance, L₄, capacitance, C₄, and resistance, R.

In the simplified circuit model 400 (FIG. 6), the above potentially parasitic elements are depicted merely as parasitic elements 90 having an inductance, L_p, a capacitance, C_p, and a resistance, R_p. In some embodiments, during a simulation of the time-variant antenna system 200, the parasitic inductance, capacitance, and resistance were measured, and are given in Table 1.

In some embodiments, the parasitic effect in the design of the time-variant antenna system 200, as shown in FIGS. 5 and 6, is considered when controlling the antenna from the switched capacitor array 80. This is possible even though the parasitic elements are located on the board 60 while the switched capacitor array 80 is on the silicon 52. Thus, in some embodiments, where the antenna frequency response is to be adjusted, the additional parasitic element values, L_p, C_p, and R_p, are also considered.

In some applications, the transceiver 40 may be coupled to multiple antennas, known as multiple-input-multiple-output (MIMO) systems. The time-variant antenna system 200 may operate in a multiple antenna environment. For example, where the transceiver 40 is coupled to four antennas, a separate switched capacitor array 80 is dedicated to each antenna, as depicted in FIG. 7, according to some embodiments. The control logic 70 controls each of the separate arrays 80A, 80B, 80C, and 80D, as needed to control the frequency range of their respective antennas 44A, 44B, 44C, and 44D.

FIG. 8 is a simplified block diagram of a processor-based system 700 implementing the time-variant antenna system 200 of FIG. 2, according to some embodiments. The processor-based system 700 may be a laptop computer, a mobile telephone, a personal digital assistant, or other wireless device. A system board 260 of the processor-based system 200 includes a central processing unit (CPU) or processor 120 and a memory 122. In some embodiments, the control logic 70 is implemented as a software program 150 and a lookup table 130, with the software being loaded into the memory 122 and executed by the processor 120. In some embodiments, the software 150 controls the switches 62 in the switched capacitor array 80, which, in turn, enables or disables the respective capacitor 58 within the array, thus tuning the antenna 44. The switched capacitor array is part of a silicon substrate 52 disposed on the system board 260, while the antenna 44 is on the antenna board 60. In some embodiments, the lookup table 130 contains parasitic effects data such as that found in Table 1, above, such that the control logic 70 is able to intelligently tune the antenna 44 to compensate for the parasitic effects.

FIGS. 9 and 10 are diagrams comparing the antenna response obtained using a prior art antenna system versus the antenna system 200, according to some embodiments. In FIG. 9, the varactor-based antenna system 100 (FIG. 1) generates two different antenna responses, 800A and 800B, resulting from square wave 810A and sawtooth 810B voltage inputs, respectively. In FIG. 10, two capacitance input waveforms, 830A and 830B, are generated by the time-variant antenna system 200, to emulate the voltages 810A and 810B, respectively. The antenna responses, 820A and 820B, are substantially similar to the antenna responses 800A and 800B, respectively.

Thus, the time-variant antenna system 200 optimally includes the switched capacitor logic 300, as described above, in some embodiments, to reduce cost and size significantly, without a loss of functionality. The linearity of the time-variant antenna 44 is enhanced with the switched capacitor array 300, thanks to its linear characteristics, in some embodiments. The number of capacitors 58 making up the switched capacitor array 80 may be determined based on its applications and the desired frequency range of the antenna 44. Further, where possible, the switched capacitor array 80 may include enabled and dormant capacitors, for maximum flexibility of operation and applications.

While the application has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the invention.

Claims

1. A time-variant antenna system, comprising: an antenna coupled to a transceiver, the antenna being disposed upon an antenna board, wherein the antenna comprises a frequency response;a switched capacitor logic coupled to the antenna through an interface, wherein the switched capacitor logic is disposed upon a silicon surface, the switched capacitor logic further comprising: a plurality of capacitors;a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor of the plurality of capacitors; anda control logic to enable or disable a switch of the plurality of switches; andan interface disposed between the board and the silicon, the interface comprising a parasitic effect, wherein the control logic tunes a frequency range of the antenna in view of the parasitic effect;

2. The time-variant antenna system of claim 1, wherein the plurality of switches and the plurality of capacitors comprise metal-oxide semiconductor devices.

3. The time-variant antenna system of claim 1, wherein the plurality of capacitors comprise metal finger devices.

4. The time-variant antenna system of claim 1, wherein the plurality of capacitors comprise metal-insulator-metal devices.

5. The time-variant antenna system of claim 1, wherein the parasitic effect comprises: parasitic resistance;parasitic inductance; andparasitic capacitance.

6. The time-variant antenna system of claim 1, wherein the interface further comprises: a transmission line comprising a parasitic inductance and a parasitic capacitance.

7. The time-variant antenna system of claim 1, wherein the interface further comprises: a land pad comprising a parasitic capacitance.

8. The time-variant antenna system of claim 1, wherein the interface further comprises: a controlled collapse chip connection comprising a parasitic inductance and a parasitic capacitance.

9. The time-variant antenna system of claim 1, wherein the interface further comprises: an electrostatic discharge diode comprising a parasitic capacitance.

10. The time-variant antenna system of claim 1, wherein the interface further comprises: a metal line comprising a parasitic inductance, a parasitic capacitance, and a parasitic resistance.

11. The time-variant antenna system of claim 1, wherein the switched capacitor logic comprises five capacitors and five switches; wherein the control logic adjusts the frequency range of the antenna to one of thirty-one possible states.

12. The time-variant antenna system of claim 1, wherein the switched capacitor logic comprises N capacitors and N switches, for integer N; wherein the control logic adjusts the frequency range of the antenna to one of 2N−1 possible states.

13. A time-variant antenna system, comprising: an antenna coupled to a transceiver, the antenna being disposed upon an antenna board, wherein the antenna comprises a frequency response;a switched capacitor logic coupled to the antenna through an interface, wherein the switched capacitor logic is disposed upon a silicon surface, the switched capacitor logic further comprising: a plurality of capacitors;a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor of the plurality of capacitors; anda control logic to enable or disable a switch of the plurality of switches;a second antenna coupled to the transceiver, the second antenna being disposed upon the antenna board; anda second switched capacitor logic device coupled to the second antenna, the second switched capacitor logic device being disposed upon the silicon surface and coupled to the second antenna via the interface;

14. A switched capacitor logic unit disposed on a silicon substrate, the switched capacitor logic unit comprising: a plurality of capacitors arranged in a parallel array;a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor in the parallel array; anda control logic to enable or disable one or more switches of the plurality of switches;

15. The switched capacitor logic unit of claim 14, wherein the parallel array comprises five capacitors and the plurality of switches comprises five switches; wherein the control logic adjusts the frequency range of the antenna to one of thirty-one possible states.

16. The switched capacitor logic unit of claim 14, wherein the parallel array comprises N capacitors and the plurality of switches comprises N switches, for integer N; wherein the control logic adjusts the frequency range of the antenna to one of 2N−1 possible states.

17. The switched capacitor logic of claim 14, the control logic further comprising: a software program to be loaded into a memory and to be executed by a processor;

18. The switched capacitor logic of claim 14, the control logic further comprising: a lookup table comprising parasitic effects data for one or more components in the interface between the parallel array and the antenna;

19. A processor-based system disposed on a system board, the processor-based system comprising: a central processing unit (CPU);a memory coupled to the CPU;an antenna coupled to a transceiver; anda switched capacitor logic unit, the switched capacitor logic unit comprising: a plurality of capacitors arranged in a parallel array;a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor in the parallel array; anda control logic to enable or disable one or more switches of the plurality of switches, the control logic comprising: a software program to be loaded into the memory and executed by the processor; anda lookup table comprising parasitic effects data about one or more elements of the interface;

20. The processor-based system of claim 19, wherein the lookup table comprises parasitic effects data for: a transmission line comprising a parasitic inductance, L1, and a parasitic capacitance, C1;a land pad comprising a parasitic capacitance, CL;a controlled collapse chip connection comprising a parasitic inductance, L2, and a parasitic capacitance, C2;an electrostatic discharge diode comprising a parasitic capacitance, C3;a metal line comprising a parasitic inductance L4, a parasitic capacitance, C4, and a parasitic resistance, R.