Patent Application
20240330551
The field of the disclosure is data processing, or, more specifically, methods, apparatus, and products for performing timing analysis of a digital integrated circuit using intent based timing constraints.
Fabrication of an integrated circuit or chip includes several steps to finalize such as logic design, analysis, and physical implementation. The chip may be designed according to a hierarchical design methodology such that the chip is divided into functional circuit components or elements. The logic design and component placement must result in a physical implementation that meets the design and performance requirements of the chip. To ensure that the design requirements are met, design analysis such as timing analysis of the chip is performed at different stages and levels of design.
Exemplary embodiments include a method, apparatus, and computer program product to perform timing analysis of a digital integrated circuit using intent based timing constraints. A method according to an embodiment includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.
The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the disclosure.
Exemplary apparatus and systems for performing timing analysis of a digital integrated circuit using intent based timing constraints in accordance with the present disclosure are described with reference to the accompanying drawings, beginning with
Stored in RAM 120 is an operating system 122. Operating systems useful in computers configured for performing timing analysis of a digital integrated circuit using intent based timing constraints according to embodiments of the present disclosure include UNIX™, Linux™ Microsoft Windows™, AIX™, and others as will occur to those of skill in the art. The operating system 122 in the example of
The computing system 100 of
The example computing system 100 of
The exemplary computing system 100 of
As previously discussed, design analysis such as timing analysis is performed to ensure that the physical implementation of a chip design will meet requirements. For example, static timing analysis (STA) is generally performed to efficiently accomplish timing analysis without simulating the full integrated circuit. In STA, one or more timing signals are propagated through the simulated chip design from an input side to a timing point and timing values of interest are computed such as arrival time, slew, and slack. Different timing values may be associated with different clock types of the integrated circuit such as test clocks vs. functional clocks. STA is performed at different stages of the design, but analyzing the entire chip design at every stage is inefficient in terms of run-time. Instead, a hierarchical design methodology is used and timing analysis is performed at different hierarchical levels (e.g., core, unit, component) based on the needs at any given design stage.
A component of the chip may be, for example, a single logic gate or a collection of circuits configured to perform a specific task or function. Detailed analysis may be formed at the component level. For example, components may be timed using accurate timing analysis techniques that include transistor level timing tools or gate level timing tools. This type of detailed analysis may be followed by generation of abstract models that represent the relevant characteristics, such as timing characteristics, of the component in a simplified form. The generation of abstract models may be referred to as abstraction. At higher levels (e.g., unit level, core level), components are represented by abstracts for the purposes of performing the analysis. A unit comprised of several components, each associated with abstracts, may itself be abstracted. Because components are reused in different parts of the chip design at different levels of hierarchy, the same component may be part of different clock domains.
Some timing points or nodes may be associated with timing constraints. A constraint refers to a modification or other control exerted based on the incoming timing signal. An exemplary constraint is the adjustment of the arrival time at a node by a specified value, based on the incoming signal being a functional signal. While executing a STA procedure including propagating timing values from an input side to an output side of an integrated circuit, a timing constraint may specify modifying the timing at a node with the constraint, at a node toward the output side from the node with the constraint, or at a node toward the input side from the node with the constraint. In some situations, some constraints may be in the form of loops between components.
In order to achieve proper coverage and margining in timing analysis, STA involves the creation of a plurality of clock phases for each of several generalizable categories such as functional and test categories. Examples of such generalizable categories include functional, scan, automatic built in self-test (ABIST), array test, and gate array (GA) margin. To achieve correct timing at circuit components such as latches, local clock buffers (LCBs), and other complex circuitry, timing constraints are added which control/adjust the propagation of timing phases based on these generalizable characteristics. For example, at a particular latch input, a timing engineer may need to “don't care” all timing phases of a scan type while retaining all functional phases.
In traditional timing analysis, such timing constraints need to be explicitly written against each phase belonging to a generalizable category. It should be noted that the number of phases that can correspond to a generalizable category may be dozens or more. This traditional timing analysis approach introduces significant complexity and associated runtime and memory cost. Capturing these constraints from lower level design to upper level timing requires post-processing to make these constraints phase independent.
Many clocks of different types catering to various timing requirements may be defined in a timing analysis run. Often, in order to assert a constraint (such as a value adjustment) common to all clocks of a particular type, the same adjustment assertion needs to be applied for every functional clock defined in the system. The number of assertions on a timing point is the same as the number of clocks in a given clock type. Any new clock addition to the existing clock type requires assertions to be applied for the newly created clock. If later in the flow another clock is defined for an existing clock type, in traditional timing analysis the newly defined clock does not receive the correct assertion. It is often difficult to recognize missing assertions and looking at the assertions applied in a traditional timing run does not clearly state the intent of the assertion, and intent is lost among these plurality of assertions.
In an example intent based procedure, “don't care” signals for a particular clock type of clock may be desired with an intent to disable timing for scan signals on a functional pin or disable functional signals on a scan pin of the integrated circuit. Other intent based procedures include renames for clock division, cloning from functional to scan, ABIST, and GA margin. Capturing these assertions as part of an abstract model and accurately applying them in-context requires some post-processing to make the assertions clock domain independent.
One or more embodiments described herein provide for performing timing analysis of a digital integrated circuit using intent based timing constraints. In an embodiment, a plurality of intent based groups are defined for an integrated circuit design such as a functional intent group, a scan intent group, an ABIST intent group, a GA margin intent group, etc. Each clock phase of a plurality of clocks of the integrated circuit design is assigned to or associated with one or more of the intent groups. Timing constraints are defined with respect to each of the intent groups. During timing propagation, propagated clock phases are mapped to intent groups and the associated timing constraints are applied to the timing signals to compute one or more timing results. Constraints for a category (i.e., intent group) cover any current and further clocks defined in that category. Intent based constraints and assertions based on intent groups are captured as-is from lower level design as part of an abstract model for use in in-context analysis for upper level designs. The necessity for post-processing of constraints is avoided.
Various embodiments allow for timing assertions to be defined based on intent, e.g., for a clock type. An assertion for a clock type covers any current and future clock defined in that clock type. This removes order dependency allowing assertions to become incremental in nature. For example, a timer can apply correct assertions with a change in clocks in a particular clock type. Traditionally, designers have to apply assertion on all clocks defined of a particular clock type for a particular timing point, and have to keep track of new clock definitions or new clocks reaching a particular timing point to result in a correct final set of assertions. Various embodiments using intent base assertions allow for more intuitive, dynamic, and robust assertions in integrated circuit design. Capturing these assertions for in-context model usage becomes more straightforward and does not require extra post-processing.
Various embodiments are applicable for both incremental and non-incremental timing analysis. Various embodiments are further applicable to both deterministic and statistical timing analysis. Various embodiments provide for more efficient design of integrated circuits. For example, a rules design team is made aware of how a particular cell/pin is supposed to be used, and any intent assertions can be specified as part of standard cell rules. In another example, a designer can specify timing constraints in a concise and intuitive manner for definition specific and instance specific assertions that may be derived from, e.g., a keyword setting by the designer that results in intention based assertions in timing. In another example, a flow developer does not need to be concerned about where the assertions are applied.
In a particular embodiment, a timer processes the intent based assertions as part of incremental timing analysis which eliminates a requirement of reapplication of native or callback assertions. In a particular embodiment, propagation of intent based assertions as part of an abstracted model is made easier because the size of the abstract commands are reduced as well as the required work in a post-processing step to make phase independent abstracts. Intent based assertions are phase independent by nature.
Accordingly, a “don't care” status of each pin of Latch2 (204) and Latch3 (206) is explicitly configured for each phase of the functional and scan phases of the clock.
In one or more embodiments, a functional intent group is defined for the functional clock type and a scan intent group is defined for the scan clock type. An example command structure according to an embodiment is as follows:
Accordingly, the “don't care” status of the data port (D) pin of Latch2 (204) for all scan clock types and the “don't care” status of the scan port (S) pin of Latch3 (206) for all functional clock types are configured using a single command for each.
In one or more embodiments, a functional intent group is defined for the functional clock type and an ABIST intent group is defined for the ABIST clock type. An example command structure according to an embodiment is as follows:
In a similar example scenario, a GA margin phase on an output of a GA margin launch latch Latch1 (302) is cloned to Latch2 (304). An example traditional command structure is as follows:
In one or more embodiments, a functional intent group is defined for the functional clock type and a GA margin intent group is defined for the GA margin clock type. An example command structure according to an embodiment is as follows:
In the traditional implementation, assertions are static and do not work with new propagated phases. The new functional clock Mnew+ at Latch2/Clk results in Mnew@L at Latdch2/Q. The intended cloning of Mnew@L to AB_Mnew@L does not happen with incremental phase propagation. In contrast, in an embodiment incremental assertions are handled correctly. For example, new functional clock Mnew+ at Latch2/Clk results in Mnew@L at Latch2/Q. Cloning of Mnew@L to AB_Mnew@L is done as part of incremental phase propagation.
For further explanation,
The method of
The method of
The method of
For further explanation,
The method of
For further explanation,
The method of
The method of
The method of
The method of
In an example timing analysis with intent based timing constraints in accordance with an embodiment includes an exemplary constraint of “don't care” timing phases on a timing point. A “don't care” constraint for an intent group is applied on the timing point and the constraint is saved on the timing point with an intent group index to facilitate quick access. The intent group is defined earlier in the timing flow and a unique category index is established for the intent group.
In analysis step of “get timing phases on a timing point”, clock phases propagating from timing segments to a timing point are collected. For each such propagated phase, a timer checks whether the phase has a “don't care” constraint. With intent group constraints, the timer checks for the presence of an intent-group specific “don't care” constraint for the intent group associated with the clock phase. The category index from the propagated phase is matched with the category index saved in the constraint on the timing point. The association of a category with its index is used for faster access times. If such a “don't care” constraint is found, that timing phase is not propagated forward in a timing graph.
An incremental change upstream from the timing point previously analyzed results in queueing the timing point for recalculation of timing phases, and the analysis step will be performed again to obtain an updated list of timing phases for forward propagation.
In view of the explanations set forth above, readers will recognize that the benefits of performing timing analysis of a digital integrated circuit using intent based timing constraints according to embodiments of the present disclosure include:
Exemplary embodiments of the present disclosure are described largely in the context of a fully functional computer system for performing timing analysis of a digital integrated circuit using intent based timing constraints. Readers of skill in the art will recognize, however, that the present disclosure also may be embodied in a computer program product disposed upon computer readable storage media for use with any suitable data processing system. Such computer readable storage media may be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the disclosure as embodied in a computer program product. Persons skilled in the art will recognize also that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present disclosure.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present disclosure without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.
