Claims
- 1. A video synchronization circuit for synchronizing a clock signal with a received sync signal, wherein the sync signal has a binary value alternating between logical zero and logical one, wherein the sync signal is characterized by a repetition period, and wherein the sync signal alternates between an uninverted state in which the sync signal has a duty cycle less than 50% for a first number of consecutive repetition periods and an inverted state in which the sync signal has a duty cycle greater than 50% for a second number of consecutive repetition periods, said video synchronization circuit comprising:
- a sync input for receiving the sync signal;
- a sampling circuit having an input connected to the sync input and having an output at which the sampling circuit supplies a periodic sample of the value of the sync signal at a periodic sampling time which is offset relative to the beginning of each repetition period by an amount of time such that, during periods when the sync signal is uninverted, the value of the sync signal at said periodic sampling time is logical zero, and such that, during periods when the sync signal is inverted, the value of the sync signal at said periodic sampling time is logical one;
- a first phase locked loop circuit having an input connected to the sync input and having an output at which the phase locked loop circuit produces a first clock signal which is phase locked with the sync signal;
- a first shift register having a clock input, a data input, and a plurality of shift register stages, wherein the clock input of the first shift register is connected to the output of the first phase locked loop circuit, and wherein the data input of the first shift register is connected to the output of the sampling circuit.
- 2. A video synchronization circuit according to claim 1, wherein the sampling circuit further comprises:
- a timing circuit for producing a periodic sampling pulse at said periodic sampling time; and
- an AND gate having an output and first and second inputs, wherein the output of the AND gate is connected to the data input of the first shift register, the first input of the AND gate is connected to the sync input, and the second input of the AND gate is connected to receive the sampling pulse from the timing circuit.
- 3. A video synchronization circuit according to claim 2, wherein:
- the timing circuit further comprises
- a second phase locked loop circuit having an input connected to receive the first clock signal from the first phase locked loop circuit and having an output at which the second phase locked loop circuit produces a second clock signal having a repetition period which is a submultiple of the repetition period of the first clock signal, and
- a second shift register having a clock input and a plurality of shift register stages, wherein the clock input of the second shift register is connected to receive the second clock signal from the output of the second phase locked loop, and wherein the second shift register produces a "walking one" pattern in its shift register stages in response to the second clock signal; and
- an output of one of the stages of the second shift register is connected to supply the sampling pulse to the second input of the AND gate.
- 4. A video synchronization circuit according to claim 3, wherein said one stage of the second shift register is a stage whose output has a value of logical one during repetition periods of the sync signal that overlap said periodic sampling time and has a value of logical zero during all other repetition periods of the sync signal.
- 5. A video synchronization circuit according to claim 3, wherein the first and second phase locked loop circuits are the same phase locked loop circuit.
- 6. A video synchronization circuit according to claim 1, further comprising:
- a flip flop circuit having a set input, a reset input, and an output, wherein the set input of the flip flop circuit is connected to the output of the sampling circuit, and wherein the output of the flip flop circuit is connected to the data input of the first shift register; and
- an OR gate having an output and a plurality of inputs, wherein the output of the OR gate is connected to the reset input of the flip flop circuit, and wherein the respective inputs of the OR gate are connected to respective outputs of the first N stages of the first shift register, where N is a positive integer.
- 7. A video synchronization circuit according to claim 6, wherein the sampling circuit further comprises:
- an AND gate having an output and first and second inputs, wherein the output of the AND gate is connected to provide said periodic sample to the set input of the flip flop circuit, and the first input of the AND gate is connected to the sync input;
- a second phase locked loop circuit having an input connected to receive the first clock signal from the first phase locked loop circuit and having an output at which the second phase locked loop circuit produces a second clock signal having a repetition period which is a submultiple of the repetition period of the first clock signal; and
- a second shift register having a clock input and a plurality of shift register stages, wherein
- an output of one of the stages of the second shift register is connected to the second input of the AND gate,
- the clock input of the second shift register is connected to receive the second clock signal from the output of the second phase locked loop, and
- the second shift register produces a "walking one" pattern in its shift register stages in response to the second clock signal.
- 8. A video synchronization circuit according to claim 1, further comprising:
- an OR gate having an output and a plurality of inputs, wherein the output of the OR gate is connected to the data input of the first shift register, and wherein the respective inputs of the OR gate are connected to respective outputs of the first N stages of the first shift register, where N is a positive integer.
- 9. A video synchronization circuit according to claim 8, wherein the integer N is 3.
- 10. A video synchronization circuit according to claim 8, wherein the integer N is greater than or equal to the number of consecutive periods of the first clock signal during which the sync signal remains inverted.
- 11. A video synchronization circuit according to claim 1, wherein:
- the phase locked loop circuit further comprises an enable input such that
- when the enable input receives a signal whose value is logical one, the phase locked loop circuit establishes a repetition period for the clock signal by phase locking the clock signal to the horizontal sync pulses, and
- when the enable input receives a signal whose value is logical zero, the phase locked loop circuit maintains the most recently established repetition period of the clock signal; and
- the video synchronization circuit further comprises an enable circuit for supplying to the enable input of the phase locked loop a signal having a value equal to logical one during some of the periods in which the sync signal is uninverted and a value equal to logical zero during some of the periods during which the sync signal is inverted.
- 12. A horizontal synchronization circuit for synchronizing a clock signal with a received video signal, wherein the video signal has a vertical scan interval periodically alternating with a vertical sync interval, wherein each vertical scan interval includes a first plurality of horizontal sync pulses having a first repetition period, and wherein each vertical sync interval includes a second plurality of horizontal sync pulses having a second repetition period different from the first repetition period, said horizontal synchronization circuit comprising:
- a phase locked loop circuit having a sync input connected to receive the horizontal sync pulses of the video signal, having an output at which the phase locked loop circuit produces a clock signal, and having an enable input such that
- when the enable input receives a signal whose value is logical one, the phase locked loop circuit establishes a repetition period for the clock signal by phase locking the clock signal to the horizontal sync pulses, and
- when the enable input receives a signal whose value is logical zero, the phase locked loop circuit maintains the most recently established repetition period of the clock signal;
- an enable circuit for supplying, to the enable input of the phase locked loop, an enable signal having a value equal to logical one during each vertical scan interval and equal to logical zero during each vertical sync interval.
- 13. A horizontal synchronization circuit according to claim 12, wherein the enable circuit comprises:
- a first shift register having a plurality of shift register stages and having a clock input connected to receive the clock signal from the phase locked loop circuit so as to produce a "walking one" pattern in the stages of the first shift register; and
- a flip flop circuit having a set input, a reset input, and an output, wherein
- the set input of the flip flop circuit is connected to receive an output of a first selected stage of the shift register;
- the reset input of the flip flop circuit is connected to receive an output of a second selected stage of the shift register; and
- the output of the flip flop circuit is connected to supply the enable signal to the enable input of the phase lock loop circuit.
- 14. A horizontal synchronization circuit according to claim 13, wherein:
- the first selected stage of the shift register is a stage whose output is logical one at the beginning of each vertical scan interval; and
- the second selected stage of the shift register is a stage whose output is logical one at the beginning of each vertical sync interval.
- 15. A retrace detection circuit for producing at its output a binary "Retrace Detect" signal whose value is logical one only when a received sync signal is inverted, wherein the sync signal has a binary value alternating between logical zero and logical one, wherein the sync signal is characterized by a repetition period, and wherein the sync signal alternates between an uninverted state in which the sync signal has a duty cycle less than 50% for a first number of consecutive repetition periods and an inverted state in which the sync signal has a duty cycle greater than 50% for a second number of consecutive repetition periods, said retrace detection circuit comprising:
- a phase locked loop circuit having an input connected to receive the sync signal and having an output at which the phase locked loop circuit produces a clock signal which is phase locked to the sync signal so that the clock signal has a repetition period which is a submultiple of the repetition period of the sync signal;
- a shift register having a plurality of shift register stages and having a clock input connected to receive the clock signal from the phase locked loop circuit so as to produce a "walking one" pattern in the stages of the shift register; and
- an AND gate having an output, having a first input connected to receive the sync signal, and having a second input connected to an output of one of the stages of the shift register;
- wherein the output of the AND gate is connected to supply said output of the retrace detection circuit.
- 16. A retrace detection circuit according to claim 15, wherein said one stage of the shift register is a stage whose output has a value of logical one during repetition periods of the sync signal that overlap said periodic sampling time and has a value of logical zero during all other repetition periods of the sync signal.
- 17. A method of synchronizing a "walking one" pattern in a shift register with a period when a received sync signal is inverted, wherein the sync signal has a binary value alternating between logical zero and logical one, wherein the sync signal is characterized by a repetition period, and wherein the sync signal alternates between an uninverted state in which the sync signal has a duty cycle less than 50% for a first number of consecutive repetition periods and an inverted state in which the sync signal has a duty cycle greater than 50% for a second number of consecutive repetition periods, said method comprising the steps of:
- receiving said sync signal;
- producing a first clock signal having a repetition period synchronized with the repetition period of the sync signal;
- providing a first shift register having a clock input, a data input, and a plurality of shift register stages;
- coupling the first clock signal to the clock input of the first shift register;
- periodically sampling the value of the sync signal at a time which is offset relative to the beginning of each repetition period by an amount of time such that, during periods when the sync signal is uninverted, the value of the sync signal at said periodic sampling time is logical zero, and during periods when the sync signal is inverted, the value of the sync signal at said periodic sampling time is logical one; and
- coupling said periodically sampled value of the sync signal to the data input of the first shift register.
- 18. A method according to claim 17, wherein the step of periodically sampling the sync signal further comprises the steps of:
- producing a second periodic clock signal having a repetition period which is a submultiple of the repetition period of the first clock signal;
- providing a second shift register having a clock input and a plurality of shift register stages;
- coupling the second clock signal to the clock input of the second shift register so as to produce a "walking one" pattern in the stages of the second shift register; and
- periodically producing said sampled value of the sync signal by the step of
- producing the logical AND of the sync signal and an output of a selected one of the stages of the second shift register.
- 19. A method according to claim 18, wherein the step of producing said logical AND further comprises the step of:
- selecting, as said selected one stage of the second shift register, a stage of the second shift register having a logical one output during repetition periods of the sync signal that overlap said periodic sampling time and having a logical zero output during all other repetition periods of the sync signal.
- 20. A method according to claim 17, further comprising the steps of:
- providing a flip flop circuit having a set input, a reset input, and an output;
- coupling said periodically sampled value of the sync signal to the set input of the flip flop circuit;
- coupling the output of the flip flop circuit to the data input of the first shift register; and
- applying to the reset input of the flip flop circuit a logical signal whose value is the logical OR of the respective outputs of the first N stages of the first shift register, where N is a positive integer.
- 21. A method according to claim 20, wherein the step of periodically sampling the value of the sync signal comprises the steps of:
- producing a second periodic clock signal having a repetition period which is a submultiple of the repetition period of the first clock signal;
- providing a second shift register having a clock input and a plurality of shift register stages;
- coupling the second clock signal to the clock input of the second shift register so as to produce a "walking one" pattern in the stages of the second shift register; and
- producing said periodically sampled value of the sync signal by the step of
- producing the logical AND of the sync signal and an output of a selected one of the stages of the second shift register.
- 22. A method according to claim 21, wherein the step of producing said logical AND further comprises the step of:
- selecting, as said selected one stage of the second shift register, a stage of the second shift register having a logical one output during repetition periods of the sync signal that overlap said periodic sampling time and having a logical zero output during all other repetition periods of the sync signal.
- 23. A method according to claim 17, further comprising the steps of:
- applying a logical zero value signal to the data input of the first shift register, regardless of the sampled value of the sync signal, when any of the first N stages of the first shift register has a logical one output, wherein N is a positive integer.
- 24. A method according to claim 23, wherein the integer N is 3.
- 25. A method according to claim 23, wherein the integer N is greater than or equal to the number of consecutive periods of the first clock signal during which the sync signal remains inverted.
- 26. A method according to claim 17, wherein the step of producing the first clock signal further comprises the steps of:
- during at least a portion of the periods during which the sync signal is uninverted, establishing the repetition period of the first clock signal by phase locking the first clock signal to the sync signal; and
- during at least a portion of the periods during which the sync signal is inverted, maintaining the repetition period of the first clock signal equal to the repetition period established during the step of establishing the repetition period, wherein said maintaining is performed without regard to the repetition period of the sync signal during said portion of the periods during which the sync signal is inverted.
- 27. A method of phase locking a clock signal with a horizontal sync pulse within a received video signal, comprising the steps of:
- receiving a video signal having a vertical scan interval periodically alternating with a video sync interval, wherein
- each video scan interval includes a first plurality of horizontal sync pulses having a first repetition period, and
- each vertical sync interval includes a second plurality of horizontal sync pulses having a second repetition period different from the first repetition period;
- producing a clock signal characterized by a repetition period;
- during each video scan interval, establishing the repetition period of the clock signal by phase locking the clock signal with said first plurality of horizontal sync pulses; and
- during each vertical sync interval, maintaining the repetition period of the clock signal equal to the repetition period established during the step of establishing the repetition period.
- 28. A method according to claim 27, wherein:
- the step of establishing the repetition period by phase locking the clock signal further comprises the steps of
- supplying an Enable binary signal to an Enable input of a phase locked loop circuit, and
- setting the Enable signal to logical one at the beginning of each video scan interval; and
- the step of maintaining the repetition period further comprises the step of
- resetting the Enable signal to logical zero at the beginning of each vertical sync interval.
- 29. A method according to claim 27, further comprising the steps of:
- providing a first shift register having a clock input and a plurality of shift register stages; and
- coupling the clock signal to the clock input of the first shift register so as to produce a "walking one" pattern in the stages of the first shift register;
- wherein the step of establishing the repetition period by phase locking the clock signal further comprises the steps of
- supplying an Enable binary signal to an Enable input of a phase lock loop circuit, and
- setting the Enable signal to logical one when a first selected stage of the shift register has a logical one output; and
- wherein the step of maintaining the repetition period further comprises the step of
- resetting the Enable signal to logical zero when a second selected stage of the shift register has a logical one output.
- 30. A method according to claim 29, wherein the step of establishing the repetition period by phase locking the clock signal further comprises the steps of:
- providing a flip flop having a set input, a reset input, and an output;
- coupling the output of the flip flop to the Enable input of the phase lock loop circuit;
- coupling the set input of the flip flop to receive the output of the first selected stage of the shift register; and
- coupling the reset input of the flip flop to receive the output of the second selected stage of the shift register.
- 31. A method according to claim 29, further comprising the steps of:
- selecting, as the first selected stage of the shift register, a stage whose output is logical one at the beginning of each vertical scan interval; and
- selecting, as the second selected stage of the shift register, a stage whose output is logical one at the beginning of each vertical sync interval.
- 32. A method of producing a binary "Retrace Detect" signal whose value is logical one only when a received sync signal is inverted, wherein the sync signal has a binary value alternating between logical zero and logical one, wherein the sync signal is characterized by a repetition period, and wherein the sync signal alternates between an uninverted state in which the sync signal has a duty cycle less than 50% for a first number of consecutive repetition periods and an inverted state in which the sync signal has a duty cycle greater than 50% for a second number of consecutive repetition periods, said method comprising the steps of:
- receiving said sync signal;
- producing a periodic clock signal which is phase locked to the sync signal so that the clock signal has a repetition period which is a submultiple of the repetition period of the sync signal;
- providing a shift register having a clock input and a plurality of shift register stages;
- coupling the clock signal to the clock input of the shift register so as to produce a "walking one" pattern in the stages of the shift register; and
- producing said Retrace Detect signal by producing the logical AND of the sync signal and an output of a selected one of the stages of the shift register.
- 33. A method according to claim 32, further comprising the step of:
- selecting, as said selected one stage of the shift register, a stage whose output has a value of logical one during repetition periods of the sync signal that overlap said periodic sampling time and has a value of logical zero during all other repetition periods of the sync signal.
Parent Case Info
This application is a continuation of application Ser. No. 08/372,413 filed Jan. 13, 1995, now U.S. Pat. No. 5,638,085.
Government Interests
This invention was made with Government support under Contract No. DABT63-93-C-0025 awarded by Advanced Research Projects Agency (ARPA). The Government has certain rights in this invention.
US Referenced Citations (18)
Non-Patent Literature Citations (2)
Entry |
"The NTSC Color Television Standards", Proceedings of the I.R.E., Jan. 1954, pp. 46-48. |
"NTSC Signal Specifications", Proceedings of the I.R.E., Jan. 1954, pp. 17-19. |
Continuations (1)
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372413 |
Jan 1995 |
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