The disclosure relates to a display device. In particular, the disclosure relates to a timing controller and a polarity control method thereof.
For a liquid-crystal display (LCD), a common voltage Vcom is a reference voltage for liquid crystal rotation. In a sub-pixel circuit of a display panel, two electrodes of a liquid crystal capacitor are respectively applied with the common voltage Vcom and a grayscale voltage to rotate liquid crystal molecules. When liquid crystal electrodes are applied with different grayscale voltages, the liquid crystal may rotate at different angles, providing different light transmittances. Ideally, the common voltage Vcom is constant. Practically, however, a level of the common voltage Vcom may drift due to the coupling effects. If the common voltage Vcom is not stable, the actual brightness of the sub-pixel circuit may be different from a target brightness. How to reduce the level drift of the common voltage Vcom is one of many technical issues in the related technical field.
The disclosure provides a timing controller and a polarity control method thereof to reduce a level drift of a common voltage of a display panel.
In an embodiment of the disclosure, the timing controller includes a line buffer and a check circuit. The line buffer is configured to temporarily store a plurality of sub-pixel data of a current sub-pixel row in an image frame so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. The check circuit is configured to generate a polarity command corresponding to the current sub-pixel row for the source driver to set a polarity inversion mode of the current sub-pixel row. The check circuit checks the plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row.
In an embodiment of the disclosure, the polarity control method includes the following. A plurality of sub-pixel data of a current sub-pixel row in an image frame is temporarily stored by a line buffer of the timing controller so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. The plurality of sub-pixel data of the current sub-pixel row is checked by a check circuit of the timing controller so as to determine whether to dynamically change a polarity inversion mode of the current sub-pixel row. A polarity command corresponding to the current sub-pixel row is generated by the check circuit for the source driver to set the polarity inversion mode of the current sub-pixel row.
In an embodiment of the disclosure, the timing controller includes a line buffer and a check circuit. The line buffer is configured to temporarily store a plurality of sub-pixel data of a current sub-pixel row in an image frame so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. The check circuit is configured to check whether a polarity inversion mode of a previous sub-pixel row in the image frame is changed from a default mode to a new mode. The check circuit generates a polarity command corresponding to the current sub-pixel row for the source driver to set a polarity inversion mode of the current sub-pixel row. In the case where the polarity inversion mode of the previous sub-pixel row is changed from the default mode to the new mode, the check circuit maintains the polarity inversion mode of the current sub-pixel row in the default mode. In the case where the polarity inversion mode of the previous sub-pixel row is maintained in the default mode, the check circuit checks the plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row.
In an embodiment of the disclosure, the polarity control method includes the following. A plurality of sub-pixel data of a current sub-pixel row in an image frame is temporarily stored by a line buffer of the timing controller so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. Whether a polarity inversion mode of a previous sub-pixel row in the image frame is changed from a default mode to a new mode is checked by a check circuit of the timing controller. In the case where the polarity inversion mode of the previous sub-pixel row is changed from the default mode to the new mode, a polarity inversion mode of the current sub-pixel row is maintained in the default mode by the check circuit. In the case where the polarity inversion mode of the previous sub-pixel row is maintained in the default mode, the plurality of sub-pixel data of the current sub-pixel row is checked by the check circuit so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row. A polarity command corresponding to the current sub-pixel row is generated by the check circuit for the source driver to set the polarity inversion mode of the current sub-pixel row.
Based on the foregoing, the timing controller according to the embodiments of the disclosure may perform line-based polarity control. For example, in some embodiments, the determination/adjustment of the polarity inversion modes of different sub-pixel rows may be independent of each other. The timing controller may check a plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row. For example, the timing controller may select one of the plurality of candidate polarity inversion modes as the polarity inversion mode of the current sub-pixel row according to the plurality of sub-pixel data of the current sub-pixel row, to maximally reduce the coupling effects of the plurality of driving voltages (grayscale voltages) of the current sub-pixel row on the common voltage of the display panel. Therefore, the timing controller may reduce the level drift of the common voltage.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The term “coupling (or connection)” as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if it is herein described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through other devices or some connection means. Terms such as “first” and “second” mentioned through out the specification (including the claims) are used to name elements, or to distinguish between different embodiments or scopes, and are not used to limit the upper or lower bound of the number of elements, nor used to limit the sequence of elements. In addition, wherever possible, elements/members/steps using the same reference numerals in the drawings and embodiments denote the same or similar parts. Cross-reference may be made to relevant descriptions of elements/members/steps using the same reference numerals or using the same terms in different embodiments.
A source driver may convert a plurality of sub-pixel data of the current sub-pixel row into a plurality of driving voltages (grayscale voltages), and then output the driving voltages to different data lines (also referred to as source lines) of a display panel. The symbol “+” as shown in the upper part UP1 of
The lower part DN1 of
In the embodiment shown in
For example, the check circuit 220 may perform the process shown in
In some practical application examples, the filtering condition may include “a certain target sub-pixel data among the plurality of sub-pixel data of the current sub-pixel row is less than a threshold”. The check circuit 220 may classify the target sub-pixel data meeting the filtering condition into the statistics target class, and classify the target sub-pixel data not meeting the filtering condition into the non-statistics target class. For example, it may be assumed that a range of the sub-pixel data is 0 to 255 (or other ranges), and the threshold is 55 (or other values). The check circuit 220 may classify sub-pixel data greater than or equal to the threshold “55” into the non-statistics target class, and classify sub-pixel data less than the threshold “55” into the statistics target class.
In some practical application examples, the filtering condition may include “a certain target sub-pixel data among the plurality of sub-pixel data of the current sub-pixel row is greater than a first threshold, or the target sub-pixel data is less than a second threshold”, where the first threshold is greater than the second threshold. The check circuit 220 may classify the target sub-pixel data meeting the filtering condition into the statistics target class, and classify the target sub-pixel data not meeting the filtering condition into the non-statistics target class. For example, it may be assumed that a range of the sub-pixel data is 0 to 255 (or other ranges), the first threshold is 200 (or other values), and the second threshold is 55 (or other values) value). The check circuit 220 may classify sub-pixel data greater than or equal to the first threshold “200” into the statistics target class, classify sub-pixel data between the first threshold “200” and the second threshold “55” into the non-statistics target class, and classify sub-pixel data less than or equal to the second threshold “55” into the statistics target class.
In step S420, the check circuit 220 may apply each of a plurality of candidate polarity inversion modes to the sub-pixel data belonging to the statistics target class to calculate a polarity statistic value of each candidate polarity inversion mode. For example, the check circuit 220 may apply a certain target mode among the candidate polarity inversion modes to the sub-pixel data belonging to the statistics target class in the current sub-pixel row, and then counts a first number of positive polarity sub-pixels and a second number of negative polarity sub-pixels in the sub-pixel data belonging to the statistics target class. The check circuit 220 may calculate a difference between the first number and the second number and take the difference as the polarity statistic value of the target mode.
For example,
The check circuit 220 may apply each of the candidate polarity inversion modes 510 and 520 to the sub-pixel data belonging to the statistics target class to calculate the polarity statistic value of each candidate polarity inversion mode. Assuming that the current sub-pixel row is the m-th sub-pixel row in the image frame, and the vertical axis polarity period of the candidate polarity inversion mode is n (where n is 4 in the embodiment of
For example, the check circuit 220 may apply the candidate polarity inversion mode 520 to the sub-pixel data belonging to the statistics target class in the current sub-pixel row, and then counts a first number of positive polarity sub-pixels and a second number of negative polarity sub-pixels in the sub-pixel data belonging to the statistics target class. Taking
In addition, the check circuit 220 may apply the candidate polarity inversion mode 510 to the sub-pixel data belonging to the statistics target class in the current sub-pixel row, and then counts a first number of positive polarity sub-pixels and a second number of negative polarity sub-pixels in the sub-pixel data belonging to the statistics target class.
In step S430, the check circuit 220 may select one of the candidate polarity inversion modes as the polarity inversion mode of the current sub-pixel row based on the polarity statistic values of the candidate polarity inversion modes. For example, the check circuit 220 may select a minimal polarity statistic value from the polarity statistic values of the candidate polarity inversion modes, and the check circuit 220 may select a candidate polarity inversion mode corresponding to the minimal polarity statistic value as the polarity inversion mode of the current sub-pixel row. Taking the candidate polarity inversion modes 510 and 520 as shown in
The specific embodiment of step S320 as shown in
The check circuit 220 may binarize the plurality of sub-pixel data of the current sub-pixel row to generate a binarized row. The check circuit 220 may perform the PDF on the binarized row to determine whether the binarized row matches a first characteristics matrix. When a first result of the PDF indicates that the binarized row matches the first characteristics matrix, the check circuit 220 may take a first candidate polarity inversion mode (e.g., the candidate polarity inversion mode 510 as shown in
In summary of the above, the check circuit 220 may dynamically change the polarity inversion modes of different sub-pixel rows to perform line-based polarity control (Line based polarity inversion mode adjustment). For example, the check circuit 220 may check the sub-pixel data of the current sub-pixel row in a statistical manner, and then dynamically change/determine the polarity inversion mode of the current sub-pixel row based on the statistical result. Determination of the polarity inversion mode of the current sub-pixel row in the image frame may be independent of (unrelated to) determination of the polarity inversion mode of a previous sub-pixel row in the image frame. Nonetheless, based on the practical applications, in other embodiments, determination of the polarity inversion mode of the current sub-pixel row may depend on determination of the polarity inversion mode of the previous sub-pixel row. For example, in the case where the polarity inversion mode of the previous sub-pixel row is changed from a default mode to a new mode, regardless of the result of the check circuit 220 checking the plurality of sub-pixel data of the current sub-pixel row, the check circuit 220 maintains the polarity inversion mode of the current sub-pixel row in the default mode. In the case where the polarity inversion mode of the previous sub-pixel row is maintained in the default mode, the check circuit 220 dynamically changes the polarity inversion mode of the current sub-pixel row according to the result of checking the plurality of sub-pixel data of the current sub-pixel row (see the relevant description of
In summary of the above, the timing controller 200 may perform line-based polarity control. The timing controller 200 may check the plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row. For example, the timing controller 200 may select one of the plurality of candidate polarity inversion modes as the polarity inversion mode of the current sub-pixel row according to the plurality of sub-pixel data of the current sub-pixel row, to maximally reduce the coupling effects of the plurality of driving voltages (grayscale voltages) of the current sub-pixel row on the common voltage Vcom of the display panel 30. Therefore, the timing controller 200 may reduce the level drift of the common voltage Vcom.
In the embodiment shown in
Depending on different design requirements, in some embodiments, the check circuit 220 and/or 820 may be realized as a hardware circuit. In other embodiments, the check circuit 220 and/or 820 may be realized as firmware, software (i.e., programs), or a combination of them. In other embodiments, the check circuit 220 and/or 820 may be realized as a combination of multiple of hardware, firmware, and software.
In terms of hardware form, the check circuit 220 and/or 820 may be realized as a logic circuit on an integrated circuit (IC). For example, the relevant functions of the check circuit 220 and/or 820 may be realized as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and/or other processing units. The relevant functions of the check circuit 220 and/or 820 may be realized as hardware circuit, such as various logic blocks, modules, and circuits in an IC, by utilizing hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.
In terms of software form and/or firmware form, the relevant functions of the check circuit 220 and/or 820 may be realized as programming codes. For example, the check circuit 220 and/or 820 may be realized by utilizing general programming languages (e.g., C, C++, or assembly language) or other suitable programming languages. The programming codes may be recorded/stored in a “non-transitory computer readable medium”. In some embodiments, the non-transitory computer readable medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes a memory card, read only memory (ROM), flash memory, a programmable logic circuit, or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. Electronic equipment (e.g., a central processing unit (CPU), a controller, a microcontroller, a or microprocessor) may read and execute the programming codes from the non-transitory computer readable medium so as to realize the relevant functions of the check circuit 220 and/or 820.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.