Patent Application
20130106996
This application claims the benefit of Taiwan application Serial No. 100139656, filed Oct. 31, 2011, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a timing controller, and more particularly to a timing controller with video format conversion, a method therefor and a display system.
2. Description of the Related Art
A conventional liquid crystal display (LCD) system includes a system board and a timing control board. The system board is a front-end core of the display system and is extensively implemented in large-scale integrations. A main processing unit in the system board is a system-on-chip (SoC), which integrates various video interfaces including a high definition multimedia interface (HDMI), a video decoder and a scaler into an integrated chip serving as a core chip.
Current display technology, e.g., the flat-panel display technology, can be categorized into two-dimensional (2D) and three-dimensional (3D) display systems. In order to implement a display system that fulfills 2D and 3D display requirements, it is necessary that the system board of a conventional display system be redesigned to provide video signals compliant to a target format of a 3D display panel. The system board needs to further satisfy specific standards of a timing controller board compliant to the target format, so as to provide timing control signals to the 3D display panel by the timing controller board to drive the 3D display panel for 3D display.
For example, there are two types of 3D display panels supporting the frame sequential format and line alternative format, respectively. Thus, two different system board circuits need to be provided in order to implement the two kinds of display systems utilizing the two types of 3D display panels.
As a result, the overall display system structure is made complicated and inconvenient to manufacture such that the cost of the overall 3D display system is increased. However, the increased cost not only disfavors the manufacturing but also hinders the promotion and public acceptance of the 3D display system.
The invention is directed to a timing controller with video format conversion, a method for a timing controller and a display system. A 3D display system can be implemented by using a timing controller with video format conversion according to an embodiment, thus reducing the complexity of the system circuit complexity of the display system.
According to an aspect of the present invention, a display system is provided. The display system includes a display control unit and a timing control unit. The display control unit receives a video source, generates a digital video signal, and outputs a control signal. The control signal includes a first control signal indicating a 2D display mode or a 3D display mode. The timing control unit, coupled to the display control unit, receives the digital video signal and outputs a 2D output video signal or a 3D output video signal in response to the control signal. The timing control unit includes a 3D data format conversion unit, and outputs the 3D output video signal by the 3D data format conversion unit in response to the first control signal indicating the 3D display mode.
According to another aspect of the present invention, a timing controller with video format conversion is provided. The timing controller is for use in a display panel having a 2D display mode and a 3D display mode. The timing controller includes an input signal switch unit and a 3D data format conversion unit. The input signal switch unit includes an input terminal, at least one first output terminal and at least one second output terminal. The first output terminal of the input signal switch unit is coupled to an output terminal of the timing controller. The 3D data format conversion unit is coupled between the at least one second output terminal of the input signal switch unit and the output terminal of the timing controller. The input signal switch unit receives a control signal. The control signal includes a first control signal indicating a 2D display mode or a 3D display mode. When the first control signal indicates the 2D display mode, the input signal switch unit outputs an input signal from the first output terminal. When the first control signal indicates the 3D display mode, the input signal switch unit outputs an input signal from the at least one second output terminal to the 3D data format conversion unit for display.
According to another aspect of the present invention, a timing control unit of a display is provided. The timing control unit includes the foregoing timing controller and a timing control module. The timing controller is disposed on the timing control module. The timing control module provides a timing control signal and a 3D output signal to a display panel.
According to yet another aspect of the present invention, a method for a timing control unit is provided. The method includes the following steps. A control signal is received. The first control signal indicates a 2D display mode or a 3D display mode. In response to the control signal, a 2D output video signal or a 3D output video signal is outputted by a timing control unit. The timing control unit is coupled between a display panel module and a display control unit. The step of outputting the 2D or 3D output video signal includes the following steps. In response to the first control signal indicating the 2D display mode, a 2D output video signal is outputted; in response to the first control signal indicating the 3D display mode, a 3D output video signal is outputted by a 3D data format conversion unit according to the second control signal.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Embodiments of a timing controller, a method therefor and a display system are described below. In one embodiment, a display system for a timing controller with video format conversion is provided. In a 3D mode, the timing controller receives an input signal having a source format, and outputs a 3D output video signal having a target format in response to a control signal. Thus, with respect to the 3D mode, the timing controller is capable of receiving input signals of different source formats and outputting an output video signal compliant to a target format of a display module. Hence, implementing a 3D display system by using the timing controller can reduce the complexity of its system circuit. For example, a display control unit (e.g., a system board) serving as a video signal processing front end in a display panel, but not compliant to a target format required by 3D display of a 3D display panel, can employ the timing controller according to the embodiment to provide a 3D output video signal compliant to the target format to present 3D display effects by the 3D display panel.
In response to the first control signal S1 indicating the 2D display mode, the timing control unit 120 outputs the 2D output video signal for 2D display. For example, the timing control unit 120 is implemented for detecting the 2D display mode and the 3D display mode according to the first control signal S1. When the 2D display mode is determined (e.g., when the first control signal S1 is at a low level), the timing control unit 120 converts low-voltage differential signaling (LVDS) pixel data provided by the display control unit 110 to a digital video signal, e.g., a mini-LVDS or reduce swing differential signaling (RSDS) signal to drive a data driver of a panel, so as to display a 2D picture on a display panel module 190, e.g., a 3D TFT-LCD panel.
In response to the first control signal S1 indicating the 3D display mode and the second control signal S2, the timing control unit 120 outputs a 3D output video signal V2 for display in the 3D display mode. The digital video signal V1 has a source format, and the 3D output video signal V2 has a target format. For example, when the 3D display mode (e.g., the first control signal S1 is at a high level) is determined by the timing control unit 120, the timing control unit 120 performs 3D format conversion to convert the LVDS pixel data provided by the display control unit 110 to the digital video signal according to the second control signal S2, so as to display a 3D picture on the display panel module 190, e.g., a 3D TFT-LCD panel. According to an indication of the second control signal S2, the timing control unit 120 converts a source format to a target format. For example, the source format is a side-by-side, top-down, or frame-packing 3D format. For example, the target format is a frame sequential or line alternative 3D format. In an alternative embodiment, the timing control unit 120 includes a 3D data format conversion unit (as shown in
According to the embodiment, the display system 10 implementing the structure 100, e.g., a 3D LCD system such as a 3D LCD or television based on a shutter glass or pattern retarder technology, can reduce system circuit complexity.
In an alternative embodiment, the timing control unit 120 of the display in
For example, the input signal switch unit 210 receives a control signal, wherein the control signal includes a first control signal indicating a 2D display mode or a 3D display mode. When the first control signal indicates the 3D display mode, the input signal switch unit 210 outputs the input signal from the at least one second output terminal C2 to the 3D data format conversion unit 220. In another embodiment, the control signal further includes a second control signal. When the first control signal indicates the 3D display mode, the input signal switch unit 210 outputs the input signal from one of the at least one second output terminal C2 according to the second control signal. The number of the second output terminal C2 of the input signal switch unit 210 may be one or multiple. The at least one second output terminal C2 of the input signal switch unit 210 may be coupled to the 3D data format conversion unit 220 to output the output video signal for 3D format conversion in the 3D display mode.
Referring to
Referring to
In one embodiment, the 3D data format conversion unit is implemented to convert an input signal having a source format of a side-by-side format, a top-down format, a frame packing format or a line alternative format to an output video signal having a target format of a frame sequential format. When the target format is a 3D frame sequential format, the frame refresh rate (e.g., 120 Hz) of the 3D output signal is at least twice of the frame refresh rate of an input signal. In one embodiment, the 3D data format conversion unit is implemented to convert an input signal having a source format such as a side-by-side format, a top-down format, a frame packing format or a line alternative format to an output video signal having a target format of a line alternative format. In yet another embodiment, the 3D data format conversion unit is implemented to cover both embodiments above to provide an output video signal having a target format as a line alternative format or a frame sequential format.
In one embodiment, the input signal switch unit 210 in
In one embodiment, the timing controller 200 includes a control unit 230 for receiving a control signal so as to perform mode control and format conversion. In one embodiment, the control unit 230, coupled to the input signal switch unit 210, informs or enables the input signal switch unit 210 to output the input signal V1 from the first output terminal C1 in response to a control signal (e.g., the first control signal S1) indicating the 2D display mode. Also in response to the control signal (e.g., the first control signal S1) indicating the 3D display mode, the control unit 230 informs or enables the input signal switch unit 210 to output the input signal V1 from at least one of the second output terminals C2.
In one embodiment, the control unit 230 includes a mode control interface 231 and a format control interface 240. The mode control interface 231 receives a control signal (e.g., the first control signal S1) and informs the input signal switch unit 231 to enter either the 2D or 3D display mode. In yet another embodiment, in response to the control signal indicating the 3D display mode, the mode control interface 231 informs or activates the format control interface 240. The format control interface 240 receives a control signal (e.g., the second control signal S2) and informs the input signal switch unit 210 to perform the switching of a desired format. In one embodiment, the format control interface 240 further manages data transmission and conversion between the format control interface 240 and the display control unit 110. In one embodiment, the format control interface 240 includes a digital interface 241 and a decoder 243. For example, the digital interface 241 is implemented by a hardware interface supporting a digital interface protocol, e.g., I2C and SPI. The decoder 243 decodes the control signal received by the digital interface 241 into data, a request or a command to inform the input signal switch unit 210 to perform 3D format conversion. The above protocol may also be various types of definition. For example, 2-bit, 4-bit or other data formats are utilized for defining the format conversion. For example, 0001, 0010, 0011 and 0100 respectively represent source formats of a side-by-side format, a top-down format, a frame packing format and a line alternative format; 1000 and 1001 respectively represent target formats of a frame sequential format and a line alternative format.
The control unit 230 may be implemented according to setting and circuit requirements, and other definitions may be used instead of the examples above. For example, the first control signal S1 and the second control signal S2 may be regarded as a control signal or integrated in a control signal. For another example, the input signal switch unit 210 may directly receive a control signal rather than through an additional control unit. For another example, a same digital interface (e.g., I2C or SPI) may be utilized for transmitting and decoding a control signal.
In another embodiment based on
In another embodiment, the control signal (e.g., S1 or S2) can be embedded in a signal stream of the input signal V1 of the input signal switch unit 210, e.g., the control signal is embedded as a header in a signal stream of the input signal V1.
In some embodiments, the timing control unit 120, the input signal switch unit 210 or the 3D data format conversion unit 220 can be implemented by a processor, a digital signal processor, or a programmable integrated circuit such as a microcontroller, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Further in an example, the timing control unit 120 can be integrated as an integrated circuit or integrated with other circuits into a system on chip.
In the above embodiment, for example, the target format is a frame sequential format, a line alternative format, or another format. The format conversion request may indicate a first source format. Embodiments of the target format and the source format may be referred in the description of the foregoing embodiments, and shall be omitted herein.
A timing controller, a method for a timing controller and a display system according to several embodiments are as described above. A timing controller with video format conversion is provided according to one embodiment. Thus, implementation of a 3D display system by using the timing controller can reduce system circuit complexity. For example, a display control unit (e.g., a system board) serving as a video signal processing front end in a display panel, but not compliant to a target format required by 3D display of a 3D display panel, can utilize the timing controller according to the embodiment to provide a 3D output video signal compliant to the target format to present 3D display effects by the 3D display panel.
Therefore, for a manufacturer of a 3D display system such as a display or a television, the circuit complexity of the system board is reduced to simplify the overall system structure. More specifically, even a conventional system board (e.g., a conventional SoC) that cannot directly support 3D video signals or data format conversion is still capable of controlling a timing controller with video format conversion, thereby providing an output video signal compliant to a 3D display panel for display. Such an approach will be of great convenience to the manufacturing of 3D display systems, thus resulting in reduced hardware costs.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 100139656 | Oct 2011 | TW | national |
