Timing generating circuit and digital to analog converter using the same

Abstract

A current-cell type D/A converter using a timing generating circuit for converting a digital code to the corresponding differential voltage Vout between a first analog voltage and a second voltage includes a plural of current cells and a plural of switch-control-signal generating circuits generating each of switch-control signals being provided each of the above current cells. Each of the above current cells includes the switching NMOSs, and the constant-current sources of the NMOSs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1: A view of configuration diagram of main parts of a current-cell type D/A converter showing the first embodiment of the present invention.

FIG. 2: A view of timing chart of the switch-control signals in FIG. 1.

FIG. 3: A view of checking results of effects by simulation of a D/A converter according to the first embodiment and a conventional D/A converter.

FIG. 4: A view of configuration diagram of main parts of a current-cell type D/A converter showing the second embodiment of the present invention.

FIG. 5: A view of timing chart of the switch-control signals in FIG. 4.

FIG. 6: A view of configuration diagram of a switch-control-signal generating circuit showing the third embodiment of the present invention.

FIG. 7: A view of configuration diagram of main parts of a conventional current-cell type D/A converter.

Claims

1. A current-cell type digital-to-analog converter for converting a digital code to the corresponding differential analog voltage between a first and a second analog voltages comprising; a plural of current cells being connected in parallel between a first output line being configured to output said first analog voltage, a second output line being configured to output said second analog voltage and a source-voltage node; anda plural of switch-control-signal generating circuits being formed with respect to each of said current cells and being configured to input said digital code, to generate a first switch-control signal corresponding to said digital code, a second switch-control signal having the opposite phase to said first switch-control signal, a third switch-control signal having a staggered timing to said first switch-control signal, and a forth switch-control signal having a staggered timing to said second switch-control signal, and to provide each of said current cells with said switch-control signals, respectively,wherein each of said current cells includes;a first switch being connected between said first output line and a common node and being turned on/off by said first switch-control signal;a second switch being connected between said second output line and said common node and being turned on/off by said second switch;a first switch device being connected in parallel to said first switch and being turned on/off by said third switch-control signal;a second switch device being connected in parallel to said second switch and being turned on/off by said forth switch-control signal; anda constant current source being connected between said common node and said source voltage node and being configured to supply a predetermined weighed current.

2. The digital-to-analog converter according to claim 1, wherein said first and second output lines are connected to other source voltage node having a different level to said source voltage node through current-voltage conversion devices, respectively.

3. The digital-to-analog converter according to claim 1, wherein said each of switch-control-signal generating circuits are configured to output said first, second, third, and forth switch-control signals having timings to avoid simultaneous off-states of said first, second switches and said first, second switch devices.

4. The digital-to-analog converter according to claim 1, wherein said third switch-control signal comprises a plural of first signals having staggered timings and said first switch device comprises a plural of switches being connected in parallel and turned on/off by said plural of first signals, and said forth switch-control signal comprises a plural of second signals having a staggered timings and said second switch device comprises a plural of switches being connected in parallel and turned on/off by said plural of second signals.

5. The digital-to-analog converter according to claim 1, wherein each of said switch-control-signal generating circuits comprises delay circuits.

6. The digital-to-analog converter according to claim 5, wherein said delay circuits comprise a plural of inverters.

7. The digital-to-analog converter according to claim 5, wherein said delay circuits comprise inverters, resistors, and capacitors.

8. The digital-to-analog converter according to claim 7, wherein said constant current source comprises a plural transistors being serially connected and being in on-sates by a bias voltage.

9. A timing generating circuit comprising; a first transistor being formed on between a first node and a second node and being configured to connect electrically between said first node and said second node in a first period;a second transistor being formed on between a first node and a second node and being configured to connect electrically between said first node and said second node in a second period being slightly staggered from said first period;a third transistor being formed on between said second node and a third node and being configured to connect electrically between said second node and said third node in a third period completely opposite to said first period; anda forth transistor being formed on between said second node and said third node and being configured to connect electrically between said second node and said third node in a forth period completely opposite to said second period.