Timing of non-secured and secured tasks

Abstract

A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, previously described, shows an example of application of the present invention;

FIG. 2, previously described, shows a second example of application of the present invention;

FIG. 3, previously described, very schematically illustrates a conventional example of the sharing of a same processing unit by two operating systems;

FIGS. 4A, 4B, 4C, 4D, and 4E, previously described, illustrate in timing diagrams the operation of the system of FIG. 3;

FIG. 5 very schematically illustrates in the form of blocks a first embodiment of the present invention applied to the sharing of a same processing unit by two operating systems;

FIGS. 6A, 6B, 6C, 6D, and 6E illustrate, in timing diagrams, an embodiment of the present invention applied to the system of FIG. 5; and

FIG. 7 very schematically shows in the form of blocks a second example of embodiment of the present invention applied to the protection of tasks executed by two operating systems.

Claims

1. A method of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters being clocked at the rate of said clock, wherein, on each execution of the second task, the content of the first counter plus or minus a randomly selected offset value is assigned to said second counter.

2. The method of claim 1, wherein each counter is assigned to a different operating system of a processor.

3. The method of claim 2, wherein said first counter is a timer of the processor.

4. A method for sharing a first value of a timer between at least one first counter for timing at least one first task and at least one second counter for timing at least one second task, said counters being clocked at a rate of a same clock and being updated with said first value plus or minus a second value which is different for each counter and which is randomly selected.

5. A method for protecting the duration of at least one first task clocked by at least one first counter, by an analysis of a duration of at least one second task clocked by a second counter, implementing the sharing method of claim 1.

6. A system for sharing a clock between at least one first operating system clocked by at least one first counter and at least one second operating system clocked by a second counter, comprising means for implementing the method of claim 1.

7. A microprocessor comprising the system of claim 6.

8. A system for sharing a first value between at least one first counter for timing at least one first task and at least one second counter for timing at least one second task, comprising means for implementing the method of claim 4.