Timing recovery for data storage channels with buffered sectors

Abstract

A storage channel, e.g., for a disk drive system, may asynchronously sample and buffer an entire sector, and then process the buffered sector to recover timing information. The storage channel may operate in an open-loop and utilize an exhaustive search to determine timing parameters. Alternatively, the storage channel may operative in a closed-loop, processing the sector once, and feeding back information obtained during decoding to the timing loop.

Description

BACKGROUND

In many systems, data is transmitted or retrieved asynchronously, i.e., without any additional timing reference. However, the receiver or detector in the system must eventually process the data synchronously. To do this, the receiver or detector must recover the timing information (e.g., the “clock”) from the data at the receive end.

Timing recovery is becoming a major challenge in data storage channels, such as in disk drive storage systems. As storage capacities and data rates increase, design tradeoffs may require that the storage channels operate in a noisier environment with higher raw error rates. However, more noise and more raw detection errors may make reliable timing recovery more difficult.

SUMMARY

A storage channel, e.g., for a disk drive system, may asynchronously sample and buffer an entire sector and then process the buffered sector to recover timing information. The system may then re-sample the buffered sector using the recovered timing information.

The storage channel may include a read head to read an analog waveform including a number of sectors from a storage medium. A sampler may sample the waveform at the Nyquist rate.

The storage channel may operate in an open-loop and utilize an exhaustive search to determine timing parameters. A timing recovery module may determine coefficients in a polynomial modeling frequency characteristics of the signal. A decoder may decode the buffered sector using a plurality of sets of timing parameters obtained from the exhaustive search and to determine an optimal set of timing parameters. A re-sampling module may then re-sample the buffered sector using the optimal set of timing parameters. The re-sampling module may interpolate data points in the buffered sector in response to the timing information.

In an embodiment, a timing recovery module may process the buffered sector bi-directionally. The timing recovery module may determine a first phase offset using information in a pre-amble of the sector, determine a second phase offset using information in a post-amble of the sector, and then determine a frequency offset from the first phase offset and the second phase offset.

The storage channel may operate in a closed-loop, processing the sector once, and feeding back information obtained during decoding to a timing loop. The timing recovery module may launch the timing loop in a tracking mode using the determined frequency offset. The decoder may decode the re-sampled data points in the buffered sector, and provide timing information obtained from said decoding to the timing loop.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is block diagram of a data storage channel with open-looped timing recovery.

FIG. 2 is a block diagram illustrating a disk drive data sector format.

FIG. 3 is a flowchart describing a timing recovery operation using an open-loop approach.

FIG. 4 is a flowchart describing a timing recover operation using a closed-loop approach.

FIG. 5 is a block diagram of a data storage channel with closed-loop timing recovery.

FIG. 6 is a block diagram illustrating a bi-directional processing data sector format.

FIG. 7 is a flowchart describing a timing recovery operation using a combination open-looped/close-looped approach.

DETAILED DESCRIPTION

FIG. 1 shows a communication channel 100 according to an embodiment. The communication channel may be a data storage channel implemented in a disk drive storage system. A read head may read data from a disk and input the data 102 to the storage channel as an analog waveform.

The data on the disk may be organized in sectors. FIG. 2 shows an exemplary sector format 200. The sector may be 512 bytes (4096 bits) long and include a preamble 202, an address mark 204, and data 206.

FIG. 3 is a flowchart describing a timing recovery operation according to an embodiment. The input waveform may be asynchronously sampled by an analog-to-digital converter 104 (block 302). The storage channel samples the waveform at a sampling rate of at least the Nyquist rate, which is at least twice as fast as the maximum frequency component of the waveform. The Nyquist rate is the sampling rate necessary to cover the complete spectrum of the signal and accurately recover the continuous waveform. Consequently, the storage channel can recover the continuous-time waveform and, if necessary, reconstruct the value of the waveform at any instant by interpolation without loss of information.

In an embodiment, the storage channel may buffer an entire sector in a buffer 106 (block 304). The buffered sector may be processed for timing information by a timing recovery module 108. A re-sampling module 110 may use the recovered clock to re-sample the buffered sector, which may then be processed by a Viterbi detector 112 to estimate the actual signal.

Timing recovery basically deals with two variables: frequency (f) and phase (φ). Once the initial phase offset and frequency offset values are decided, there is a deterministic relationship between the phase and frequency at any time, which is that the phase is the time-integration of the frequency, i.e., $\varphi \left(t\right)={\int }_0^{1}f\left(t\right)dt+\varphi \left(0\right).$

The initial phase offset can be any value between 0 and 1.0 T, where T is the length of one clock cycle. The initial frequency offset is usually very small, with typical values being smaller than +/−0.5%. Also, the frequency drift over the duration of one sector is either a very small value or virtually zero. Therefore, it can be assumed that with regard to the sampling frequency, the data frequency is either constant or a function of time that can be characterized by a low-order (e.g., third order or lower) polynomial.

Since there are only a few parameters to estimate regarding the timing recovery, an exhaustive search may be performed to find the optimal values of these parameters (block 306). The initial phase offset may be estimated using phase acquisition information provided in the preamble of the sector. For example, a Zero Phase Start (ZPS) technique may be utilized. ZPS information may be provided in the preamble at the beginning of a sector. ZPS is a technique that provides a way to quickly determine the sampling phase. A known portion of the signal, e.g., a sinusoidal waveform, may be sampled at four samples per cycle. With zero phase offset, the samples would be taken at the peak and zero crossing points on the waveform. The sampling phase may be determined by calculating the offset between the samples and the peak and zero crossing points.

The ZPS should provide an accurate estimate of the phase offset at the beginning of the sector. Even if exhaustive search is needed to estimate the initial phase offset, the search may be limited to a narrow range around the estimate produced by the ZPS operation and will not be dominant in deciding the complexity of computation. As described above, the frequency characteristics of the sector may be modeled by a low order polynomial (e.g., f(t)=f₀+f₁x+f₂x²+f₃x³). For the exhaustive search of the frequency parameters f₀, f₁, f₂, f₃, the zero-order term, f₀, (i.e., the initial frequency offset) and the first-order term, f₁, (i.e., the drifting rate of the frequency during a sector) will be the most important two terms to decide. Their range of search and accuracy will be the deciding factors for the computational complexity of the exhaustive search. The second- and third-order terms (f₂ and f₃) are likely to be insignificant. The limits, and step size(s), of the exhaustive searches may be predetermined, e.g., set by the disk drive manufacturer based on known tolerances.

A Maximum-likelihood (ML) criterion may be used to determine the optimal parameters. A re-sampled sequence may be generated using the timing decided by each combination of the phase and frequency parameters and loss-free interpolation (block 308). Viterbi detection may then be performed on the re-sampled sequence, and the likelihood of the detected sequence calculated (block 310). The likelihood may be indicated by a metric such as the mean square error (MSE), Euclidian distance, and/or their modified versions with non-linear pattern-dependent effects taken into account. The metric may be stored for each set of parameters (block 312). The optimal set of parameters is the one that gives the maximum likelihood (block 314). The parameters corresponding to the maximum likelihood decision may be provided to the re-sampling module 110 and the buffered sector re-sampled using the optimal set of parameters (block 316).

In the embodiment described above, timing recovery is operating in an open-loop (i.e., without a traditional timing loop). However, the exhaustive search techniques may require a significant amount of computational complexity, which translates into computation time and cost.

In an embodiment, timing recovery may be performed by processing the buffered sector only once (in a bi-directional process) in order to save computational resources. FIG. 4 is a flowchart describing a timing recover operation using a closed-loop approach. The complete sector may be sampled asynchronously at the Nyquist rate (possibly higher) (block 302) and then buffered (block 304). The data storage channel 500 may include a timing loop 502 (e.g., phase locked loop (PLL) 502), as shown in FIG. 5.

The format 600 of the sector may be modified, as shown in FIG. 6, so that the sector can be processed from front-to-back and back-to-front. In many systems, the preamble is used for frequency and phase acquisition, with a length of about 120 bits. In the sector format shown in FIG. 6, the preamble may be shortened to a length just. long enough to perform a reliable ZPS (block 406), even in the presence of a bit error rate (BER) of le⁻¹, e.g., about 16-bits, or 32-bits for a more reliable estimate. Then based on this ZPS, and with a close enough estimation of frequency, the address mark at the beginning of the sector can be detected (block 408). Another address mark 606 and a post-amble 608 may be added to the end of the sector. The post-amble may be just long enough to perform another ZPS (block 410). Based on the ZPS from the post-amble bits, the second address mark can be detected by processing the sector backwards (block 412). Since the time interval between the two address marks can be decided with an accuracy within a fraction of a sampling clock cycle, and the number of data bits between the two address marks is known, a very accurate average frequency offset can be calculated (block 414). If the frequency is not drifting noticeably over one sector, then the calculated average frequency offset can be used as initial frequency offset for the timing loop (block 416). The timing loop can then be launched into the tracking mode (block 418). As long as the initial frequency error is smaller than +/−0.1%, the tracking-mode timing loop can start operating reliably. Timing information may be fed back to the timing loop from the Viterbi detector as it processes the re-sampled and interpolated data points in the buffered sector (block 420).

In alternative embodiments, combinations of the open-looped exhaustive search and the close-looped processing may be used. For example, the bi-directional sector format 600 shown in FIG. 6 can also be used with the open-looped, exhaustive search technique. With the ending phase value and average frequency offset known, the exhaustive search can be performed in much narrower ranges and therefore significantly expedited. FIG. 7 is a flowchart describing a timing recovery operation using a combined open-looped/close-looped approach. A close-looped timing recovery (block 702, shown in detail in FIG. 4) can be performed first by utilizing the information of the averaged frequency offset over a buffered sector. If at the end of the sector, the timing loop appears to have operated normally (block 704), which can be indicated by the end phase value, averaged frequency register value, and abruptness of phase changes, then the history of the frequency register value can be used as a good starting curve and a good indicator of the widths of the ranges for the exhaustive search. Narrowed widths for a range of search based on these indicators may be calculated (block 706), and an open-looped exhaustive search performed in the narrowed ranges (block 708, shown in detail in FIG. 3). The combined open-looped/close-looped approach may improve the overall channel performance by removing timing jitter.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, blocks in the flowcharts may be skipped or performed out of order and still produce desirable results. Accordingly, other embodiments are within the scope of the following claims.

Claims

1-112. (canceled)

113. A method comprising: asynchronously sampling a signal including a sector; buffering the sector; processing the buffered sector to recover timing information, wherein said processing comprises processing the buffered sector bi-directionally; and re-sampling the buffered sector using the timing information.

114. The method of claim 113, wherein the sector includes: a pre-amble; a post-amble; a first address mark after the pre-amble; a second address mark before the post-amble; and a pre-determined number of data bits between the first address mark and the second address mark, and wherein said processing comprising: determining a first phase offset using information in a pre-amble of the sector; determining a second phase offset using information in a post-amble of the sector; finding the first address mark; finding the second address mark; counting a number of samples between the first address mark and the second address mark; and determining a frequency offset from the first phase offset, the second phase offset, the number of samples, and the pre-determined number of data bits.

115. The method of claim 114, further comprising: launching a timing loop in a tracking mode using the determined frequency offset.

116. The method of claim 115, further comprising: decoding the re-sampled data points in the buffered sector; and providing timing information obtained from said decoding to the timing loop.

117. An apparatus comprising: a buffer to receive and buffer an input sampled sector from the sampler; a timing recovery module to recover timing information from the buffered sector, wherein the timing recovery module is operative to process the buffered sector bi-directionally; and a re-sampling module to re-sample the buffered sector using the timing information from the timing recovery module.

118. The apparatus of claim 117, wherein the sector includes: a pre-amble; a post-amble; a first address mark after the pre-amble; a second address mark before the post-amble; and a pre-determined number of data bits between the first address mark and the second address mark, and wherein the timing recovery module is operative to: determine a first phase offset using information in a pre-amble of the sector; determine a second phase offset using information in a post-amble of the sector; find the first address mark; find the second address mark; count a number of samples between the first address mark and the second address mark; and determine a frequency offset from the first phase offset, the second phase offset, the number of samples, and the pre-determined number of data bits.

119. The apparatus of claim 118, further comprising a timing loop, wherein the timing recovery module is operative to launch the timing loop in a tracking mode using the determined frequency offset.

120. The apparatus of claim 119, wherein the decoder is operative to: decode the re-sampled data points in the buffered sector; and provide timing information obtained from said decoding to the timing loop.

121. An apparatus comprising: means for buffering an input sampled sector from the sampler; means for recovering timing information from the buffered sector; means for processing the buffered sector bi-directionally; and means for re-sampling the buffered sector using the timing information from the timing recovery module.

122. The apparatus of claim 121, wherein the sector includes: a pre-amble; a post-amble; a first address mark after the pre-amble; a second address mark before the post-amble; and a pre-determined number of data bits between the first address mark and the second address mark, and further comprising: means for determining a first phase offset using information in a pre-amble of the sector; means for determining a second phase offset using information in a post-amble of the sector; means for finding the first address mark; means for finding the second address mark; means for counting a number of samples between the first address mark and the second address mark; and means for determining a frequency offset from the first phase offset, the second phase offset, the number of samples, and the pre-determined number of data bits.

123. The apparatus of claim 122, further comprising: a timing loop; and means for launching a timing loop in a tracking mode using the determined frequency offset.

124. The apparatus of claim 123, further comprising: means for decoding the re-sampled data points in the buffered sector; and means for providing timing information obtained from said decoding to the timing loop.

125. A computer program comprising: asynchronously sampling a signal including a sector; buffering the sector; processing the buffered sector to recover timing information, wherein said processing comprises processing the buffered sector bi-directionally; and re-sampling the buffered sector using the timing information.

126. The computer program of claim 125, wherein the sector includes: a pre-amble; a post-amble; a first address mark after the pre-amble; a second address mark before the post-amble; and a pre-determined number of data bits between the first address mark and the second address mark, and wherein said processing comprises: determining a first phase offset using information in a pre-amble of the sector; determining a second phase offset using information in a post-amble of the sector; finding the first address mark; finding the second address mark; counting a number of samples between the first address mark and the second address mark; and determining a frequency offset from the first phase offset, the second phase offset, the number of samples, and the pre-determined number of data bits.

127. The computer program of claim 126, further comprising: launching a timing loop in a tracking mode using the determined frequency offset.

128. The computer program of claim 127, further comprising: decoding the re-sampled data points in the buffered sector; and providing timing information obtained from said decoding to the timing loop.

129. A storage system comprising: a read head to read data; and a storage channel to receive said data, the storage channel including a buffer to receive and buffer an input sampled sector from the sampler, a timing recovery module to recover timing information from the buffered sector, wherein the timing recovery module is operative to process the buffered sector bi-directionally, and a re-sampling module to re-sample the buffered sector using the timing information from the timing recovery module.

130. The system of claim 129, wherein the sector includes: a pre-amble; a post-amble; a first address mark after the pre-amble; a second address mark before the post-amble; and a pre-determined number of data bits between the first address mark and the second address mark, and wherein the timing recovery module is operative to: determine a first phase offset using information in a pre-amble of the sector; determine a second phase offset using information in a post-amble of the sector; find the first address mark; find the second address mark; count a number of samples between the first address mark and the second address mark; and determine a frequency offset from the first phase offset, the second phase offset, the number of samples, and the pre-determined number of data bits.

131. The system of claim 130, further comprising a timing loop, wherein the timing recovery module is operative to launch a timing loop in a tracking mode using the determined frequency offset.

132. The system of claim 131, wherein the decoder is operative to: decode the re-sampled data points in the buffered sector; and provide timing information obtained from said decoding to the timing loop.