Claims
- 1. A timing verification system for verifying timing paths in a circuit design including a plurality of interconnected devices comprising:
(A) charge determining means for determining a plurality of charges at a corresponding plurality of specific nodes within a circuit, each of the plurality of charges corresponding to a specific configuration of devices and including model generation means for generating a plurality of models corresponding to said plurality of nodes, each of said plurality of models representing defining a charge within a specific configuration based on characteristics of a device in said specific configuration, each said specific configuration including at least one MOS device having:
(i) a gate connected to either one of a rising voltage input or a falling voltage input; (ii) a source and a drain at a voltage which is in an opposite direction to that to which the gate is connected; and (B) delay determining means for determining delays in paths in a selected circuit design to be verified using selected ones of said plurality of charges corresponding to one of the specific configurations representative of that circuit design.
- 2. The timing verification system of claim 1, wherein such charge determining means includes
charge calculation means for determining a charge for a node in said circuit design based upon one of said plurality of models corresponding to a configuration at said node and characteristics of a device on said node.
- 3. The timing verification system of claim 3, wherein said means for simulating signals simulates signals based upon predetermined operating conditions that include temperature.
- 4. The timing verification system of claim 4, wherein said predetermined operating conditions correspond to operating conditions of said circuit design.
- 5. The timing verification system of claim 3, wherein said means for generating models includes means for applying curve fitting techniques to said charges.
- 6. The timing verification system of claim 3, wherein said means for generating models includes means for determining at least two models corresponding to charges, a first model which exceeds each of the charges determined by simulation, and a second model which is less than each of the charges determined by simulation.
- 7. The timing verification system of claim 2, wherein said models correspond to at least one of a minimum charge at a gate of a device, a maximum charge at a gate of a device, a minimum charge at a drain of a device, and a maximum charge at a drain of a device.
- 8. A timing verification system for verifying timing paths in a circuit design including a plurality of interconnected devices comprising:
(A) charge determining means for determining a plurality of charges at a corresponding plurality of specific nodes within a circuit, each of the plurality of charges corresponding to a specific configuration of devices and including model generation means for generating a plurality of models corresponding to said plurality of nodes, each of said plurality of models representing defining a charge within a specific configuration based on characteristics of a device in said specific configuration, each said specific configuration including at least one MOS device having:
(i) a gate connected to either one of a rising voltage input or a falling voltage input; (ii) at least one of either a source or a drain connected to a Miller effect voltage; and (B) delay determining means for determining delays in paths in a selected circuit design to be verified using selected ones of said plurality of charges corresponding to one of the specific configurations representative of that circuit design.
- 9. The timing verification system as defined in claim 8, wherein the source is at the Miller effect voltage, and the drain is connected to either VSS or VDD.
- 10. The timing verification system as defined in claim 8, wherein the drain is at the Miller effect voltage, and the source is connected to either VSS or VDD.
- 11. The timing verification system of claim 8, wherein said charge determining means includes:
charge calculation means for determining a charge for a node in said circuit design based upon one of said plurality of models corresponding to a configuration at said node and characteristics of a device at said node.
- 12. The timing verification system of claim 11, wherein said model generation means includes:
means for creating a set of configurations of devices; means for simulating signals in said set of configurations for a plurality of characteristic values of said devices; means for determining charges at nodes in said set of configurations of devices based upon said signals; and means for generating models of charges based upon said charges and said plurality of characteristics of said devices.
- 13. The timing verification system of claim 12, wherein said means for simulating signals simulates signals based upon predetermined operating conditions that include temperature.
- 14. The timing verification system of claim 13, wherein said predetermined operating conditions correspond to operating conditions of said circuit design.
- 15. The timing verification system of claim 12, wherein said means for generating models includes means for applying curve fitting techniques to said charges.
- 16. The timing verification system of claim 12, wherein said means for generating models includes means for determining at least two models corresponding to charges, a first model which exceeds each of the charges determined by simulation, and a second model which is less than each of the charges determined by simulation.
- 17. The timing verification system of claim 11, wherein said models correspond to at least one of a minimum charge at a gate of a device, a maximum charge at a gate of a device, a minimum charge at a drain of a device, and a maximum charge at a drain of a device.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation of commonly assigned co-pending U.S. patent application Ser. No. 09/208,780, which was filed on Dec. 10, 1998, by James A. Farrell, et al. for a TIMING VERIFIER FOR MOS DEVICES AND RELATED METHOD, which is now allowed, which was a Continuation of U.S. patent application Ser. No. 09/085,265, filed May 26, 1996, now abandoned, and these are hereby incorporated by reference.
Continuations (2)
|
Number |
Date |
Country |
Parent |
09208780 |
Dec 1998 |
US |
Child |
10218079 |
Aug 2002 |
US |
Parent |
09085265 |
May 1998 |
US |
Child |
09208780 |
Dec 1998 |
US |