Token ID mechanism for network data transfer

Abstract

A node in a network that receives data from a data source, such as another node. The receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. Thus, a token identifier is preferably neither a physical memory address nor a virtual address.

Description

BACKGROUND

1. Field of Invention

The present invention relates to data networking and specifically to receiving data via a high speed network interface.

2. Background of Invention

It is desirable to transfer data over a network in a fast and secure manner. In conventional network data transfer systems, an interface for one or more host computers may communicate over a variety of networks, such as a SCSI or FibreChannel network. In conventional systems, a data request is made and data is sent from a data source to the host's interface. Generally, the interface must wait to receive all data before the data can be processed and the checksum computed. This requirement slows the processing of data.

Ideally, data should be received and passed to the application programs with as little copying as possible since each copy operation has an adverse effect on latency. This concept is known as “zero copy.” In addition, it is desirable to include a checksum in data packets to ensure that the packet has not become corrupted in some way. Many conventional packet protocols include a checksum that includes the transmitted data.

SUMMARY OF INVENTION

A preferred embodiment of the present invention includes a node in a network that receives data from a data source, such as another node. The receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. Thus, a token identifier is preferably neither a physical memory address nor a virtual address. In described embodiments, a token identifier is an integer value that acts as an index into a token array (or table), which identifies the memory location. Alternately, a token identifier can be an ASCII string or other appropriate representation. Thus, the memory location at which data received by the receiving node is not exposed to the data source. This feature increases the security of data transfer. A table indexed by the token identifier could be in memory or on the receiving interface.

In addition, preferred embodiments of the invention validate various portions of the received data, including validating a cut-through checksum found in a received data packet. The cut-through checksum is based on data found in a packet header, and thus can be validated before the entire packet is received. This feature allows processing of the received data to begin before the entire packet has been received. Many embodiments will also receive a checksum that is based on the entire packet.

The features and advantages described in this summary and the following detailed description are not all-inclusive, and particularly, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims hereof. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter, resort to the claims being necessary to determine such inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of a system for practicing some embodiments of the present invention.

FIG. 2 shows an embodiment of a host that contains a plurality of processors and ports.

FIG. 3( a) shows a more detailed example of a node of FIG. 1.

FIG. 3( b) shows details of control and data lines of FIG. 3(a).

FIG. 4( a) shows an overview of data transfer between a sending node and a receiving node.

FIG. 4( b) shows an example of a partial protocol header received from a sending node of FIG. 4(a).

FIG. 4( c) shows an example of a partial protocol header sent to the sending node of FIG. 4(a).

FIG. 5( a) is a block diagram showing a method used to receive a data packet in accordance with a preferred embodiment of the present invention.

FIG. 5( b) is a flow chart showing details of method of FIG. 5(a).

FIG. 6 shows an example format of a received packet including a token identifier.

FIG. 7 shows an example format of a Received TID Array.

FIG. 8 shows an example format of a Receive Header Queue.

FIG. 9 shows an example format of an Eager TID Array.

FIG. 10 shows an example format of a buffer in accordance with the present invention.

FIG. 11 is a flowchart showing a method of processing a checksum in a packet before the entire packet is received.

The figures depict embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 is a block diagram illustrating an example of a system 100 for practicing some embodiments of the present invention. FIG. 1 includes a first node 102, a second node 104, and a network connecting the nodes 130. While most other systems contain more than two nodes only two nodes are shown here for ease of explanation. In the examples that follow, node 102 acts as a receiving node and node 104 acts as a sending node. It will be understood that these roles could be reversed in other circumstances because, in a preferred embodiment, most nodes are capable of both sending and receiving data. In this embodiment, first node 102 includes a host 110 and an I/O interface 112 connected to the host 110. Nodes 102 and 104 communicate via a network 130.

FIG. 2 shows an example of host 110, which contains a plurality of processors 250, 252, 254, 256, 258. The processors are, for example, the Opteron processor from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif. Each processor is associated with a port. In a preferred embodiment, Port 0 is reserved for the operating system kernel (for example, the Linux kernel, version 2.6). One or more applications execute on the processors. In the following discussion, a system and method used by one port to communicate with the interface 104 to receive data will be discussed, although it will be understood that the discussion herein may apply to any of the plurality of ports.

FIG. 3( a) shows a more detailed example of FIG. 1. In FIG. 3(a), host 110 includes a memory 302. Memory 302 contains a buffer, a Receive Header Queue, and a Tail pointer for the Receive Header Queue, each of which is discussed in more detail below. The buffer contains data received via the interface 112 and transferred via Direct Memory Access (DMA) engine 310. In a preferred embodiment, host 110 communicates with interface 112 via a packetized bidirectional bus 202 using a protocol such as the HyperTransport protocol or via a non-packetized bus such as PCI Express, although any appropriate communication bus or protocol may be used. Bus 202 includes appropriate data line (D) and control lines (C). In a preferred embodiment, network 130 is an InfiniBand network.

FIG. 3( b) shows details of control and data lines of FIG. 3(a) implemented for a 16 bit HyperTransport link. Each signal shown is actually a differential pair and the group of all the signals is repeated going from B to A. The Ctl signal indicates whether the data pins are carrying a command (if Ctl is true), or data (if Ctl is false). All data signals preferably are DDR (Double Data Rate), with data on both edges, so that a single 32 bit word is transferred on a 16 bit link each clock cycle. Other currently-defined HyperTransport widths are 8, 2, 4, and 32. Other embodiments may include these widths.

Interface 112, which can be implemented as hardware (e.g., an FPGA or any type of semiconductor chip) or as software also includes decode logic 304 and a Receive Token ID (TID) Array 700 as discussed below in connection with FIG. 7. Some embodiments also include an Eager TID Array 900, as discussed below in connection with FIG. 9.

FIG. 4( a) shows an overview of data transfer between a sending node 104 and a receiving node 102. Initially, the sending node 104 sends a message stating “I've got data” 402. In a preferred embodiment, the sending node uses the Message Passing Interface (MPI) standard, although any appropriate protocol or standard can be used.

FIG. 4( b) shows an example of a partial protocol header in a packet 402 received from a sending node of FIG. 4(a). The header includes, but is not limited to the following fields, which can occur in any appropriate order:

• • host 412—identifier of the sending node/host that wants to send data
  • tag 414—identifier chosen by application
  • type 416—identifies this as a request to send data using TIDs
  • length 418—length of data to be sent

Host 110 communicates a token identifier (TID) to I/O interface 112. A TID identifies a physical location in the host memory, but is not itself a memory address. Interface 112 sends a message stating “Send data to this TID” 404. In certain embodiments, the message to the sender also includes values for the Version, Port, and offset (see memory key 613 of FIG. 6). Certain embodiments also include flags 620.

FIG. 4( c) shows an example of a partial protocol header in a packet 404 received from a receiving node of FIG. 4(a). The header includes, but is not limited to the following fields, which can occur in any appropriate order:

• • sessionID 422—identifies which transfer of one to man in progress
  • numTIDs 424—number of TID entries in this reply that can be used
  • TIDlist 426—list of triplets (num TIDs long)

Each triplet in the TIDlist includes 1) TID, 2) offset in TID buffer, and 3) length of data to put in this ID buffer.

Thus, a long data transmission may require multiple triplet entries in the TIDlist if the protocol used has a limited message size.

Lastly, the sending node sends data packets 406 labeled with the respective TID(s) (or with the entire memory key) sent by the receiving node and the data is DMA'd to the host at the physical memory location identified by the TID(s) (or memory key). In a preferred embodiment, the sending node places the TID(s) (or the memory key) into the packet as shown in FIG. 6. In a preferred embodiment, the sending node breaks long data (e.g., data longer than 2K) into multiple packets and updates the offset field 618 for each of the multiple packets.

One advantage of using a TID in the manner shown in FIG. 4(a) is enhanced security. The sending node only needs to know the identity of the requesting host, but the sending node does not know at what physical location in the host's memory the data will eventually be stored. In fact, the receiving node can change the physical memory addresses associated with a TID with no negative effects since the sending node only knows about the TID. Thus, TIDs are advantageous over both physical memory addresses and over virtual memory addresses because the sending node does not need to know an address at all.

In a preferred embodiment, the TID(s) to use for a particular data transmission is chosen via a least recently used (LRU) free list maintained on the host. The host takes the lesser of the required number, or the number currently available from that list. The list is usually hashed with addresses, so that entries can be reused if desired (to minimize overhead in converting virtual addresses to physical, and programming them in the device).

FIG. 5( a) is a block diagram showing a method used to receive a data packet in accordance with a preferred embodiment of the present invention. When a packet is received from network 130 (such as a Fibre Channel fabric), it passes through the link layer interface 550 and a first portion is temporarily stored in a staging buffer 552. It should be noted that only enough of the packet must be received at this point to perform validation and lookup before starting the cut-through DMA operation as described below. The staging buffer is also the buffer that is DMA'd to the receive header queue, after the payload is DMA'd.

Decode logic 304 (FIG. 3(a)) parses the packet and derives an index into TID array 700, which provides a physical address in the host that is used for a DMA transfer to the host 112 via host interface 554. Control logic 556 communicates with the host to maintain the TID array and to send relevant data to the host, as described below.

FIG. 5( b) is a flow chart showing a method used to receive a data packet in accordance with a preferred embodiment of the present invention. The steps of FIG. 5(b) correspond to element 406 of FIG. 4(a). First, a packet is received 502. The packet contains a token identifier (TID) in its header. Each of the elements of FIG. 5(b) is discussed below.

FIG. 6 shows an example format for a received packet 600. In one embodiment, network 130 is an InfiniBand network, so packet 600 is based on an InfiniBand packet and contains a standard InfiniBand header 602. In other embodiments, the received packet may be of a different type. Header 602 includes a packet length (not shown), which is a standard part of the header 602.

Packet 600 includes a memory header 604, which is shown in detail in FIG. 6. The fields Version 612, Port 614, token identifier (TID) 616, and offset 618 are collectively known as “a memory key” for ease of discussion. The memory key will be used to determine a physical address in host memory where the packet will be copied. The memory header also includes pktflags 620 and a “cut-through checksum” 622, which is discussed below in connection with FIG. 11. Packet 600 also includes a protocol header 606, which is used by software on the host, and a payload 608, which contains the data to be written into host memory.

Version 612 is preferably a 4 bit version, describing a data format of memory header 604. The first version is preferably “1” and all zeroes is not used. This field only changes when the parts of the header parsed by the interface 112 change. Port 614 is preferably a 4 bit value and is checked to ensure that it is less than a known number of ports. Embodiments containing multiple ports in the host preferably will use this field. Token identifier (TID) 616 is preferably 10 bits and is checked to ensure that it is either all ones (eager TID, discussed below) or less than a known TID value. Offset 618 is preferably a 14 bit word offset that is related to a particular implementation discussed below in connection with FIG. 10. Not all embodiments contain this field. PktFlags 620 is preferably 16 bits long. The only defined field that is checked by the interface is KPF_Intr. When this flag is set, the interface will assert an interrupt status flag when the packet has completed DMAing to memory. This flag is set by the sender when it is important that the receiver respond immediately.

Cut-through checksum 622 is preferably a 16 bit checksum field over the InfiniBand header 602 (which contains packet length) and the first two words of the memory header 604.

Protocol header 606 is not looked at by the interface of the described embodiment except to validate the cut-through checksum as described in connection with FIG. 11. Payload 608 contains data to be received.

Returning to FIG. 5(b), the header of the received packet is validated 504. As an example, the packet length (in the InfiniBand header 602) added to the Offset 618 must be less than a host buffer length or the data will be stored past the end of the host buffer, which is undesirable. Other examples of validation include but are not limited to generating a cut-through checksum (see FIG. 10) and comparing it with the cut-through checksum in the received packet; determining whether the received port value 614 represents a valid and enabled port; determining that the version number 612 is valid; and determining that the TID 616 is in a valid range.

In addition, validation preferably includes checking a Valid flag 702 in a Receive TID Array 700 to determine whether the Valid flag is set.

Returning to FIG. 5(b), the token identifier 616 is used as an index into a Receive TID Array 700 for the Port 614 as shown in FIG. 7. In a preferred embodiment, there is a Receive TID Array 700 for each Port as shown in FIG. 2.

FIG. 7 shows an example format of Receive TID Array 700. In the example, the Array has 1024 entries although an appropriate number can be used. Each entry contains a Valid flag 702, indicating; a Buffer Length 704, indicating; and a physical host address 706, indicating a location in the buffer of host 110 where the received data is to be stored. Thus, each TID identifies a location in the host's memory. The Valid Flag 702 indicates whether the entry contains valid information. In a preferred embodiment, the Valid flag is not cleared when a packet is processed, so while a clear Valid flag indicates an error, a set flag does not necessarily indicate lack of an error. The Valid flag is not cleared in the described embodiment because to do so would require a write operation from the host and because of the existence of a 2K byte limit on the data payload that is inherent in InfiniBand. Because of this limitation of payload length, data is sometimes transferred in multiple packets that are associated with the same TID but that have different offset values (see FIG. 10). In this case, it would be incorrect to clear the TID after processing the first of the series of packets.

In a preferred embodiment, if the Valid flag 702 is not set, a received packet will have only its header parts written to the Receive Header Queue 800. In this case, the part of the packet following the words written to the Receive Header Queue 800 will not be written anywhere in host memory and are lost.

Buffer Length 704 is the size in words of the host buffer pointed to by physical host address 706. Physical host address 706 preferably is at least a 40 bit address of the buffer in host memory. The described embodiment supports up to a 48 bit address (although the invention is not thus limited). A current Opteron implementation only supports a maximum of 40 physical addresses, although future versions may support larger address sizes.

As shown in FIG. 5(b), the header is checked against the token identifier 508 and the token identifier is used to set up a host destination 510. The received data (i.e., payload 608) is sent to the host memory via Direct Memory Access (DMA) 512. Then header information is DMA'd to a Receive Header Queue 800.

FIG. 8 shows a Receive Header Queue 800. Each application on the host has its own Receive Header Queue 800. Each Receive Header Queue 800 preferably is located in physically continuous memory. Each entry contains Receive Header Flags 802; the InfiniBand header 602/804; and memory header 604/806, which also includes the protocol header 606 from the received packet. Examples of Receive Header Flags 802 are shown in Table 1. These flags preferably are written by the interface after the rest of the entry is written but always before the Receive Header Tail 808 pointer is updated. It is necessary to wait until the entire packet has been received because some flags, such as the EGP (good packet flag) cannot be set until the entire packet is received.

Next, as shown in FIG. 5(b), the status flags are updated and Receive Header Tail pointer 808 in the interface is updated 516 to indicate that there is a new entry in the Receive Header Queue. Next, the Receive Header Tail pointer 808 in the host is updated. In a preferred embodiment, the host determines that new data is available by polling the Tail pointer 808 for the Receive Header Queue. Thus, while in a preferred embodiment, an application on the host side sets the Receive Head pointer 807 on the host, the interface 112 sets the Receive Tail pointer 808 on the host.

FIG. 9 shows an Eager TID Array 900, which is used in some embodiments of the present invention. Eager TIDs are used for “unexpected” packets, such as a control message, a synchronization message, or a short message sent by a sender node without going through the protocol shown in FIG. 4(a). An Eager TID is indicated by a TID field in the packet having a value of all “1”s. Because the packet is “unexpected,” interface 112 has not sent a TID to be used for the packet. In the described embodiment, short packets do not need to use unexpected/eager mode, but for performance reasons, usually do. Whether a packet is “unexpected” is the most important issue, rather than the length. Also “short” in this context may well mean a user protocol payload of more than one InfiniBand (2 KB) packet. It's a question of the crossover point in copying data, versus overhead involved in setting up the expected TID transfer.

In a preferred embodiment, there is an Eager TID Array 900 for each Port as shown in FIG. 2. Each Eager TID Array 900 preferably contains 512 entries. The Eager TID Array acts as a DMA list in a similar manner to the Received TID Array. In a preferred embodiment, TID entries in the Eager TID Array are used only once and are allocated in a circular fashion. FIG. 10 shows an example of how sending node might break data into a series of packets. This may occur, for example, if the data length exceeds the predetermined payload length of a packet. FIG. 10 shows an example Receive TID Array 1002. In the example, a TID 1 is associated with a 16K buffer at location 12340000. A TID 14 is associated with a 4K buffer at location 4560000. A TID 23 is associated with an 8K buffer at location 7890000. When data is sent from the sending node for TID 1, it is broken into eight 2K packets. The offset in each of these packets is progressively larger, indicating that the received data is to be stored at the memory address identified by TID 1 and offset by the offset value in the corresponding packet. Thus, in the described embodiment, the sending node must be aware of the existence of the memory header field 604 and must take appropriate actions to put the proper values in the field 604.

FIG. 11 is a flowchart showing a method of processing a checksum in a packet before the entire packet is received. As shown in FIG. 6, a received packet 600 includes a cut-through checksum 622. This cut-through checksum 600 is based on certain fields in the header of the received packet, but is not based on the payload data in the packet. The exact fields used to compute a cut-through checksum will vary with implementation. In a preferred embodiment where the packet 600 is an extension of an InfiniBand header (see FIG. 6), the following checks are made before beginning a DMA transfer. The DMA transfer is begun before the entire packet is received, thus decreasing latency. Because a certain amount of checking is performed in connection with the cut-through checksum, it is reasonable to make a tradeoff between increasing latency and making sure that the data being written is accurate before the DMA begins.

In a preferred embodiment, the cut-through checksum (also called a K_Checksum) is sixteen bits although other lengths can be used. The cut-through checksum is preferably computed as follows:

Cut-through Checksum=A+B+C,

or Cut-through Checksum=A+B−C

or Cut-through Checksum=A−B−C−1.

Other appropriate functions f for computing a Cut-through Checksum can be used.

Use of a cut-through checksum determines that enough of a packet has been validated to guarantee that the memory location to which the data transfer is directed (in cut-through fashion) in host memory, is the correct and safe memory location for the packet. To put this another way, if the checksum had not been validated, the packet might have indicated (erroneously) that the data transfer should have been directed to a location in the host memory that was a location reserved for some other packet (overwriting the data of that packet if allowed to continue).

Where A is a LNH (This is preferably a 2 bit field. B is the PktLen field from the InfiniBand header and is preferably an 11 bit field. Link Next Header) field in a LRH (Local Routing Header) in InfiniBand header 602. In one implementation, the bytes in the InfiniBand header are swapped before the checksum is computed. C is formed from a portion of the memory header 604. This preferably includes Version 612, Port 614, TID, 616, Offset 618 and PktFlags 620. Checking these values before beginning the DMA protects all fields that are needed to start transferring data to host memory before the InfiniBand CRC checksum results are known and also validate that the received packet is of the proper type.

It will be understood that various implementations will compute the cut-through checksum differently. For example, an implementation that does not include TIDs will not include a TID value in the checksum. For example, an implementation that does not include offsets will not include an offset in the checksum, and so on. A cut-through checksum is any checksum that is computed using header based data only in order to decrease latency and speed up data transfer.

As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Likewise, the particular naming and division of the modules, features, attributes, methodologies and other aspects are not mandatory or significant, and the mechanisms that implement the invention or its features may have different names, divisions and/or formats. Furthermore, as will be apparent to one of ordinary skill in the relevant art, the modules, features, attributes, methodologies and other aspects of the invention can be implemented as software, hardware, firmware or any combination of the three. Of course, wherever a component of the present invention is implemented as software, the component can be implemented as a standalone program, as part of a larger program, as a plurality of separate programs, as a statically or dynamically linked library, as a kernel loadable module, as a device driver, and/or in every and any other way known now or in the future to those of skill in the art of computer programming. Additionally, the present invention is in no way limited to implementation in any specific programming language, or for any specific operating system or environment. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

TABLE 1
RcvHdrFlags Format
RHF_VCRCErr | RHF_ICRCErr | RHF_LenErr | RHF_MTUErr |
RHF_ParityErr | RHF_KHdrErr | RHF_TIDNotValid | RHF_TIDErr |
RHF_MKErr | RHF_EgrIndex | RHF_IBErr | Reserved |
RHF_RcvType | RHF_Length | RHF_SWA | RHF_SWB |
This describes the format of the first qword of the RcvHdr queue entry.
It is written after the rest of the entry is written in most cases, but
always before the RcvHdrTail pointer is updated.
RHF_VCRCErr, RHF_ICRCErr, and RHF_LenErr are set if the packet
had VCRC, ICRC, or length (LRH length didn't match length as received
from fabric) errors, respectively. They are set as appropriate, independent
of whether error interrupts are enabled. RHF_ParityErr is set if a
parity error was found in the interface memory while copying a packet
to host memory. RHF_IBErr is set if there was an IB low level
packet error (packet received from EBP, Malformed (LVer VL,
GRH_VL15), or flow control error causing IB layer overrun).
RHF_KHdrErr indicates an invalid MemoryHdr (cut-through_Chksum
invalid, or not present due to short length).
RHF_TIDNotValid indicates that the access TID entry did not have its
RT_Valid bit set and that no data was DMA'ed to the buffer specified
by the TID entry.
RHF_TIDErr is sent when RT_BufSize was too small for the received
packet.
RHF_MKErr is set if one or more of the K_Port or
K_TID fields of K_MemKey were not valid (such packets
are always copied to Port 0, since they indicate a programming error).
RHF_EgrIndex is log2 (RcvEgrCnt) bits in length. When the packet
has K_TID all-ones, this is the index in the RcvEgr array on
interface that was used to determine where the data was copied in
main memory. The host then looks at its own copy of this array to find
the matching data.
RHF_RcvType is a 2 bit field indicating received packet type,
with four possible values corresponding to the four possible receive types.
The first (type 0) is when interface finds a valid K_MemKey in
the KeyHdr, with a K_TID not all-ones. This is the MPI expected
receive case. The second (type 1) is when we have a valid K_MemKey,
and all-ones K_TID. This is the MPI eager receive case, as well
as the IP implementation. The third (type 2) is all valid IB packets
(not KD), and the fourth (type 3) is all other packets (those
with some kind of transport or other error).
RHF_Length is an 11 bit field given the length in words
of the packet as received from the fabric, which may not be the same
as that in the LRH. If the received length was too large to fit
in 11 bits (it was larger than the MTU + header + CRCs), then
the field should be set to all ones, and RHF_MTUErr
will also be set.
The RHF_SWA and RHF_SWB flags are reserved for
software use. They are guaranteed to never be set by the interface.

Claims

1. A method performed by a receiving node in a network, comprising: the receiving node receiving an indication from the network that a sending node wants to send data to the receiving node, the indication from the sending node including a field for identifying a request for sending data using token identifiers;the receiving node sending to the sending node a token identifier identifying a memory location on the receiving node, an offset value that is updated when a transfer is split into multiple packets, and a data size for the memory location, the token identifier being a value that acts as an index into a token array, which identifies the memory location, but is not a physical or virtual address, so that the sending node is unaware of the memory location;the receiving node receiving from the sending node the token identifier and at least a first portion of the data;writing the data to the receiving node at the memory location;using a first token identifier array for processing the data, if the data is unexpected, as indicated by a field of the token identifier; andusing a second token identifier array for processing the data, if the data is expected.

2. The method of claim 1, wherein the indication that a sending node wants to send data to the receiving node is in the form of a Message Passing Interface (MPI) message containing a length of the data.

3. The method of claim 1, wherein the receiving node comprises an interface and at least one host processor.

4. The method of claim 3, wherein the interface and the host processor communicate via a Hypertransport protocol.

5. The method of claim 3, wherein the interface and the host processor communicate via a Peripheral Component Interconnect (PCI) Express protocol.

6. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving an InfiniBand packet format modified to include at least the token identifier.

7. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving an offset value into a memory buffer on the host.

8. The method of claim 7, further comprising receiving, by the receiving node from the sending node, the token identifier and at least a second portion of the data, along with a second offset into the memory buffer on the host where the second portion of data is to be stored.

9. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving memory header data that includes the token identifier.

10. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving memory header data that includes the token identifier and an offset into a memory buffer on a host.

11. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving memory header data including the token identifier and a port on a host.

12. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving memory header data including the token identifier and a version of the packet format.

13. The method of claim 1, wherein receiving, by the receiving node from the sending node, the token identifier and at least a first portion of the data further includes receiving a cut-through checksum based at least on data in the memory header but not the received data.

14. The method of claim 1 wherein the method is performed by an I/O interface communicating with a host processor.

15. The method of claim 14, wherein the I/O interface is a semiconductor chip.

16. The method of claim 14, wherein the I/O interface is a Field Programmable Gate Array (FPGA).

17. The method of claim 14, wherein the host processor determines the token identifier and which memory location on the host is associated with the token identifier.

18. The method of claim 1, further comprising validating the received packet before the data is written to the memory.

19. The method of claim 1, further comprising checking that the token identifier identifies a valid address in memory before the data is written to the memory.

20. The method of claim 1, further comprising checking that the data will not overrun an associated memory buffer before the data is written to the memory.

21. The method of claim 1, further comprising beginning to Direct Memory Access (DMA) the received data to the memory before all of the data is received.

22. A method performed by an interface of a receiving node in a network between a host, which has a memory, and a network, the method comprising: the interface of the receiving node receiving an indication from a sending node in the network that the sending node wants to send data to the receiving node, wherein the indication includes a field for identifying a request for sending data using token identifiers;the receiving node sending to the sending node a token identifier identifying a memory location on the receiving node, an offset value that is updated when a transfer is split into multiple packets, and a data size for the memory location, wherein the token identifier is a value that acts as an index into a token array, which identifies the memory location, but is not a physical or virtual address, so that the sending node is unaware of the memory location;the interface of the receiving node receiving a packet having at least a first portion of data and a token identifier;extracting the token identifier from the received packet;determining a memory address in the memory of the host in accordance with the token identifier;writing the data to the memory of the host at the determined memory address;using a first token identifier array for processing the data, if the data is unexpected, as indicated by a field of the token identifier; andusing a second token identifier array for processing the data, if the data is expected.

23. The method of claim 22, wherein writing the data comprises writing the data to the memory of the host using Direct Memory Access (DMA).

24. The method of claim 22, wherein the interface is an interface chip communicating with the host.

25. An interface to a host in a network, which has a memory, the interface comprising: a token sending unit for sending a token identifier identifying a memory location on the host to a packet sending node in the network, an offset value that is updated when a transfer is split into multiple packets, and a data size for the memory location, the token identifier being a value that acts as an index into a token array, which identifies the memory location, but is not a physical or virtual address, so that the sending node is unaware of the memory location, and before the interface sends the token identifier, the interface receives an indication from the sending node that the sending node wants to send data to the host, and the indication includes a field for identifying a request for sending data using token identifiers;a staging buffer for holding a packet received by the interface from the sending node, the packet received from the sending node containing at least received data and the token identifier;a first token identifier array indexed by the token identifier to yield an address of the memory location, if the data is expected data;a second token identifier array indexed by the token identifier to yield the address of the memory location, if the data is unexpected data, as indicated by a field of the token identifier; andan engine to send the data to the extracted memory location of the host.

26. The interface of claim 25, where the engine is a Direct Memory Access (DMA) engine.

27. The interface of claim 25, further comprising a validation engine to validate the token identifier before it is used as an index.

28. The interface of claim 25, further comprising a validation engine to validate the memory location before data is written to the memory location.

29. The interface of claim 25, further comprising a validation engine to validate the length of the data before it is written to the memory location.

30. The interface of claim 25, further comprising an engine to communicate with the host to obtain the token identifier before the token identifier is sent.

31. The interface of claim 25, further comprising a validation engine to validate checksum in accordance with the token identifier but not in accordance with the received data.

32. The interface of claim 25, wherein a packet header is sent to the host to be placed in a Receive Header Queue of the host.

33. The interface of claim 32, wherein the interface updates a tail pointer to the Receive Header Queue after the data has been written to the memory of the host.

34. A system, comprising: a host system; andan interface to the host system connected to the host system and to a network, the interface including: a module that receives an indication that a sending node in the network wants to send data to the host system, the indication including a field for identifying a request for sending data using token identifiers;a module that sends to the sending node a token identifier identifying a memory location on the host system, an offset value that is updated when a transfer is split into multiple packets, and a data size for the memory location, the token identifier being a value that acts as an index into a token array, which identifies the memory location, but is not a physical or virtual address, so that the sending node is unaware of the memory location;a module that receives, from the sending node, the token identifier and at least a first portion of the data, anda module that writes the data at the memory location;a first token identifier array for processing the data, if the data is unexpected, as indicated by a field of the token identifier; anda second token identifier array for processing the data, if the data is expected.