In addition to the provisional application referred to above, the following are incorporated herein by reference: U.S. patent application Ser. No. 12/708,497, filed 18 Feb. 2010, titled “Electronic Devices and Systems, and Methods for Making and Using the Same;” U.S. patent application Ser. No. 12/971,884, filed 17 Dec. 2010, titled “Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof,” U.S. patent application Ser. No. 12/971,955 filed 17 Dec. 2010, titled “Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof;” OS patent application Ser. No. 12/895,785 filed 30 Sep. 2010, titled “Advanced Transistors With Threshold Voltage Set Dopant Structures;” U.S. patent application Ser. No. 13/459,971, filed 30 Apr. 2012, titled “Multiple Transistor Types Formed in a Common Epitaxial Layer by Differential Out Diffusion from a Doped Underlayer;” U.S. patent application Ser. No. 13/592,122, filed 22 Aug. 2012, titled “Porting a Circuit Design from a First Semiconductor Process to a Second Semiconductor Process,” the entirety of these disclosures is hereby incorporated by reference.
The present invention relates generally to integrated circuits and methods of designing integrated circuits for manufacture in a semiconductor process.
Integrated circuit design typically begins with the knowledge of a design goal or specification. Such specifications describe the required performance of the circuit(s) to be designed. Integrated circuit designers typically first create a computer model of a circuit design that will meet the performance specification. That circuit design model is based upon the electrical circuit elements that are available in a given semiconductor manufacturing process. For example, electrical circuit elements may include diodes, transistors, capacitors, resistors, and so on. Typical modern integrated circuits include both p-channel field effect transistors and n-channel field effect transistors. Integrated circuits that include both p-channel field effect transistors and n-channel field effect transistors are referred to as CMOS integrated circuits.
It is common in semiconductor process technology nodes from about 45 nm and beyond, to find that a substantial amount of static power in CMOS integrated circuits is attributable to off-state leakage current in the transistors. The power consumption that results from this unwanted leakage current is undesirable, and consequently designers seek to reduce the power consumption due to leakage current.
One approach to reducing leakage current is to re-design the circuitry of an integrated circuit. Regardless of whether such a re-design can reduce leakage current without reducing performance, a high cost will be incurred in re-tooling the design. As is known in the field of integrated circuit design, the cost of preparing masks and fabricating integrated circuits with those mask sets is very high. In view of the high cost of re-designing an integrated circuit, designers desire to re-use their circuit designs (both transistor network topologies and physical layout). Circuit design re-use may reduce non-recurring engineering costs and may also reduce the time required to implement an integrated circuit design in fully fabricated integrated circuits. Re-using an integrated circuit design generally includes re-using the physical layout for that design. Re-using a physical layout generally means fabricating an integrated circuit in the same process for which it was originally designed, or fabricating it in an alternative process with different electrical characteristics but substantially the same feature sizes.
Unfortunately, the performance of many integrated circuit designs is very sensitive to complex combinations and distributions of variations in the electrical characteristics of transistors resulting from uncontrolled variations in the semiconductor manufacturing process. In some instances these performance sensitivities can result in a circuit that does not meet its specified performance goals. Failure to meet performance goals may result in the binning of parts into lower performance categories, and may even lead to total failure. Such yield losses are of great concern to designers.
Embodiments of the invention are described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left most digit(s) of a reference number identifies the drawing in which the reference number first appears.
It is noted that the cross-sectional representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures, process steps, and operations which they are illustrating.
The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the invention. References in the Detailed Description to “one exemplary embodiment,” “an illustrative embodiment,” “an exemplary embodiment,” and so on, indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary or illustrative embodiment may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the relevant art(s) to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the embodiments that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments.
The acronym AVT, as used herein is interchangeable with σΔVT.
The acronym CMOS refers to Complementary Metal Oxide Semiconductor. As used in this disclosure CMOS refers to either a circuit that includes both p-channel field effect transistors and n-channel field effect transistors, or a semiconductor manufacturing process that produces both p-channel field effect transistors and n-channel field effect transistors on the same die or on the same substrate.
Epitaxial layer refers to a layer of single crystal semiconductor material. In this field, an epitaxial layer is commonly referred to “epi.”
FET, as used herein, refers to field effect transistor. An n-channel FET is referred to herein as an N-FET. A p-channel FET is referred to herein as a P-FET. Unless noted otherwise the FETs referred to herein are MOSFETs.
It is noted that the use of the word “transistor” in this field is context sensitive. That is, depending on the context, it may refer to a physically implemented transistor in an integrated circuit, a simulation model of a transistor, a layout of a transistor, a schematic representation of a transistor, and so on.
As used herein, “gate” refers to the gate terminal of a FET. The gate terminal of a FET is also referred to in this field as a “gate electrode.” Historically, the gate electrode was a single structure such as a layer of doped polysilicon disposed on a gate dielectric. More recent gate electrodes have included the use of metals and metal alloys in their structures.
Source/drain (S/D) terminals refer to the terminals of a FET, between which conduction occurs under the influence of an electric field, subsequent to the inversion of the semiconductor surface under the influence of an electric field resulting from a voltage applied to the gate terminal of the FET. Generally, the source and drain terminals of a FET are fabricated such that they are geometrically symmetrical. With geometrically symmetrical source and drain terminals it is common to simply refer to these terminals as source/drain terminals, and this nomenclature is used herein. Designers often designate a particular source/drain terminal to be a “source” or a “drain” on the basis of the voltage to be applied to that terminal when the FET is operated in a circuit.
Substrate, as used herein, refers to the physical object that is the basic workpiece that is transformed by various process operations into the desired microelectronic configuration. Silicon wafers are a commonly used substrate in the manufacture of integrated circuits.
The “active” surface of a substrate refers to the surface in and upon which active circuit elements such as transistors are, or are to be, formed.
The acronym SRAM refers to Static Random Access Memory.
The term “porting” as used herein refers to the methods involved in taking a first integrated circuit design that has been targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements specified for the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. Further, in the context of the present disclosure, the second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Still further, in the context of the present disclosure, the methods involved in porting include determining processing targets for the second semiconductor manufacturing process.
The term “migrating” as used herein is synonymous with porting.
Overview
Recently, processes have been developed, such as the DDC transistor manufacturing processes developed by SuVolta, Inc., of Los Gatos, Calif., which can improve electrical performance without requiring an integrated circuit design to be re-implemented at the smaller dimensions required at other technology nodes. Because electrical improvements can be obtained without having to re-design circuitry and physical layouts for smaller feature sizes, there is significant interest in porting existing integrated circuit designs from a first semiconductor manufacturing process to a second manufacturing process with no, or relatively few, changes to the physical layout.
Put another way, a manufacturing process such as the DDC transistor semiconductor manufacturing process, offers reduced off-state leakage current as compared to designs implemented in conventional semiconductor manufacturing processes at substantially the same feature sizes. Further, a DDC transistor semiconductor manufacturing process can provide this improved electrical performance without requiring the large expense of producing a new mask set. However, in order to make a decision about whether to port an existing design to the alternative manufacturing process, customers desire to evaluate whether the yield to be expected in the new process makes the porting economically feasible. In other words, even if electrical performance is improved, if the yield is too low to profitably produce the product represented by the design, there is very little chance that a customer will agree to use the alternative process.
It is well known in the fields of integrated circuit design and semiconductor manufacturing that each new technology node provides smaller feature sizes for transistors, and usually for other structures such as interconnect as well. Conventionally, improved electrical performance required implementing integrated circuit designs with a more advanced manufacturing processes at a technology node that offered smaller feature sizes. Historically it was possible to “shrink” the physical layout and manufacture this smaller version of the original design in the new process. However, as feature sizes have become smaller, and particularly as minimum transistor dimensions have decreased below 100 nm, the required manufacturing processes and lithography methods have introduced layout constraints to such an extent that a simple linear shrink of a physical layout is very difficult, if not impossible, to use as a means of porting a given integrated circuit design from a first process to a second process that offers improved electrical performance.
As is known in the field of integrated circuit design, the cost of preparing masks and fabricating the integrated circuits is very high. In view of these costs, integrated circuit designers perform extensive simulations of their circuit designs in order to reduce the risk of manufacturing a circuit that does not perform as desired. Such circuit simulations generally rely on four sets of information: (a) a network topology description, (b) circuit element models, (c) process related targets (e.g., transistor threshold voltages), and (d) input waveforms to drive the circuit being simulated.
Both the network topology description and the input waveforms are independent of, or at least substantially decoupled from, the semiconductor manufacturing process with which the circuit is intended to be manufactured. The circuit element models and the process related targets are closely related to this semiconductor manufacturing process.
As noted above, integrated circuit designers seek to reduce static power consumption due to off-state leakage current. But, even in seeking to reduce this parasitic power consumption, circuit designers also desire to re-use their integrated circuit designs. In this context, an integrated circuit design refers to the information describing both a transistor network topology and a corresponding physical layout. It is noted that the aforementioned “transistor network topology” is used broadly herein and may encompass circuit network topologies that include other electrical circuit elements such as resistors, capacitors, diodes, and so on.
In general, a digital integrated circuit design project progresses through a number of well recognized steps. Each step provides some work product that is typically used as an input to the next step. For example, a system level description or system specification may be prepared that describes the functions and features of an integrated circuit. From the system level specification an architectural design for the proposed integrated circuit may be prepared. Next, a functional design and/or logic design is performed. Transistor-level circuit design may be performed subsequent to a logic design. Physical design may involve creating a physical layout of the integrated circuit, or at least portions of the integrated circuit. Various verification processes are performed to ensure that the design will meet its performance specifications. In the case of a digital integrated circuit, for example, simulations and/or static timing analyses are used to ensure that the timing requirements are met; design rule checking is performed to ensure manufacturability of the physical layout; layout versus schematic checking is performed to ensure that the physical layout matches the intended circuit design; and so on. Finally the integrated circuit is fabricated, tested, packaged, and the process is complete.
It is noted that there may be wide latitude in the steps of the circuit design project outlined above. For example, if the integrated circuit design is to be created by using pre-designed standard cells, then the need to perform transistor-level circuit design may be significantly diminished if not eliminated.
Various embodiments provide for transforming transistor parameter targets of a circuit designed for a first semiconductor manufacturing process to transistor parameter targets in a second semiconductor manufacturing process. The transistor parameter targets for the second process provide equal or better electrical performance and/or equal or better yield when the circuit is manufactured using the second process. The transistor parameter targets of the second process are typically, but not necessarily, different from those of the first process.
By way of example and not limitation, FET threshold voltage is a commonly used transistor parameter target. In fact, many semiconductor processes are set up to provide N-FETs selectively targeted to have either low Vt, standard Vt, or high Vt. Such processes also typically provide P-FETs selectively targeted to have either low Vt, standard Vt, or high Vt.
In the case of memory bit cell design, a substantial effort goes into developing and verifying the physical layout of the bit cell. From both cost and time-to-market perspectives, it would be very helpful in the case of a memory bit cell design to be able to port an existing design to a process with improved electrical characteristics. Improvements in electrical characteristics such as leakage current and reduced threshold voltage variation, are particularly desirable.
The DDC transistor architecture, and the semiconductor manufacturing process that produces it, have, among other things, the sought after characteristic of low sub-threshold conduction. This architecture and process are discussed in more detail below.
Since the DDC transistor architecture and manufacturing process provide integrated circuit designers with the electrical characteristics that are desired, but designers are reluctant to invest in a re-design and re-layout of an existing circuit, tools and methods for investigating the yield impact of process changes and demonstrating that an alternative process is suitable not only in terms of reduced off-state leakage current, but also in terms of yield would benefit designers, producers and consumers alike. Such tools and methods are further suited for process target generation.
DDC Transistor Architecture and Manufacturing Process
The structural architecture and illustrative methods of manufacturing DDC transistors are disclosed in great detail in various patents and patent applications assigned to the assignee of this application. Nonetheless, a short description of the DDC structural architecture, methods of manufacturing, and electrical characteristics are provided below.
DDC transistor 100 includes a screening region 112 that is highly doped with P-type dopants, and a Vt set region 111 also including P-type dopants. It will be understood that, with appropriate change to substrate or dopant material, a P-FET DDC transistor can similarly be formed.
In one embodiment, a process for forming the DDC transistor includes forming the screening region 112. In some embodiments, the screening region is formed by implanting dopants into P-well 114. In alternative embodiments the screening region is formed on the P-well using methods such as in-situ doped epitaxial silicon deposition, or epitaxial silicon deposition followed by dopant implantation. The screening region formation step can be before or after shallow trench isolation (STI) formation, depending on the application and results desired. Boron (B), Indium (I), or other P-type materials may be used for P-type implants, and arsenic (As), antimony (Sb) or phosphorous (P) and other N-type materials can be used for N-type implants. In some embodiments, screening region 112 can have a dopant concentration between about 1×1018 to 1×1020 dopant atoms/cm3, with approximately 5×1019 being typical. A germanium (Ge), carbon (C), or other dopant migration resistant layer can be applied above the screening region to reduce upward migration of dopants. The dopant migration resistant layer can be implanted into the screening region or provided as an in-situ doped epitaxial layer.
In some embodiments, a threshold voltage (Vt) set region 111 is disposed above screening region 112, and formed as a thin doped layer. Vt set region 111 can be either adjacent to screening region 112, be within screening region 112, or vertically offset from screening region 112. In some embodiments, Vt set region 111 is formed by delta doping, controlled in-situ deposition, or atomic layer deposition. Vt set region 111 can alternatively be formed by way of an in-situ doped epitaxial layer that is grown above screening region 112, or by epitaxial growth of a thin layer of silicon followed by out-diffusion of dopant atoms from screening region 112. Varying dopant concentration allows for adjustments of threshold voltage value for the transistor. In some embodiments, Vt set region 111 can have a dopant concentration between about 1×1018 dopant atoms/cm3 and about 1×1019 dopant atoms per cm3. In alternative embodiments, Vt set region 111 can have a dopant concentration that is approximately less than half of the concentration of dopants in screening region 112. Preferably, ion implantation performed to introduce the dopant material into a substrate, but at least some of the doping can be done using in-situ doped epitaxial deposition.
In some embodiments, the formation of Vt set region 111 is followed by a non-selective blanket epi deposition step that forms the substantially undoped channel region 110. Shallow trench isolation (STI) structures can be formed after the non-selective blanket epi deposition step, and can include the formation of a low temperature trench sacrificial oxide liner, at a temperature lower than 900° C.
In addition to using dopant migration resistant layers, other techniques can be used to reduce upward migration of dopants from screening region 112 and Vt set region 111, including but not limited to low temperature processing, selection or substitution of low migration dopants such as antimony or indium, low temperature or flash annealing to reduce interstitial dopant migration, or any other technique to reduce movement of dopant atoms.
Substantially undoped channel region 110 is positioned above Vt set region 111. Preferably, substantially undoped channel region 110 is achieved by way of epitaxial growth of intrinsic semiconductor material without dopant additives to modify the electrical conductivity of the material. The resultant layer typically has a dopant concentration less than 5×1017 dopant atoms per cm3. In alternative embodiments, substantially undoped channel region 110 has a dopant concentration that is approximately less than one tenth of the dopant concentration in screening region 112. In one embodiment, the thickness of substantially undoped channel region 110 can range from 5 to 50 nanometers, with exact thickness being dependent upon desired transistor operating characteristics and transistor design node (i.e., a 20 nm gate length transistor will typically have a thinner channel thickness than a 45 nm gate length transistor).
A gate stack may be formed or otherwise constructed above channel region 110 in a number of different ways, from different materials, and of different work functions as is known in this field.
Source 104 and drain 106 can be formed preferably using conventional dopant ion implantation processes and materials, and typically includes source/drain extension regions that define, at least in part, the electrical channel length of the transistor of which they form a part. Channel region 110 contacts and extends between S/D 104 and S/D 106.
In various embodiments of DDC transistor 100, when voltage is applied at gate electrode at a predetermined level, a depletion region formed in channel region 110 can substantially extend to the screening region 112.
Overall improvement of noise and electrical Characteristics for a transistor require careful trade-offs to be made in doping density, length, and depth of the foregoing transistor structures. Improvements made in one area, for example, channel mobility, can be easily offset by adverse short channel effects or greater variability in capacitance or output resistance. One particularly critical parameter for analog and digital transistor design is the threshold voltage at which the transistor switches on or off.
The threshold voltage of DDC transistor 100 can be adjusted by controlling the dopant concentration and position of Vt set region 111, while leaving the bulk of channel region 110 substantially undoped. In a typical DDC process architecture, conventional “channel implants” where the channel is implanted to set threshold voltage, is not used. Preferably, the threshold voltage setting technique of forming halos adjacent to the source/drain is not used, either. Preferably, the threshold voltage of the DDC transistor is set by the design, or selection, of various DDC process variables such as the doping depth, doping profile of the doped region and location and value of the peak concentration to result in a laterally extended, doped region that is embedded a distance away from the gate dielectric layer, preferably separated from the gate dielectric by a distance of at least ⅕ of the gate length (Lg). The DDC transistor doping profiles and dopant concentrations are designed., or selected, to achieve the desired threshold voltage, junction leakage and other parametric values. The design, or selection of the doping profiles and concentrations typical takes into consideration factors such as, but not limited to, the work function of the gate electrode.
As previously noted, screening region 112 is a highly doped layer that typically contains dopant atoms with a concentration of between 1×1018 atoms/cm3 and 1×1020 atoms/cm3, positioned under channel region 110. P-type dopants such as boron are selected for screening regions of N-FETs, while N-type dopants such as arsenic, antimony or phosphorus can be selected for P-FETs. The presence of a screening region below channel region 110 is necessary to define a depletion zone beneath the gate. Generally, the greater the distance screening region 112 is positioned from gate dielectric 128, the lower the threshold voltage, and conversely, the closer screening region 112 is to gate dielectric 128, the higher the threshold voltage. As shown in
A DDC semiconductor fabrication process typically uses a different process sequence from the conventional CMOS semiconductor fabrication process because it is imperative to control against unwanted migration of dopants from the screen/Vt set region into the channel which must remain substantially undoped. An exemplary process flow for a DDC semiconductor fabrication process is shown in
Referring to
It is noted that the DDC semiconductor fabrication process can be adapted to fabricate a combination of DDC transistors and non-DDC transistors. For instance, if non-DDC transistors of conventional planar type are to be fabricated, then the process described above in connection with
Referring to
It is noted that applying bias to screening region 112 is another technique for modifying Vt of DDC 100. Screening region 112 sets the body effect for the transistor and allows for a higher body effect than is found in conventional FET technologies. For example, a body tap 126 to screening region 112 of DDC transistor 100 can be formed in order to provide further control of threshold voltage. The applied bias can be either reverse or forward biased, and can result in significant changes to threshold voltage. Bias can be static or dynamic, and can be applied to isolated transistors, or to groups of transistors that share a common well. Biasing can be static to set threshold voltage at a fixed set point, or dynamic, to adjust to changes in transistor operating conditions or requirements.
Yield-Aware Semiconductor Manufacturing Process Target Generation
A device design has characteristics that are tied to the semiconductor manufacturing process such as, among other things, junction leakage, Ion/Ioff, DIBL (drain induced barrier lowering), Vt rolloff, Vt set range and Vt variability. The device characteristics in turn can determine the minimum supply voltage, reliability and other parameters specific to the circuit designs using the devices. At the bit cell level, the speed, power and yield are influenced by the device characteristics but compensatory design changes can be made to overcome limitations otherwise in the devices. For instance, critical dimension can be enlarged at a bit cell level to allow for increased threshold voltage, decreased junction leakage, and so on. The choice of what device design to use in a given bit cell should not be made solely on device-specific considerations. How the device can serve the bit cell design including the extent of the need to redesign the bit cell, should be comprehended. Preferably, the need to redesign should be kept to a minimum. If a better device could be inserted into the otherwise same bit cell design for better performance and power, the better device would be selected. Or, by using the better device, better value in the bit cell could be achieved by shrinking the footprint of the bit cell, enabled because of the better device. A method by which to evaluate a bit cell in the context of a device having specific device characteristics is highly desired. Such a method could lead to the ability to predict yields that could be achieved, which in turn can result in the implementation of the semiconductor process to churn out improved integrated circuits.
Basically, a transistor may have positive variation, no variation, or negative variation (3 possible states). The transistor variations, when combined and having the appropriate magnitude (as described below), provide a total variation at the circuit level at one sigma. Thus, the values may be multiplied by a desired circuit sigma to provide a specific transistor sigma for each case in a simulation-based experiment. The number of permutations m required for a predetermined circuit can be related to the number of variables k according to the following equation:
Equation 1 assumes (through i=0 summation start) that the 0 sigma point is included.
For sigma points that are subsequent to an initial run, e.g., from 2 sigma to 3 sigma, the summation begins with i=1. A quantity σ represents the total range of variation of a given variable (e.g., transistor Vt or total transistor variation) in a permutation. If the parametric variation of one parameter of a transistor device is considered to be one variable, then each permutation includes a parametric variation of each transistor in the predetermined circuit. If only one variable is subject to discrete variation, the range of variation of that variable is +/−σ. If two variables are subject to discrete variation, each variable can be represented as varying within the same range, making the range of variation for each variable σ/(20.5). Similarly, for three variables subject to equal discrete variation, the range of discrete variation for each variable is σ/(30.5), and for four variables subject to equal variation, the range of discrete variation for each variable is σ/(40.5). Thus, those skilled in statistics will recognize that the transistor level variations are treated as independent in their circuit level variation effect. In general if the predetermined circuit has n variables that are subject to variation, and each variable varies within the same range, the range of discrete variation for each variable x (where x is the transistor level sigma, and σ is the circuit level sigma) is provided by the following equation:
x=σ/(n0.5). (2)
For example, for a 2-input NAND gate having two P-FETs and two N-FETs, if the parametric variation being considered is threshold voltage variation, then the NAND gate has four variables that can vary (the four transistors), and therefore, in accordance with equation (1) m=80, i.e., there are 80 unique permutations of the variables for the NAND gate that result in a discrete circuit level variation σ. These permutations are enumerated in Table 1 below, where k1, k2, k3, and k4 correspond to each of the four variables:
Table 1 thus provides a zero-case included design of experiments (DOE) full factorial matrix for the transistor level sigma (x in Eq. (1) above) to be used. The zero case is included here because it allows that the circuit may not be sensitive to small variations in some devices for specific behaviors, and this may not be known a-priori. Note that the zero variation case is only used for the circuit level sigma case encompassing that unique point.
In one embodiment, where the predetermined circuit is a six transistor SRAM cell having two P-FETs and four N-FETs, if the parametric variation being considered is the threshold voltage variation of each transistor, then the SRAM cell has six variables. Therefore, in accordance with Equation (1), there are 728 possible permutations of these variables that result in a variation σ for the SRAM cell with the summation starting at i=1 (729 with start at i=0). More simply, there are 3 states, so the number of cases is 3k−1, i.e., 80 for 4 transistors, 243 for 5 transistors, and 728 for 6 transistors, etc. While this number grows quickly, it is far less than is required for a high resolution (statistically accurate) result using Monte Carlo methods. In addition, the range of variation of the threshold voltage for each of these permutations can be σ, σ/(20.5), σ/(30.5) σ/(40.5), σ/(50.5), or σ/(60.5) respectively, depending on whether the permutation has one, two, three, four, five, or six variables subject to variation, where each variable varies within the same range. In an alternative embodiment of the method for the six transistor SRAM cell, if the parametric variations being considered are the width and Length of the transistors of the SRAM cell, the SRAM cell has twelve variables (i.e., six variables for the width, and six variables for the length of each transistor, respectively). The number of permutations for this embodiment can be calculated from Equation (1), and the range of variation for each variable can be calculated from Equation (2). The DOE full factorial can thus replace a portion of the simulation points that would be provided randomly via Monte Carlo methods, at greater computational efficiency.
A table as set forth above can be generated for transistor permutations related to the devices in a given cell, for instance, in the case of SRAM, read static noise margin, write margin, read current, write speed and leakage power based on known device characteristics such as Vt, can be calculated. Then, the data can be examined to determine the number of faults. A failure rate can be generated for a given σ, from which the overall failure rate for an array can be derived by adding individual failures for individual cells. The inverse of the failure rate provides the yield. Thereby, the yield for a given bit cell constraint (such as supply voltage) can be determined. A table as set forth above can be generated for other types of circuits, for instance, an eight or ten-transistor SRAM, other type of memory, analog circuits and digital logic circuits.
Referring to
In step 215, a for loop iteratively performs step 220 for each permutation of variables, where the parametric variation of one parameter of a transistor in the predetermined circuit is considered to be one variable. For example, if the predetermined circuit has four transistors (e.g., a 2-input NAND gate having two P-FETs and two N-FETs), and if the parametric variation being considered is the threshold voltage variation, then the predetermined circuit has four variables (i.e., the threshold voltage variation for each of the four transistors), and the for loop of step 215 performs step 220 for each metric of interest for each permutation of the four variables.
When the for loop in step 215 has completed the iterations for each permutation of variables, step 240 is executed, which reports the number of failures for the m permutations analyzed in step 215.
In step 220, a for loop iteratively performs step 225 for each metric of interest that is being evaluated to estimate the yield of the predetermined circuit. When the for loop in step 220 has completed the evaluation of each metric of interest, step 235 is executed, which reports success (i.e., a PASS condition for the predetermined circuit) if all the evaluated metrics satisfy corresponding passing criterion associated with the evaluated metric, and reports failure (i.e., a FAIL condition for the predetermined circuit) if one or more of the evaluated metrics do not satisfy the corresponding passing criterion associated with the evaluated metric. In step 225, the predetermined circuit is simulated to determine the value of each evaluated metric. Step 230 compares the value of each evaluated metric against the corresponding passing criterion associated with the evaluated metric, and reports success to step 220 if the evaluated metric satisfies the corresponding passing criterion. Alternatively, step 230 reports failure to step 220, if the evaluated metric does not satisfy the corresponding passing criterion associated with the evaluated metric of interest.
To estimate the yield of the predetermined circuit in accordance with method 200, one or more evaluated metrics are specified for the predetermined circuit, and a predetermined passing criterion is specified for each evaluated metric. In one embodiment, where method 200 is used to estimate the yield of a NAND gate, the evaluated metrics can be one or more metrics selected from (i) rise propagation delay, (ii) fall propagation delay, (iii) rise slew delay, (iv) fall slew delay, (v) switching power, and (vi) leakage power. In an alternative embodiment, where method 200 is used to estimate the yield of an SRAM cell, the evaluated metrics can be one or more metrics selected from (i) read static noise margin, (ii) write margin, (iii) read current, (iv) write delay, (v) leakage power, (vi) standby state leakage power, and (vii) standby state minimum retention voltage (Vretain). In general, Vmin indicates the lowest read/write stable voltage for an SRAM array, while Vretain indicates the hold (static) margin minimum voltage, i.e., when the array is merely retaining state. The Vretain is thus in general lower than Vmin. As is known to skilled designers, VT or device size optimizations that favor one may not favor the other being minimized. For each metric, the associated passing criteria are specified in order to determine PASS/FAIL conditions of the predetermined circuit for each evaluated metric. For example, in method 200 to estimate the yield of a NAND gate, the evaluated metrics can be rise and fall propagation delays, active power and leakage power dissipation, and the associated pass/fail conditions can be defined such that the value of each of these metrics is less than a predetermined value (such as rise propagation delay less than 100 ps, and leakage power less than 1 nW, etc.). In one embodiment, the pass/fail criteria associated with each evaluated metric can be fixed, such that the same criteria is used for each of the operating conditions being analyzed in step 205. In alternative embodiments, the pass/fail criteria associated with each evaluated metric can vary as a function of the value of the operating conditions being analyzed in step 205, such that the pass/fail criteria is different for different values of one or more of the operating conditions in step 205.
In one embodiment, method 200 simulates all m permutations (in accordance with Equations (1) and (2) above) of the variables in the circuit and for each permutation, determines which of the points pass and which do not. All evaluation metrics of interest are computed for each permutation; a permutation that fails one or more pass/fail points is regarded as a failure, while a permutation that passes all pass/fail points is regarded as a success. Pass/fail criteria may be altered in subsequent usages of the method to determine some circuit behavior characteristics, e.g., Vmin over Vretain. In one embodiment, method 200 performs the computations for several values of global sigma within a range, ideally starting with a value of global sigma just before failures first appear and ending with a value of global sigma where additional failures are no longer substantial in determining yield. This ending value of global sigma will vary depending on the circuit being analyzed. For example, the SRAM cell may require analysis up to 8 global sigma or more, as an integrated circuit can contain millions of memory cells. In an alternative example, a flip-flop may only require analysis up to 4 global sigma since a target integrated circuit can contain only a few thousand sequential elements. In one embodiment of method 200, the values of global sigma are uniformly spaced within the range of values for which the computations are performed. In one embodiment of method 200, the values of global sigma are not uniformly spaced with the range of values for which the computations are performed. In alternative embodiments of method 200, the values of σ are more widely spaced for lower values of circuit level sigma and the values of circuit level sigma are more narrowly spaced for higher values of circuit level sigma. In certain embodiments of method 200, the values of circuit level sigma are adaptively spaced such that a narrower spacing is used for values of global sigma that have more failures and a wider spacing is used for values of global sigma that have fewer (or no) failures. For instance, if there are no failures at circuit level sigma=3, then smaller values may be skipped (those same factorial points with less variation will obviously pass).
In one embodiment, method 200 performs the computation for each operating condition within a range. In one embodiment, the operating condition can be the supply voltage (Vdd) and temperature (T) at which the circuit is operating. In alternative embodiments, the operating condition can include additional conditions such as, for example, the bias voltage applied to the screening region, such that the yield estimate can be obtained for a number of additional operating conditions. Examples of SRAM yield vs. supply voltage for varying SRAM array sizes are illustrated in
In addition to plotting the yield estimates for different operating conditions, the data obtained from method 200 can be used as part of a yield improvement method that modifies the design of the predetermined circuit to improve the yield. The manner in which this is performed is circuit and metric dependent. For example, it can be observed through simulations of the 6T SRAM cell that conditions which improve read static noise margin are often detrimental to write margin, and vice versa. If the failures observed during the computations performed as part of method 200 are separated into read failures and write failures, it is possible to determine that for certain embodiments the failures are weighted more heavily towards one type. If this is the case, the 6T SRAM cell can be redesigned to adjust the mean operating point of the cell such that read and write failures are more evenly distributed, thereby reducing the total number of failures over the range of operating conditions and improving the yield.
In other embodiments, failures can be examined and sorted according to severity. For the NAND gate example discussed above, a NAND gate that fails the rise propagation delay constraint for certain operating conditions and for a certain permutation of variables, will still yield a specific rise propagation delay value. If the passing criterion is a rise propagation delay that is less than or equal to 100 ps, one failure may register 101 ps while another may register 150 ps. The former failure barely fails the test, while the latter failure is a more severe failure. If the NAND gate is redesigned after yield analysis to improve the yield, the specific permutation of variables that resulted in the 150 ps delay can be used during the optimization of the rise propagation delay to ensure that the optimization parameters chosen satisfy the rise propagation delay goals for the worst case scenario. In other embodiments, the other evaluation metrics of the circuit can be re-optimized for their own worst case scenarios simultaneously to ensure that the result of the optimization does not result in optimizing the circuit for one evaluation metric at the expense of another evaluation metric.
Various embodiments of the methods described herein can reduce the number of simulations required to obtain yield estimates for a predetermined circuit. In particular, the methods described above are more efficient than Monte Carlo simulations, as they can be used to analyze the tail of the distribution directly. In addition, the methods described above can be used to obtain information regarding the relative severity of failing permutations for a circuit over a range of operating conditions, and therefore, enable the redesign and optimization of the circuit to optimize the yield. The methods described above are not limited to the examples of the NAND gate and 6T SRAM cell discussed herein. However, a the set of evaluation metrics that are analyzed to obtain the yield estimates can be different for each type of circuit, as will be understood by those skilled in the art. The methods described herein are applicable to circuits using DDC transistors and to circuits using conventional transistors.
Referring to
In another illustrative embodiment, a method of designing a bit cell for use in an array of bit cells, the bit cell having a plurality of transistors each of which performs a specified function, the transistors each having a predefined performance parameter margin for the specified function, includes providing at least one targeted operating condition for the bit cell array; providing a value of sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having a substantially undoped transistor channel, the transistor channel being the region in which depletion occurs when a voltage is applied to a gate terminal of the transistor, the substantially undoped transistor channel being located vertically adjacent a heavily doped region, the heavily doped region setting the depletion width for the transistor; providing an array of instances based upon the value of the sigma and using a factorial calculation; providing a metric of interest by which to determine pass and failure instances; extracting individual pass and fail instances for the metric of interest; and determining a yield for the array of bit cells for the targeted operating condition. In this illustrative embodiment the bit cell is a six-transistor CMOS SRAM bit cell.
In another illustrative embodiment, an integrated circuit having at least one array of circuit cells, each circuit cell in the circuit cell array designed using a plurality of transistors each of which performs a specified function, the transistors each having a predefined performance parameter margin for the specified function, the circuit cells designed according to a method including providing at least one targeted operating condition for the bit cell array; providing a value of circuit level sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic; providing an array of instances based upon the value of the circuit level sigma; providing a metric of interest by which to determine pass and failure instances; extracting individual pass and fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition.
In still other illustrative embodiments, a computer-aided design tool comprising a non-transitory computer-readable medium storing computer-executable instructions which, when executed by a processor, performs a method to increase the yield of an integrated circuit including an array of circuit cells, the method comprising: providing at least one targeted operating condition for the bit cell array; providing a value of circuit level sigma over a predefined range; determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic; providing an array of instances based upon the value of the circuit level sigma; providing a metric of interest by which to determine pass and failure instances; extracting individual pass and fail instances for the metric of interest; and determining a yield for the array of circuit cells for the targeted operating condition. Such embodiments may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Non-transitory computer readable medium include storage devices such as semiconductor memories, magnetic memories, and similar apparatus for storing program instructions.
Various embodiments described herein may be applied to integrated circuits that use multiple types of transistors, including conventional planar transistors, DDC transistors, transistors fabricated on SOI (silicon on insulator) substrates, and finFETs. Embodiments of the methods described herein may also be applied to integrated circuits that are configured to operate as “systems on a chip” (SoC), microprocessors, microcontrollers, graphics controllers, radio frequency circuits, memories, analog circuit blocks, digital circuit blocks, and that are capable of supporting a wide range of applications, including wireless telephones, mobile devices, communication devices, “smart phones”, embedded computers, portable computers, personal computers, servers, and any other devices that can benefit from yield estimation and/or yield improvement. In alternative embodiments, the methods described herein may be applied to components and sub-systems of a SoC, instead of individual transistors, and operating conditions and evaluation metrics can be associated for each component and sub-system.
Aspects of the illustrative embodiments, or any part(s) or function(s) thereof, may be implemented using hardware, software modules, firmware, tangible computer readable media having instructions stored thereon, or a combination thereof and may be implemented in one or more computer systems or other processing systems.
It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure, is intended to be used to interpret the Claims. The Abstract of the Disclosure may set forth one or more, but not all, illustrative embodiments of the invention, and thus, is not intended to limit the invention or the subjoined Claims in any way.
The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the invention. Therefore, the Detailed Description is not meant to limit the invention. Rather, the scope of the invention is defined only in accordance with the subjoined Claims and their equivalents.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
It will be apparent to those skilled in the relevant art(s) that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus the invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the subjoined Claims and their equivalents.
This non-provisional application claims the benefit of U.S. Provisional Application 61/535,872, entitled, “Integrated Circuit Devices and Methods for Achieving a Target Objective”, and filed 16 Sep. 2011, the entirety of which is hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
3958266 | Athanas | May 1976 | A |
4000504 | Berger | Dec 1976 | A |
4021835 | Etoh et al. | May 1977 | A |
4242691 | Kotani et al. | Dec 1980 | A |
4276095 | Beilstein, Jr. et al. | Jun 1981 | A |
4315781 | Henderson | Feb 1982 | A |
4518926 | Swanson | May 1985 | A |
4559091 | Allen et al. | Dec 1985 | A |
4578128 | Mundt et al. | Mar 1986 | A |
4617066 | Vasudev | Oct 1986 | A |
4662061 | Malhi | May 1987 | A |
4761384 | Neppl et al. | Aug 1988 | A |
4780748 | Cunningham et al. | Oct 1988 | A |
4819043 | Yazawa et al. | Apr 1989 | A |
4885477 | Bird et al. | Dec 1989 | A |
4908681 | Nishida et al. | Mar 1990 | A |
4945254 | Robbins | Jul 1990 | A |
4956311 | Liou et al. | Sep 1990 | A |
5034337 | Mosher et al. | Jul 1991 | A |
5144378 | Hikosaka | Sep 1992 | A |
5156989 | Williams et al. | Oct 1992 | A |
5156990 | Mitchell | Oct 1992 | A |
5166765 | Lee et al. | Nov 1992 | A |
5208473 | Komori et al. | May 1993 | A |
5294821 | Iwamatsu | Mar 1994 | A |
5298763 | Shen et al. | Mar 1994 | A |
5369288 | Usuki | Nov 1994 | A |
5373186 | Schubert et al. | Dec 1994 | A |
5384476 | Nishizawa et al. | Jan 1995 | A |
5426328 | Yilmaz et al. | Jun 1995 | A |
5444008 | Han et al. | Aug 1995 | A |
5552332 | Tseng et al. | Sep 1996 | A |
5559368 | Hu et al. | Sep 1996 | A |
5608253 | Liu et al. | Mar 1997 | A |
5622880 | Burr et al. | Apr 1997 | A |
5624863 | Helm et al. | Apr 1997 | A |
5625568 | Edwards et al. | Apr 1997 | A |
5641980 | Yamaguchi et al. | Jun 1997 | A |
5663583 | Matloubian et al. | Sep 1997 | A |
5712501 | Davies et al. | Jan 1998 | A |
5719422 | Burr et al. | Feb 1998 | A |
5726488 | Watanabe et al. | Mar 1998 | A |
5726562 | Mizuno | Mar 1998 | A |
5731626 | Eaglesham et al. | Mar 1998 | A |
5736419 | Naem | Apr 1998 | A |
5753555 | Hada | May 1998 | A |
5754826 | Gamal et al. | May 1998 | A |
5756365 | Kakumu | May 1998 | A |
5763921 | Okumura et al. | Jun 1998 | A |
5780899 | Hu et al. | Jul 1998 | A |
5847419 | Imai et al. | Dec 1998 | A |
5856003 | Chiu | Jan 1999 | A |
5861334 | Rho | Jan 1999 | A |
5877049 | Liu et al. | Mar 1999 | A |
5885876 | Dennen | Mar 1999 | A |
5889315 | Farrenkopf et al. | Mar 1999 | A |
5895954 | Yasumura et al. | Apr 1999 | A |
5899714 | Farremkopf et al. | May 1999 | A |
5918129 | Fulford, Jr. et al. | Jun 1999 | A |
5923067 | Voldman | Jul 1999 | A |
5923987 | Burr | Jul 1999 | A |
5936868 | Hall | Aug 1999 | A |
5946214 | Heavlin et al. | Aug 1999 | A |
5985705 | Seliskar | Nov 1999 | A |
5989963 | Luning et al. | Nov 1999 | A |
6001695 | Wu | Dec 1999 | A |
6020227 | Bulucea | Feb 2000 | A |
6043139 | Eaglesham et al. | Mar 2000 | A |
6060345 | Hause et al. | May 2000 | A |
6060364 | Maszara et al. | May 2000 | A |
6066533 | Yu | May 2000 | A |
6072217 | Burr | Jun 2000 | A |
6087210 | Sohn | Jul 2000 | A |
6087691 | Hamamoto | Jul 2000 | A |
6088518 | Hsu | Jul 2000 | A |
6091286 | Blauschild | Jul 2000 | A |
6096611 | Wu | Aug 2000 | A |
6103562 | Son et al. | Aug 2000 | A |
6121153 | Kikkawa | Sep 2000 | A |
6147383 | Kuroda | Nov 2000 | A |
6153920 | Gossmann et al. | Nov 2000 | A |
6157073 | Lehongres | Dec 2000 | A |
6175582 | Naito et al. | Jan 2001 | B1 |
6184112 | Maszara et al. | Feb 2001 | B1 |
6190979 | Radens et al. | Feb 2001 | B1 |
6194259 | Nayak et al. | Feb 2001 | B1 |
6198157 | Ishida et al. | Mar 2001 | B1 |
6218892 | Soumyanath et al. | Apr 2001 | B1 |
6218895 | De et al. | Apr 2001 | B1 |
6221724 | Yu et al. | Apr 2001 | B1 |
6229188 | Aoki et al. | May 2001 | B1 |
6232164 | Tsai et al. | May 2001 | B1 |
6235597 | Miles | May 2001 | B1 |
6245618 | An et al. | Jun 2001 | B1 |
6268640 | Park et al. | Jul 2001 | B1 |
6271070 | Kotani et al. | Aug 2001 | B2 |
6271551 | Schmitz et al. | Aug 2001 | B1 |
6288429 | Iwata et al. | Sep 2001 | B1 |
6297132 | Zhang et al. | Oct 2001 | B1 |
6300177 | Sundaresan et al. | Oct 2001 | B1 |
6313489 | Letavic et al. | Nov 2001 | B1 |
6319799 | Ouyang et al. | Nov 2001 | B1 |
6320222 | Forbes et al. | Nov 2001 | B1 |
6323525 | Noguchi et al. | Nov 2001 | B1 |
6326666 | Bernstein et al. | Dec 2001 | B1 |
6335233 | Cho et al. | Jan 2002 | B1 |
6358806 | Puchner | Mar 2002 | B1 |
6380019 | Yu et al. | Apr 2002 | B1 |
6391752 | Colinge et al. | May 2002 | B1 |
6426260 | Hshieh | Jul 2002 | B1 |
6426279 | Huster et al. | Jul 2002 | B1 |
6432754 | Assaderaghi et al. | Aug 2002 | B1 |
6444550 | Hao et al. | Sep 2002 | B1 |
6444551 | Ku et al. | Sep 2002 | B1 |
6449749 | Stine | Sep 2002 | B1 |
6461920 | Shirahata | Oct 2002 | B1 |
6461928 | Rodder | Oct 2002 | B2 |
6472278 | Marshall et al. | Oct 2002 | B1 |
6482714 | Hieda et al. | Nov 2002 | B1 |
6489224 | Burr | Dec 2002 | B1 |
6492232 | Tang et al. | Dec 2002 | B1 |
6500739 | Wang et al. | Dec 2002 | B1 |
6503801 | Rouse et al. | Jan 2003 | B1 |
6503805 | Wang et al. | Jan 2003 | B2 |
6506640 | Ishida et al. | Jan 2003 | B1 |
6518623 | Oda et al. | Feb 2003 | B1 |
6521470 | Lin et al. | Feb 2003 | B1 |
6534373 | Yu | Mar 2003 | B1 |
6541328 | Whang et al. | Apr 2003 | B2 |
6541829 | Nishinohara et al. | Apr 2003 | B2 |
6548842 | Bulucea et al. | Apr 2003 | B1 |
6551885 | Yu | Apr 2003 | B1 |
6552377 | Yu | Apr 2003 | B1 |
6573129 | Hoke et al. | Jun 2003 | B2 |
6576535 | Drobny et al. | Jun 2003 | B2 |
6600200 | Lustig et al. | Jul 2003 | B1 |
6620671 | Wang et al. | Sep 2003 | B1 |
6624488 | Kim | Sep 2003 | B1 |
6627473 | Oikawa et al. | Sep 2003 | B1 |
6630710 | Augusto | Oct 2003 | B1 |
6660605 | Liu | Dec 2003 | B1 |
6662350 | Fried et al. | Dec 2003 | B2 |
6667200 | Sohn et al. | Dec 2003 | B2 |
6670260 | Yu et al. | Dec 2003 | B1 |
6693333 | Yu | Feb 2004 | B1 |
6730568 | Sohn | May 2004 | B2 |
6737724 | Hieda et al. | May 2004 | B2 |
6743291 | Ang et al. | Jun 2004 | B2 |
6743684 | Liu | Jun 2004 | B2 |
6751519 | Satya et al. | Jun 2004 | B1 |
6753230 | Sohn et al. | Jun 2004 | B2 |
6760900 | Rategh et al. | Jul 2004 | B2 |
6770944 | Nishinohara et al. | Aug 2004 | B2 |
6787424 | Yu | Sep 2004 | B1 |
6797553 | Adkisson et al. | Sep 2004 | B2 |
6797602 | Kluth et al. | Sep 2004 | B1 |
6797994 | Hoke et al. | Sep 2004 | B1 |
6808004 | Kamm et al. | Oct 2004 | B2 |
6808994 | Wang | Oct 2004 | B1 |
6813750 | Usami et al. | Nov 2004 | B2 |
6821825 | Todd et al. | Nov 2004 | B2 |
6821852 | Rhodes | Nov 2004 | B2 |
6822297 | Nandakumar et al. | Nov 2004 | B2 |
6831292 | Currie et al. | Dec 2004 | B2 |
6835639 | Rotondaro et al. | Dec 2004 | B2 |
6852602 | Kanzawa et al. | Feb 2005 | B2 |
6852603 | Chakravarthi et al. | Feb 2005 | B2 |
6881641 | Wieczorek et al. | Apr 2005 | B2 |
6881987 | Sohn | Apr 2005 | B2 |
6891439 | Jachne et al. | May 2005 | B2 |
6893947 | Martinez et al. | May 2005 | B2 |
6900519 | Cantell et al. | May 2005 | B2 |
6901564 | Stine et al. | May 2005 | B2 |
6916698 | Mocuta et al. | Jul 2005 | B2 |
6917237 | Tschanz et al. | Jul 2005 | B1 |
6927463 | Iwata et al. | Aug 2005 | B2 |
6928128 | Sidiropoulos | Aug 2005 | B1 |
6930007 | Bu et al. | Aug 2005 | B2 |
6930360 | Yamauchi et al. | Aug 2005 | B2 |
6957163 | Ando | Oct 2005 | B2 |
6963090 | Passlack et al. | Nov 2005 | B2 |
6995397 | Yamashita et al. | Feb 2006 | B2 |
7002214 | Boyd et al. | Feb 2006 | B1 |
7008836 | Algotsson et al. | Mar 2006 | B2 |
7013359 | Li | Mar 2006 | B1 |
7015546 | Herr et al. | Mar 2006 | B2 |
7015741 | Tschanz et al. | Mar 2006 | B2 |
7022559 | Barnak et al. | Apr 2006 | B2 |
7036098 | Eleyan et al. | Apr 2006 | B2 |
7038258 | Liu et al. | May 2006 | B2 |
7039881 | Regan | May 2006 | B2 |
7045456 | Murto et al. | May 2006 | B2 |
7057216 | Ouyang et al. | Jun 2006 | B2 |
7061058 | Chakravarthi et al. | Jun 2006 | B2 |
7064039 | Liu | Jun 2006 | B2 |
7064399 | Babcock et al. | Jun 2006 | B2 |
7071103 | Chan et al. | Jul 2006 | B2 |
7078325 | Curello et al. | Jul 2006 | B2 |
7078776 | Nishinohara et al. | Jul 2006 | B2 |
7089513 | Bard et al. | Aug 2006 | B2 |
7089515 | Hanafi et al. | Aug 2006 | B2 |
7091093 | Noda et al. | Aug 2006 | B1 |
7105399 | Dakshina-Murthy et al. | Sep 2006 | B1 |
7109099 | Tan et al. | Sep 2006 | B2 |
7119381 | Passlack | Oct 2006 | B2 |
7122411 | Mouli | Oct 2006 | B2 |
7127687 | Signore | Oct 2006 | B1 |
7132323 | Haensch et al. | Nov 2006 | B2 |
7169675 | Tan et al. | Jan 2007 | B2 |
7170120 | Datta et al. | Jan 2007 | B2 |
7176137 | Perng et al. | Feb 2007 | B2 |
7186598 | Yamauchi et al. | Mar 2007 | B2 |
7189627 | Wu et al. | Mar 2007 | B2 |
7199430 | Babcock et al. | Apr 2007 | B2 |
7202517 | Dixit et al. | Apr 2007 | B2 |
7208354 | Bauer | Apr 2007 | B2 |
7211871 | Cho | May 2007 | B2 |
7221021 | Wu et al. | May 2007 | B2 |
7223646 | Miyashita et al. | May 2007 | B2 |
7226833 | White et al. | Jun 2007 | B2 |
7226843 | Weber et al. | Jun 2007 | B2 |
7230680 | Fujisawa et al. | Jun 2007 | B2 |
7235822 | Li | Jun 2007 | B2 |
7256639 | Koniaris et al. | Aug 2007 | B1 |
7259428 | Inaba | Aug 2007 | B2 |
7260562 | Czajkowski et al. | Aug 2007 | B2 |
7294877 | Rueckes et al. | Nov 2007 | B2 |
7297994 | Wieczorek et al. | Nov 2007 | B2 |
7301208 | Handa et al. | Nov 2007 | B2 |
7304350 | Misaki | Dec 2007 | B2 |
7307471 | Gammie et al. | Dec 2007 | B2 |
7312500 | Miyashita et al. | Dec 2007 | B2 |
7323754 | Ema et al. | Jan 2008 | B2 |
7332439 | Lindert et al. | Feb 2008 | B2 |
7348629 | Chu et al. | Mar 2008 | B2 |
7354833 | Liaw | Apr 2008 | B2 |
7380225 | Joshi et al. | May 2008 | B2 |
7398497 | Sato et al. | Jul 2008 | B2 |
7402207 | Besser et al. | Jul 2008 | B1 |
7402872 | Murthy et al. | Jul 2008 | B2 |
7416605 | Zollner et al. | Aug 2008 | B2 |
7427788 | Li et al. | Sep 2008 | B2 |
7442971 | Wirbeleit et al. | Oct 2008 | B2 |
7449733 | Inaba et al. | Nov 2008 | B2 |
7462908 | Bol et al. | Dec 2008 | B2 |
7469164 | Du-Nour | Dec 2008 | B2 |
7470593 | Rouh et al. | Dec 2008 | B2 |
7485536 | Jin et al. | Feb 2009 | B2 |
7487474 | Ciplickas et al. | Feb 2009 | B2 |
7491988 | Tolchinsky et al. | Feb 2009 | B2 |
7494861 | Chu et al. | Feb 2009 | B2 |
7496862 | Chang et al. | Feb 2009 | B2 |
7496867 | Turner et al. | Feb 2009 | B2 |
7498637 | Yamaoka et al. | Mar 2009 | B2 |
7501324 | Babcock et al. | Mar 2009 | B2 |
7503020 | Allen et al. | Mar 2009 | B2 |
7507999 | Kusumoto et al. | Mar 2009 | B2 |
7514766 | Yoshida | Apr 2009 | B2 |
7521323 | Surdeanu et al. | Apr 2009 | B2 |
7531393 | Doyle et al. | May 2009 | B2 |
7531836 | Liu et al. | May 2009 | B2 |
7538364 | Twynam | May 2009 | B2 |
7538412 | Schulze et al. | May 2009 | B2 |
7562233 | Sheng et al. | Jul 2009 | B1 |
7564105 | Chi et al. | Jul 2009 | B2 |
7566600 | Mouli | Jul 2009 | B2 |
7569456 | Ko et al. | Aug 2009 | B2 |
7580823 | Jakatdar et al. | Aug 2009 | B2 |
7586322 | Xu et al. | Sep 2009 | B1 |
7592241 | Takao | Sep 2009 | B2 |
7595243 | Bulucea et al. | Sep 2009 | B1 |
7598142 | Ranade et al. | Oct 2009 | B2 |
7605041 | Ema et al. | Oct 2009 | B2 |
7605060 | Meunier-Beillard et al. | Oct 2009 | B2 |
7605429 | Bernstein et al. | Oct 2009 | B2 |
7608496 | Chu | Oct 2009 | B2 |
7615802 | Elpelt et al. | Nov 2009 | B2 |
7622341 | Chudzik et al. | Nov 2009 | B2 |
7638380 | Pearce | Dec 2009 | B2 |
7642140 | Bae et al. | Jan 2010 | B2 |
7644377 | Saxe et al. | Jan 2010 | B1 |
7645665 | Kubo et al. | Jan 2010 | B2 |
7651920 | Siprak | Jan 2010 | B2 |
7655523 | Babcock et al. | Feb 2010 | B2 |
7673273 | Madurawe et al. | Mar 2010 | B2 |
7675126 | Cho | Mar 2010 | B2 |
7675317 | Perisetty | Mar 2010 | B2 |
7678638 | Chu et al. | Mar 2010 | B2 |
7681628 | Joshi et al. | Mar 2010 | B2 |
7682887 | Dokumaci et al. | Mar 2010 | B2 |
7683442 | Burr et al. | Mar 2010 | B1 |
7696000 | Liu et al. | Apr 2010 | B2 |
7704822 | Jeong | Apr 2010 | B2 |
7704844 | Zhu et al. | Apr 2010 | B2 |
7709828 | Braithwaite et al. | May 2010 | B2 |
7723750 | Zhu et al. | May 2010 | B2 |
7737472 | Kondo et al. | Jun 2010 | B2 |
7741138 | Cho | Jun 2010 | B2 |
7741200 | Cho et al. | Jun 2010 | B2 |
7745270 | Shah et al. | Jun 2010 | B2 |
7750374 | Capasso et al. | Jul 2010 | B2 |
7750381 | Hokazono et al. | Jul 2010 | B2 |
7750405 | Nowak | Jul 2010 | B2 |
7750682 | Bernstein et al. | Jul 2010 | B2 |
7755144 | Li et al. | Jul 2010 | B2 |
7755146 | Helm et al. | Jul 2010 | B2 |
7759206 | Luo et al. | Jul 2010 | B2 |
7759714 | Itoh et al. | Jul 2010 | B2 |
7761820 | Berger et al. | Jul 2010 | B2 |
7795677 | Bangsaruntip et al. | Sep 2010 | B2 |
7808045 | Kawahara et al. | Oct 2010 | B2 |
7808410 | Kim et al. | Oct 2010 | B2 |
7811873 | Mochizuki | Oct 2010 | B2 |
7811881 | Cheng et al. | Oct 2010 | B2 |
7818702 | Mandelman et al. | Oct 2010 | B2 |
7821066 | Lebby et al. | Oct 2010 | B2 |
7829402 | Matocha et al. | Nov 2010 | B2 |
7831873 | Trimberger et al. | Nov 2010 | B1 |
7846822 | Seebauer et al. | Dec 2010 | B2 |
7855118 | Hoentschel et al. | Dec 2010 | B2 |
7859013 | Chen et al. | Dec 2010 | B2 |
7863163 | Bauer | Jan 2011 | B2 |
7867835 | Lee et al. | Jan 2011 | B2 |
7883977 | Babcock et al. | Feb 2011 | B2 |
7888205 | Herner et al. | Feb 2011 | B2 |
7888747 | Hokazono | Feb 2011 | B2 |
7895546 | Lahner et al. | Feb 2011 | B2 |
7897495 | Ye et al. | Mar 2011 | B2 |
7906413 | Cardone et al. | Mar 2011 | B2 |
7906813 | Kato | Mar 2011 | B2 |
7910419 | Fenouillet-Beranger et al. | Mar 2011 | B2 |
7919791 | Flynn et al. | Apr 2011 | B2 |
7926018 | Moroz et al. | Apr 2011 | B2 |
7935984 | Nakano | May 2011 | B2 |
7941776 | Majumder et al. | May 2011 | B2 |
7945800 | Gomm et al. | May 2011 | B2 |
7948008 | Liu et al. | May 2011 | B2 |
7952147 | Ueno et al. | May 2011 | B2 |
7960232 | King et al. | Jun 2011 | B2 |
7960238 | Kohli et al. | Jun 2011 | B2 |
7968400 | Cai | Jun 2011 | B2 |
7968411 | Williford | Jun 2011 | B2 |
7968440 | Seebauer | Jun 2011 | B2 |
7968459 | Bedell et al. | Jun 2011 | B2 |
7989900 | Haensch et al. | Aug 2011 | B2 |
7994573 | Pan | Aug 2011 | B2 |
8004024 | Furukawa et al. | Aug 2011 | B2 |
8012827 | Yu et al. | Sep 2011 | B2 |
8029620 | Kim et al. | Oct 2011 | B2 |
8039332 | Bernard et al. | Oct 2011 | B2 |
8046598 | Lee | Oct 2011 | B2 |
8048791 | Hargrove et al. | Nov 2011 | B2 |
8048810 | Tsai et al. | Nov 2011 | B2 |
8051340 | Cranford, Jr. et al. | Nov 2011 | B2 |
8053340 | Colombeau et al. | Nov 2011 | B2 |
8063466 | Kurita | Nov 2011 | B2 |
8067279 | Sadra et al. | Nov 2011 | B2 |
8067280 | Wang et al. | Nov 2011 | B2 |
8067302 | Li | Nov 2011 | B2 |
8076719 | Zeng et al. | Dec 2011 | B2 |
8097529 | Krull et al. | Jan 2012 | B2 |
8103983 | Agarwal et al. | Jan 2012 | B2 |
8105891 | Yeh et al. | Jan 2012 | B2 |
8106424 | Schruefer | Jan 2012 | B2 |
8106481 | Rao | Jan 2012 | B2 |
8110487 | Griebenow et al. | Feb 2012 | B2 |
8114761 | Mandrekar et al. | Feb 2012 | B2 |
8119482 | Bhalla et al. | Feb 2012 | B2 |
8120069 | Hynecek | Feb 2012 | B2 |
8129246 | Babcock et al. | Mar 2012 | B2 |
8129797 | Chen et al. | Mar 2012 | B2 |
8134159 | Hokazono | Mar 2012 | B2 |
8143120 | Kerr et al. | Mar 2012 | B2 |
8143124 | Challa et al. | Mar 2012 | B2 |
8143678 | Kim et al. | Mar 2012 | B2 |
8148774 | Mori et al. | Apr 2012 | B2 |
8163619 | Yang et al. | Apr 2012 | B2 |
8169002 | Chang et al. | May 2012 | B2 |
8170857 | Joshi et al. | May 2012 | B2 |
8173499 | Chung et al. | May 2012 | B2 |
8173502 | Yan et al. | May 2012 | B2 |
8176461 | Trimberger | May 2012 | B1 |
8178430 | Kim et al. | May 2012 | B2 |
8179530 | Levy et al. | May 2012 | B2 |
8183096 | Wirbeleit | May 2012 | B2 |
8183107 | Mathur et al. | May 2012 | B2 |
8185865 | Gupta et al. | May 2012 | B2 |
8187959 | Pawlak et al. | May 2012 | B2 |
8188542 | Yoo et al. | May 2012 | B2 |
8196545 | Kurosawa | Jun 2012 | B2 |
8201122 | Dewey, III et al. | Jun 2012 | B2 |
8214190 | Joshi et al. | Jul 2012 | B2 |
8217423 | Liu et al. | Jul 2012 | B2 |
8225255 | Ouyang et al. | Jul 2012 | B2 |
8227307 | Chen et al. | Jul 2012 | B2 |
8236661 | Dennard et al. | Aug 2012 | B2 |
8239803 | Kobayashi | Aug 2012 | B2 |
8247300 | Babcock et al. | Aug 2012 | B2 |
8255843 | Chen et al. | Aug 2012 | B2 |
8258026 | Bulucea | Sep 2012 | B2 |
8286180 | Foo | Oct 2012 | B2 |
8288798 | Passlack | Oct 2012 | B2 |
8299562 | Li et al. | Oct 2012 | B2 |
8324059 | Guo et al. | Dec 2012 | B2 |
8336010 | Chang et al. | Dec 2012 | B1 |
20010014495 | Yu | Aug 2001 | A1 |
20020023329 | Nulman | Feb 2002 | A1 |
20020042184 | Nandakumar et al. | Apr 2002 | A1 |
20030006415 | Yokogawa et al. | Jan 2003 | A1 |
20030047763 | Hieda et al. | Mar 2003 | A1 |
20030122203 | Nishinohara et al. | Jul 2003 | A1 |
20030173626 | Burr | Sep 2003 | A1 |
20030183856 | Wieczorek et al. | Oct 2003 | A1 |
20030215992 | Sohn et al. | Nov 2003 | A1 |
20040075118 | Heinemann et al. | Apr 2004 | A1 |
20040075143 | Bae et al. | Apr 2004 | A1 |
20040084731 | Matsuda et al. | May 2004 | A1 |
20040087090 | Grudowski et al. | May 2004 | A1 |
20040126947 | Sohn | Jul 2004 | A1 |
20040175893 | Vatus et al. | Sep 2004 | A1 |
20040180488 | Lee | Sep 2004 | A1 |
20050056877 | Rueckes et al. | Mar 2005 | A1 |
20050106824 | Alberto et al. | May 2005 | A1 |
20050116282 | Pattanayak et al. | Jun 2005 | A1 |
20050250289 | Babcock et al. | Nov 2005 | A1 |
20050280075 | Ema et al. | Dec 2005 | A1 |
20060017100 | Bol et al. | Jan 2006 | A1 |
20060022270 | Boyd et al. | Feb 2006 | A1 |
20060049464 | Rao | Mar 2006 | A1 |
20060068555 | Zhu et al. | Mar 2006 | A1 |
20060068586 | Pain | Mar 2006 | A1 |
20060071278 | Takao | Apr 2006 | A1 |
20060091481 | Li et al. | May 2006 | A1 |
20060154428 | Dokumaci | Jul 2006 | A1 |
20060157794 | Doyle et al. | Jul 2006 | A1 |
20060161452 | Hess | Jul 2006 | A1 |
20060197158 | Babcock et al. | Sep 2006 | A1 |
20060203581 | Joshi et al. | Sep 2006 | A1 |
20060220114 | Miyashita et al. | Oct 2006 | A1 |
20060223248 | Venugopal et al. | Oct 2006 | A1 |
20070040222 | Van Camp et al. | Feb 2007 | A1 |
20070117326 | Tan et al. | May 2007 | A1 |
20070158790 | Rao | Jul 2007 | A1 |
20070212861 | Chidambarrao et al. | Sep 2007 | A1 |
20070238253 | Tucker | Oct 2007 | A1 |
20080028349 | Muranaka | Jan 2008 | A1 |
20080067589 | Ito et al. | Mar 2008 | A1 |
20080108208 | Arevalo et al. | May 2008 | A1 |
20080138953 | Challa et al. | Jun 2008 | A1 |
20080169493 | Lee et al. | Jul 2008 | A1 |
20080169516 | Chung | Jul 2008 | A1 |
20080197439 | Goerlach et al. | Aug 2008 | A1 |
20080227250 | Ranade et al. | Sep 2008 | A1 |
20080237661 | Ranade et al. | Oct 2008 | A1 |
20080258198 | Bojarczuk et al. | Oct 2008 | A1 |
20080272409 | Sonkusale et al. | Nov 2008 | A1 |
20090003105 | Itoh et al. | Jan 2009 | A1 |
20090057746 | Sugll et al. | Mar 2009 | A1 |
20090057762 | Bangsaruntip et al. | Mar 2009 | A1 |
20090108350 | Cai et al. | Apr 2009 | A1 |
20090121298 | Furukawa et al. | May 2009 | A1 |
20090134468 | Tsuchiya et al. | May 2009 | A1 |
20090224319 | Kohli | Sep 2009 | A1 |
20090302388 | Cai et al. | Dec 2009 | A1 |
20090309140 | Khamankar et al. | Dec 2009 | A1 |
20090311837 | Kapoor | Dec 2009 | A1 |
20090321849 | Miyamura et al. | Dec 2009 | A1 |
20100012988 | Yang et al. | Jan 2010 | A1 |
20100038724 | Anderson et al. | Feb 2010 | A1 |
20100100856 | Mittal | Apr 2010 | A1 |
20100148153 | Hudait et al. | Jun 2010 | A1 |
20100149854 | Vora | Jun 2010 | A1 |
20100187641 | Zhu et al. | Jul 2010 | A1 |
20100207182 | Paschal | Aug 2010 | A1 |
20100228370 | Tsen et al. | Sep 2010 | A1 |
20100270600 | Inukai et al. | Oct 2010 | A1 |
20110059588 | Kang | Mar 2011 | A1 |
20110073961 | Dennard et al. | Mar 2011 | A1 |
20110074498 | Thompson et al. | Mar 2011 | A1 |
20110079860 | Verhulst | Apr 2011 | A1 |
20110079861 | Shifren et al. | Apr 2011 | A1 |
20110095811 | Chi et al. | Apr 2011 | A1 |
20110147828 | Murthy et al. | Jun 2011 | A1 |
20110169082 | Zhu et al. | Jul 2011 | A1 |
20110175170 | Wang et al. | Jul 2011 | A1 |
20110180880 | Chudzik et al. | Jul 2011 | A1 |
20110193164 | Zhu | Aug 2011 | A1 |
20110212590 | Wu et al. | Sep 2011 | A1 |
20110230039 | Mowry et al. | Sep 2011 | A1 |
20110242921 | Tran et al. | Oct 2011 | A1 |
20110248352 | Shifren | Oct 2011 | A1 |
20110294278 | Eguchi et al. | Dec 2011 | A1 |
20110307846 | Culp et al. | Dec 2011 | A1 |
20110309447 | Arghavani et al. | Dec 2011 | A1 |
20120021594 | Gurtej et al. | Jan 2012 | A1 |
20120034745 | Colombeau et al. | Feb 2012 | A1 |
20120056275 | Cai et al. | Mar 2012 | A1 |
20120065920 | Nagumo et al. | Mar 2012 | A1 |
20120108050 | Chen et al. | May 2012 | A1 |
20120132998 | Kwon et al. | May 2012 | A1 |
20120138953 | Cai et al. | Jun 2012 | A1 |
20120146155 | Hoentschel et al. | Jun 2012 | A1 |
20120167025 | Gillespie et al. | Jun 2012 | A1 |
20120187491 | Zhu et al. | Jul 2012 | A1 |
20120190177 | Kim et al. | Jul 2012 | A1 |
20120223363 | Kronholz et al. | Sep 2012 | A1 |
Number | Date | Country |
---|---|---|
0274278 | Jul 1988 | EP |
0312237 | Apr 1989 | EP |
0531621 | Mar 1993 | EP |
0683515 | Nov 1995 | EP |
0889502 | Jan 1999 | EP |
1450394 | Aug 2004 | EP |
59193066 | Nov 1984 | JP |
4186774 | Jul 1992 | JP |
8153873 | Jun 1996 | JP |
8288508 | Nov 1996 | JP |
2004087671 | Mar 2004 | JP |
794094 | Jan 2008 | KR |
WO2009000934 | Dec 2008 | WO |
WO2011062788 | May 2011 | WO |
Entry |
---|
Abiko, H et al., “A Channel Engineering Combined with Channel Epitaxy Optimization and TED Suppression for 0.151 μm n-n Gate CMOS Technology”, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 23-24. |
Chau, R et al., “A 50nm Depleted-Substrate CMOS Transistor (DST)”, Electron Device Meeting 2001, IEDM Technical Digest, IEEE International, pp. 29.1.1-29.1.4. |
Ducroquet, F et al. “Fully Depleted Silicon-On-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channel”, ECS 210th Meeting, Abstract 1033, 2006. |
Ernst, T et al., “Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrcal Properties Features”, ECS Trans. 2006, vol. 3, Issue 7, pp. 947-961. |
Goesele, U et al., Diffusion Engineering by Carbon in Silicon, Mat. Res. Soc. Symp. vol. 610, 2000. |
Hokazono, A et al., “Steep Channel & Halo Profiles Utilizing Boron-Diffusion-Barrier Layers (Si:C) for 32 nm Node and Beyond”, 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 112-113, 2008. |
Hokazono, A et al., “Steep Channel Profiles in n/pMOS Controlled by Boron-Doped Si:C Layers for Continual Bulk-CMOS Scaling”, IEDM09-676 Symposium, pp. 29.1.1-29.1.4, 2009. |
Holland, OW and Thomas, DK “A Method to Improve Activation of Implanted Dopants in SiC”, Oak Ridge National Laboratory, Oak Ridge, TN, 2001. |
Kotaki, H., et al., “Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS”, IEDM 96, pp. 459-462, 1996. |
Lavéant, P. “Incorporation, Diffusion and Agglomeration of Carbon in Silicon”, Solid State Phenomena, vols. 82-84, pp. 189-194, 2002. |
Noda, K et al., “A 0.1-μm Delta-Doped MOSFET Fabricated with Post-Low-Fnergy Implanting Selective Epitaxy” IEEE Transactions on Electron Devices, vol. 45, No. 4, pp. 809-814, Apr. 1998. |
Ohguro, T et al., “An 0.18-μm CMOS for Mixed Digital and Analog Aplications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, IEEE Transactions on Electron Devices, vol. 46, No. 7, pp. 1378-1383, Jul. 1999. |
Pinacho, R et al., “Carbon in Silicon: Modeling of Diffusion and Clustering Mechanisms”, Journal of Applied Physics, vol. 92, No. 3, pp. 1582-1588, Aug. 2002. |
Robertson, LS et al., “The Effect of Impurities on Diffusion and Activation of Ion Implanted Boron in Silicon”, Mat. Res. Soc. Symp. vol. 610, 2000. |
Scholz, R et al., “Carbon-Induced Undersaturation of Silicon Self-Interstitials”, Appl. Phys. Lett. 72(2), pp. 200-202, Jan. 1998. |
Scholz, RF et al., “The Contribution of Vacancies to Carbon Out-Diffusion in Silicon”, Appl. Phys. Lett., vol. 74, No. 3, pp. 392-394, Jan. 1999. |
Stolk, PA et al., “Physical Mechanisms of Transient Enhanced Dopant Diffusion in Ion-Implanted Silicon”, J. Appl. Phys. 81(9), pp. 6031-6050, May 1997. |
Thompson, S et al., “MOS Scaling: Transistor Challenges for the 21st Century”, Intel Technology Journal Q3' 1998, pp. 1-19, 1998. |
Wann, C. et al., “Channel Profile Organization and Device Design for Low-Power High-Performance Dynamic Threshold MOSFET”, IEDM 96, pp. 113-116, 1996. |
Werner, P et al., “Carbon Diffusion in Silicon”, Applied Physics Letters, vol. 73, No. 17, pp. 2465-2467, Oct. 1998. |
Yan, Ran-Hong et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE Transactions on Electron Devices, vol. 39, No. 7, Jul. 1992. |
Komaragiri, R. et al., “Depletion-Free Poly Gate Electrode Architecture for Sub 100 Nanometer CMOS Devices with High-K Gate Dielectrics,” IEEE IEDM Tech Dig., San Francisco CA, 833-836, Dec. 13-15, 2004, Dec. 2004. |
Samsudin, K et al., “Integrating Intrinsic Parameter Fluctuation Description into BSIMSOI to Forecast sub-15nm UTB SOI based 6T SRAM Operation”, Solid-State Electronics (50), pp. 86-93 (2006). |
Wong, H et al., “Nanoscale CMOS”, Proceedings of the IEEE, Vo. 87, No. 4, pp. 537-370 (Apr. 1999). |
Banerjee, et al. “Compensating Non-Optical Effects using Electrically-Driven Optical Proximity Correction”, Proc. of SPIE vol. 7275 7275OE (2009). |
Cheng, et al. “Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications”, Electron Devices Meeting (IEDM) (Dec. 2009). |
Cheng, et al. “Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Feturing Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain”, Symposium on VLSI Technology Digest of Technical Papers, pp. 212-213 (2009). |
Drennan, et al. “Implications of Proximity Effects for Analog Design”, Custom Integrated Circuits Conference, pp. 169-176 (Sep. 2006). |
Hook, et al. “Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEE Transactions on Electron Devices, vol. 50, No. 9, pp. 1946-1951 (Sep. 2003). |
Hori, et al. “A 0.1 μm CMOS with a Step Channel Profile Formed by Ultra High Vacuum CVD and In-Situ-Doped Ions”, Proceeding of the International Electron Devices Meeting, New York, IEEE, US, pp. 909-911 (Dec. 5, 1993). |
Matshuashi, et al. “High-Performance Double-Layer Epitaxial-Channel PMOSFET Compatible with a Single Gate CMOSFET”, Symposium on VLSI Technology Digest of Technical Papers, pp. 36-37 (1996). |
Shao, et al., “Boron Diffusion in Silicon: The Anomalies and Control by Point Defect Engineering”, Materials Science and Engineering R: Reports, vol. 42, No. 3-4, pp. 65-114 (Nov. 2003). |
Sheu, et al. “Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs”, IEEE Transactions on Electron Devices, vol. 53, No. 11, pp. 2792-2798 (Nov. 2006). |
Number | Date | Country | |
---|---|---|---|
61535872 | Sep 2011 | US |