TOPOLOGY AGNOSTIC DETECTION AND LOCATION OF FAULT IN DC MICROGRID USING LOCAL MEASUREMENTS

Abstract

Systems and methods of determining fault location on a DC microgrid feeder need to be extremely fast to protect the circuit breaker and converter-source components. This disclosure develops a seminal theoretical foundation for fast fault location on a DC feeder that uses only single-ended local measurements in time domain. The theory provides a closed-form deterministic solution for fault location, making the resulting fault location method agnostic to system-topology and immune to fault resistance. The theory is developed with ideal DC voltage sources and is extended to practical converter-sources. The performance of the resulting method is demonstrated by simulating a DC feeder with converters connected at both ends, modeled in PSCAD (power systems computer-aided design).

Description

FIELD

The present disclosure relates generally to fault detection and fault location. More particularly, the present subject matter relates to detecting a fault and determining the fault location on a DC feeder within a critical time, using only single-ended local measurements.

BACKGROUND

Despite the clear advantages of DC distribution systems over AC, DC distribution microgrids have not gained much commercial success due to some major challenges. One challenge is the much faster protection needed for the safety of converter components and circuit breakers. In other words, systems and methods of determining fault location on a DC microgrid feeder, which must precede operation of a circuit breaker to clear the fault, need to be extremely fast to protect the circuit breaker and converter-source components. This disclosure develops a seminal theoretical foundation for fast fault location on a DC feeder that uses only single-ended local measurements (using measurements only at one bus) in time domain. The theory provides a closed-form deterministic solution for fault location, and the resulting method is agnostic to system topology and immune to fault resistance. The theory is developed with ideal DC voltage sources and is extended to practical converter sources, and the performance of the resulting method is demonstrated by simulating a DC feeder with converters connected at both ends, modeled in Power Systems Computer-Aided Design (PSCAD).

With microgrids emerging as building blocks for future power delivery paradigm, DC networks are being conceived to be a better alternative than the traditional AC networks^[1]. Most of the generation at the distribution level is typically solar photovoltaic (PV), often supported by battery storage. These sources are DC. Modern loads like laptops, computers, TV, cell phone chargers, and electric vehicles operate on DC as well. Thus, DC microgrids can be less lossy as they would require fewer conversion stages. In terms of operating complexity, there is no need for reactive power generation or frequency regulation in DC systems, resulting in better and simpler control of power.

Despite the benefits, implementation of DC microgrids at the commercial scale is obstructed by some challenges, one of which is unusually fast protection requirements, typically in tens of microseconds, caused by the following two constraints: First, in response to a fault, current in DC circuits rises in a matter of tens of microseconds^[2], without having a natural current zero. If the fault current crosses the breaking limit of the controlling circuit breaker, it cannot be interrupted. Secondly, in a DC microgrid, DC-DC converters are used to interface renewable sources to the microgrid, and AC-DC rectifiers are used to connect the microgrid with the AC grid. These converters and rectifiers are made of power electronic devices such as diodes and IGBTs and have capacitors connected at their DC side, known as DC-link capacitors. When a fault occurs in a DC microgrid, current from these capacitors dominates at first^[3]-[5]. After the capacitor voltage drops to a critical value, a high fault current starts to flow through the power electronic devices^[3],[6], exposing them to damage. Thus, another protection challenge in DC microgrids is to isolate the fault before the current goes beyond the limit of the power electronic circuitry.

The published literature on protection of DC microgrids can be divided into two main categories: Those which use local measurements only and those which use remote measurements as well, and hence, need communication^[7]-[9]. Since communication introduces delays and uncertainties, which are counterproductive to fast and reliable protection, schemes using local measurements only will be discussed here. Prior art indicates a local measurement-based fault location method used for bolted faults only; for any other fault involving a resistance, authors had to use communication^[11]. An inductance-based fault location method was proposed^{[34], [35]}, but the method can only be applied if the system is radial, and the fault current is being sourced from one end only. However, a DC microgrid will certainly have multiple sources, and therefore, a fault will be fed from both ends of the faulted feeder.

Some other methods in published literature also use only local measurements for fault detection^[4],[10]. These methods use current derivatives for fault detection which creates system dependency as derivatives change with the location of fault on a given feeder, as well as with topology of the network, thus severely restricting the generality of application. Further, a current limiting inductance is inserted in series with cables, and voltage across the inductance is used for fault detection^[6]. This can also be related to the current derivative approach because voltage across an inductance is directly proportional to the current derivative. Setting thresholds using this approach are determined through rigorous simulation of the entire system, which underscores their system dependency.

There are very few works that determine the exact location of the fault after detecting it. In some, the faulted section is isolated, but the location of fault on that section is not determined^{[4], [10]}. In others, fault location is determined through communication^[11]. Certain schemes use iterative methods for determining fault location, but the execution time of such iterative methods is variable; their convergence is dependent upon the initial guesses and the numerical condition of various steps used in the process. In addition, the execution time increased with increasing distance to the fault point^[3],[6].

Some authors propose fault location methods by using a power probe unit (PPU) and a portable current injection kit (CIK), respectively^{[12]-[13],[36]}. However, these are offline techniques and can only be used once the faulted section is isolated by some other means. Also, as PPU or CIK are only used in locating the fault, these add extra costs to the system.

Traveling wave-based methods were used in a number of papers for locating faults in HVDC systems^[14],[15]. However, a traveling wave-based method is not practical for DC microgrids. Due to the complex topology of the distribution system, a large number of reflections take place, compromising the accuracy of the method^[16]. Additionally, very short feeder lengths, characteristic of DC microgrids, hamper the process of isolating traveling waves.

Machine learning-based approaches are also tried for DC microgrid protection. For example, two different Artificial Neural Networks (ANNs) were used for fault location and fault detection in a 4-bus ring type DC microgrid^[17]. This method is system dependent as any change in the network will require a new set of simulations to train the ANN again with new circuit parameters. It is also practically impossible to show that the method performs well for every fault at any distance with any fault resistance. Moreover, lack of field data compromises the validity of such machine learning based approaches.

The reason all methods proposed for single-ended fault location are system dependent is that the biggest hurdle for any single-ended fault location approach is the unknown fault resistance. Thus, many prior methods have drawbacks that they are either 1) system dependent; 2) need communication (not local); or 3) are not closed form (iterative).

SUMMARY

Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, may be learned from the description, or may be learned through practice of the embodiments.

In general, it is a present object to provide for a fast fault detection and location technique that uses only single-ended local measurements in time domain. A major hurdle in development of DC microgrids is fast and selective protection. This is being comprehensively solved by the presently disclosed technology.

The presently disclosed technology can also be potentially applicable for high voltage DC (HVDC), which is significant since HVDC lines are part of most power systems. The presently disclosed technology can also be applicable to voltage source converter (VSC)-based HVDC transmission lines.

To overcome above-referenced drawbacks, this disclosure develops a deterministic closed-form mathematical formulation using time domain data sampled at high frequency that makes the fault location immune to fault resistance. Because relatively higher frequencies in some environments can make the technology vulnerable to measurement noises, for some embodiments, filtering might be practiced to avoid any issue. Technology to sample voltage and current waveforms at sampling rates required by this formulation is already commercially implemented in AC power systems.

Since the formulation uses only the total resistance and inductance of the protected feeder, the method is topology-agnostic, thus amenable to be used on any feeder in any DC microgrid. It can be implemented in both radial and meshed networks. The only constraint is that the data should be sampled at a high enough frequency for the current derivative to be calculated accurately. By properly adjusting the sampling frequency, high-resistance faults can also be located by this method. The fault is detected and located simultaneously using only three fault samples, which means that for a sampling frequency of 1 MHz (assumed in this disclosure), the time taken is just 3 μs. Since commercially available relays already use this sampling frequency^[18] and oscilloscopes support even higher sampling frequencies^[19], this assumption is reasonable. Since the formulation uses the total resistance and inductance of only the protected feeder, the resulting method becomes system-independent, i.e., any change in the operating parameters of the system or any topological change in the network will not impact the detection or location of fault by this method. By properly adjusting the sampling frequency, high-resistance faults can also be detected and located by this method.

It is to be understood that the presently disclosed subject matter equally relates to associated and/or corresponding methodologies. One exemplary such method relates to a method of protecting a DC feeder electrical power network including the steps of: 1) providing one or more circuit breaker arrangements which, on activation, isolate electrical faults within the network; 2) sampling voltage and current of the network at a relatively high sampling rate; 3) determining the occurrence of and location of a fault in the network based on the sampled voltage and current; and 4) activating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

Another presently disclosed exemplary embodiment relates to a method of detecting and handling faults in a DC power transmission or distribution system network using only single-ended local measurements in time domain. Such method preferably comprises: 1) providing one or more circuit breaker arrangements which, on activation, isolate electrical faults within the network; 2) conducting three consecutive samplings of the network voltage and current at a relatively high sampling rate of up to about 1 MHz; 3) determining the occurrence of a fault in the network based on calculating a current derivative from the sampled voltage and current; and 4) activating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

Other example aspects of the present disclosure are directed to systems, apparatus, tangible, non-transitory computer-readable media, user interfaces, memory devices, and electronic devices for fault detection.

Another presently disclosed exemplary embodiment relates to a fault protection system for protecting a DC feeder electrical power network. Such system preferably comprises: 1) one or more circuit breaker arrangements which, on activation, isolate electrical faults within the network; 2) one or more processors programmed for sampling voltage and current of the network at a relatively high sampling rate; 3) determining the occurrence of and location of a fault in the network based on the sampled voltage and current; and 4) activating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

Additional objects and advantages of the presently disclosed subject matter are set forth in, or will be apparent to, those of ordinary skill in the art from the detailed description herein. Also, it should be further appreciated that modifications and variations to the specifically illustrated, referred and discussed features, elements, and steps hereof may be practiced in various embodiments, uses, and practices of the presently disclosed subject matter without departing from the spirit and scope of the subject matter. Variations may include, but are not limited to, substitution of equivalent means, features, or steps for those illustrated, referenced, or discussed, and the functional, operational, or positional reversal of various parts, features, steps, or the like.

Still further, it is to be understood that different embodiments, as well as different presently preferred embodiments, of the presently disclosed subject matter may include various combinations or configurations of presently disclosed features, steps, or elements, or their equivalents (including combinations of features, parts, or steps or configurations thereof not expressly shown in the figures or stated in the detailed description of such figures). Additional embodiments of the presently disclosed subject matter, not necessarily expressed in the summarized section, may include and incorporate various combinations of aspects of features, components, or steps referenced in the summarized objects above, and/or other features, components, or steps as otherwise discussed in this application. Those of ordinary skill in the art will better appreciate the features and aspects of such embodiments, and others, upon review of the remainder of the specification, and will appreciate that the presently disclosed subject matter applies equally to corresponding methodologies as associated with practice of any of the present exemplary devices, and vice versa.

These and other features, aspects and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the related principles.

BRIEF DESCRIPTION OF THE DRAWINGS

A full and enabling disclosure of the presently disclosed subject matter, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which:

FIG. 1A is an exemplary presently disclosed time domain representation schematic of a two bus DC circuit with ideal DC sources;

FIG. 1B is an exemplary presently disclosed s-domain representation schematic of a two bus DC circuit with ideal DC sources;

FIG. 2A is a presently disclosed exemplary graph of simulated and calculated currents from Bus 1 to fault for a fault at 80 m distance from Bus 1;

FIG. 2B is a presently disclosed exemplary graph of simulated and calculated currents from Bus 1 to fault for a fault at 40 m distance from Bus 1;

FIG. 3 is a representative schematic of a presently disclosed exemplary embodiment of a two bus DC microgrid, fed with converters;

FIG. 4 is a presently disclosed exemplary graph of currents through different components in a converter under normal load condition;

FIG. 5 is a presently disclosed exemplary comparison graph of fault currents sourced by an ideal source and a converter;

FIG. 6 is a representative flowchart of an exemplary presently disclosed embodiment for subject matter for detecting and locating fault(s);

FIG. 7 is a presently disclosed exemplary graph of calculated distances to fault point from Bus 1 and Bus 2;

FIG. 8 is a presently disclosed exemplary graph of current from Bus 1 to fault with varying fault resistance with ideal voltage source;

FIG. 9A is a presently disclosed exemplary graph of results of current from high resistance (Rf=2Ω) fault simulated at 80 m from Bus 1;

FIG. 9B is a presently disclosed exemplary graph of results of capacitor (source) voltage from high resistance (Rf=2Ω) fault simulated at 80 m from Bus 1;

FIG. 9C is a presently disclosed exemplary graph of results of calculated distance of fault point from Bus 1 and Bus 2 for a high resistance (Rf=2Ω) fault simulated at 80 m from Bus 1;

Table I is a chart of calculated distance x from Bus 1 to fault per a presently disclosed example in the subject specification;

Table II is a chart of parameters per a presently disclosed test system example in the subject specification;

Table III is a chart of performance of the presently disclosed method listing the sampling frequencies required to get the fault location error within ±1.5%;

Table IV is a chart of performance of the presently disclosed method with high resistance fault (Rf=2Ω) with increasing sampling frequency;

Table V is a chart of performance of the presently disclosed method with low resistance fault (Rf=0.01Ω) with decreasing sampling frequency;

Table VI is a chart of performance of the presently disclosed method with varying fault distance;

Table VII is a chart of performance of the presently disclosed method with varying DC link capacitor size;

Repeat use of reference characters in the present specification and drawings is intended to represent the same or analogous features or elements or steps of the presently disclosed subject matter.

DETAILED DESCRIPTION

Reference now will be made in detail to embodiments, one or more examples of which are illustrated in the drawings. Each example is provided by way of explanation of the embodiments, not limitation of the present disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the present disclosure. For instance, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. Thus, it is intended that aspects of the present disclosure cover such modifications and variations.

Introduction

The rest of the disclosure includes Section II, theoretical proof of the proposed method with ideal DC voltage sources; Section III, which validates the theory with simulated data; Section IV, which shows how the method is applicable to a practical test feeder fed by converter-based sources; Section V, which shows how the method can be adapted for any value of fault resistance; Section VI, which includes sensitivity analysis of this method with respect to various parameters; and Section VII, which concludes the disclosure and describes future work.

II. Derivation of Theory for the Proposed Method with Ideal Sources

A. Fault Currents

FIG. 1A shows a two-bus DC system with a DC feeder connected between Bus 1 and Bus 2. Two voltage sources with steady state values V₁ and V₂ are feeding the line from the two buses. At a distance x from Bus 1, a fault with a fault resistance R_f is assumed. Current I₀ is flowing from Bus 1 to Bus 2 before the fault. Due to short lines in DC microgrids, line capacitance is ignored in FIG. 1, and the line is approximated with an inductance and a resistance only. Other circuit parameters used in the development of theory are as follows:

R₁, L₁=resistance and inductance, respectively, of line section from Bus 1 to fault.

R₂, L₂=resistance and inductance, respectively, of line section from Bus 2 to fault.

R, L=total resistance and inductance of line.

r, I=resistance and inductance per unit length of the line.

${\mathrm{•\tau }}_L=\frac{L_1}{R_1}=\frac{L_2}{R_2}=\mathrm{time}\mathrm{constant}\mathrm{of}\mathrm{the}\mathrm{line}.$

i₁=Current from Bus 1 to fault.

i₂=Current from Bus 2 to fault.

FIG. 1B shows the s domain equivalent of the circuit of FIG. 1A. I₁(s) and I₂(s) denote the s domain equivalent of currents i₁ and i₂, respectively, and will be denoted simply as I₁ and I₂ during derivation. Applying KVL to the circuit in FIG. 1B, we get

(s²L₁+s(R₁+R_f))I₁+sR_fI₂=V₁+sL₁I₀   (1)

sR _f I ₁+(s²L₂+s(R₂+R_f))I₂=V₂−sL₂I₀   (2)

If Eqs. 1 and 2 are solved for I₁(s), I₂(s) and subsequent inverse Laplace transforms are performed to get i₁(t) and i₂(t), the following expressions are obtained:

i ¹(t)=K₁+K₃*e^{−(λL+λf)t}   (3)

i ₂(t)=K′₁+K′₃*e^{−(λL+λf)t}   (4)

where

${\lambda }_L=\frac{1}{{\tau }_L}=\frac{R}{L};{\lambda }_f=\frac{R_f}{L_p}=\frac{R_f}{L_1L_2}$

and K₁, K₃, K′₁, K′₃ are constants.

Stepwise derivation is provided in the supplementary material (Appendix A) submitted with this disclosure, and Appendix B calculates coefficients K₁ and K₃ for Section III using the relevant data from Eq. 13. Both Appendices A and B are part of this specification.

B. Fault Location Using Local Measurements

From Eqs. 3 and 4, the pre-fault current is

I ₀ =K ₁ +K ₃=−(K′₁+K′₃)   (5)

Subtracting lo from Eq. 3, and adding the result to Eq. 4, the following expressions can be obtained:

i ₁(t)−I₀=K₁+K₃*e^−(λLλf)t−K₁K₃⇒i₁(t)−I₀=K₃*(e^−(λLλf)t−1)   (6)

and,

i ₂(t)+I₀=K′₁+K′₃*e^{−(λL+λf)t}−K′₁−K′₃⇒i₂(i)+I₀=K′₃*(e^{−(λl+λf)t}−1)   (7)

Dividing Eq. 7 by Eq. 6, Eq. 8 is obtained:

$\begin{array}{cc}\frac{i_2\left(t\right)+I_0}{i_1\left(t\right)-I_0}=\frac{K_3^{\prime }}{K_3}=m& \left(8\right)\end{array}$ $⟹i_2\left(t\right)+I_0=m*\left(i_1\left(t\right)-I_0\right)$ $⟹i_2\left(t\right)=m*i_1\left(t\right)-\left(m+1\right)I_0$

If the instantaneous fault voltage during the fault is v_f(t), with corresponding source voltage at the sending end in FIG. 1A being v₁(t),

$\begin{array}{cc}{v}_1\left(t\right)=x\left[l*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}+{\mathrm{ri}}_1\left(t\right)\right]+v_f\left(t\right)& \left(9\right)\end{array}$ $⟹v_1\left(t\right)=x\left[l*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}+{\mathrm{ri}}_1\left(t\right)\right]+R_f\left(i_1\left(t\right)+i_2\left(t\right)\right)$

Using the expression of i₂(t) from Eq. 8 in Eq. 9 and re-organizing terms, Eq. 10 can be obtained:

$\begin{array}{cc}{v}_1\left(t\right)=x\left[l*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}+{\mathrm{ri}}_1\left(t\right)\right]+R_f\left(m+1\right)\left(i_1\left(t\right)-I_0\right)& \left(10\right)\end{array}$

If v₁, i₁,

$\frac{{\mathrm{di}}_1}{\mathrm{dt}}$

can be measured at two different times t₁ and t₂, Eq. 11 and Eq. 12 can be formed:

$\begin{array}{cc}{v}_1\left(t_1\right)=x\left[l*\frac{{\mathrm{di}}_1\left(t_1\right)}{\mathrm{dt}}+{\mathrm{ri}}_1\left(t_1\right)\right]+R_f\left(m+1\right)\left(i_1\left(t_1\right)-I_0\right)& \left(11\right)\end{array}$ $\begin{array}{cc}{v}_1\left(t_2\right)=x\left[l*\frac{{\mathrm{di}}_1\left(t_2\right)}{\mathrm{dt}}+{\mathrm{ri}}_1\left(t_2\right)\right]+R_f\left(m+1\right)\left(i_1\left(t_2\right)-I_0\right)& \left(12\right)\end{array}$

From Eqs. 11 and 12, the location of fault, x, can be expressed as:

$\begin{array}{cc}x=\frac{❘\begin{array}{cc}{v}_1\left(t_1\right)& i_1\left(t_1\right)-I_0\\ v_1\left(t_2\right)& i_1\left(t_2\right)-I_0\end{array}❘}{❘\begin{array}{cc}{l*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}❘}_{t=t_1}+r*i_1\left(t_1\right)& i_1\left(t_1\right)-I_0\\ {l*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}❘}_{t=t_2}+r*i_1\left(t_2\right)& i_1\left(t_2\right)-I_0\end{array}❘}& \left(13\right)\end{array}$

Notice that Eq. 13 provides a closed-form solution for fault location that does not include the fault resistance term R_f. Samples of voltage and current at time t₁ and t₂ can be measured, and if the sampling rate is high enough (1 MHz assumed in this disclosure), current derivative di₁/dt can also be accurately measured. Thus, Eqs. 11 and 12 can be solved for fault location x and R_f (m+1). Three consecutive readings are needed to solve the two equations, as two samples are needed to calculate di₁/dt. This translates to a solution time of just 3 μs. Note that R_f (m+1) is of no use, but x provides a closed-form solution for fault location in 3 μs. When the fault current will start to settle down, i.e.,

${{\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}❘}_{t=t_1}=\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}❘}_{t=t_2}\approx 0$

and i₁(t₁)≈i₁(t₂). In that case, both equations will have the same information, and the solutions will have the zero-determinant problem. So, it is important to use values during the transient state after a fault.

III. Validation of the Proposed Theory

To validate the theory developed in Section II, the circuit depicted in FIG. 1A is simulated in PSCAD with a sampling frequency of 1 MHz, meaning the sampled values are 1 μs apart. Rated system voltage is chosen to be 400 V, as it has been used in a number of papers for DC microgrids^[20]-[24]. A 100 m long Yorkshire conductor^[25] is chosen for the feeder. Circuit parameters are: r=1.37 mΩ/m, I=0.25 μH/m; V₁=400 V, V₂=395 V; R_f=0.01Ω; I₀=36.63 A. Fault resistance is taken as R_f=0.01Ω (low resistance) for this validation. Section V will show how the method can be extended to high-resistance faults.

Two faults are simulated at x⁽¹⁾=80 m and x⁽²⁾=40 m distance from Bus 1. The fault inception time was set at t₀=0.1 s for both cases. Currents from Bus 1 to fault (iBus1_sim) for both cases are plotted in FIG. 2.

For x⁽¹⁾=80 m case, L₁⁽¹⁾=20 μH; L₂⁽¹⁾=5 μH; R₁⁽¹⁾=109.6 mΩ; and R₂⁽¹⁾=27.4 mΩ. So, L_p⁽¹⁾=L₁⁽¹⁾∥L₂⁽¹⁾=4 μH;

${\lambda }_L=\frac{R}{L}=5480s^{-1}\mathrm{and}{\lambda }_f^{\left(1\right)}=\frac{R_f}{L_p^{\left(1\right)}}=\frac{0.01\Omega }{4\mathrm{\mu H}}=2500s^{-1}.$

To get the expression of current in form of Eq. 3, values of coefficients K₁⁽¹⁾ and K₃⁽¹⁾ are needed. A detailed calculation of the coefficients is provided in the supplementary material (Appendix B). From the calculated values, current i₁⁽¹⁾(t) is

i ₁ ⁽¹⁾(t)=2524.2843−2487.6497e^−7980*t

However, since the fault in the circuit was simulated at t₀=0.1 s, i₁⁽¹⁾(t) will be:

i ₁ ⁽¹⁾(t)=2524.2843−2487.6497e^{−7980*(t−0.1)}   (14)

The calculated current using Eq. 14 is plotted in FIG. 2A as iBus1_calc, and are superimposed on the simulated current. Similarly, simulated and calculated currents for fault at x⁽²⁾=40 m are plotted in FIG. 2B, which are also superimposed. This validates the theory of Section II-A.

To validate the method for fault location, measurements of three consecutive samples at three instances during the transient period after the fault initiation were made, and the fault distance was calculated using Eqs. 11 and 12 for each set of samples. In each case, the current derivative at a specific time-instant (say, t₂) was calculated using measurement at that time instant and the previous measurement, i.e.,

$\frac{{\mathrm{di}}_1\left(t_2\right)}{\mathrm{dt}}=\frac{i_1\left(t_2\right)-i_1\left(t_1\right)}{t_2-t_1}.$

Table I shows measured and calculated values at all three instances, for faults created at 80 m and 40 m from Bus 1. The calculated distance in each case is very close to the actual distance. The other variable being solved through Eqs. 11 and 12 is R_f(m+1), which is of no interest to fault location. This result validates the closed-form deterministic theoretical formulation developed in Section II-B. So, it can be concluded that fault distance can be calculated, even in the presence of fault resistance, using local measurements only (in 3 μs), using the closed-form deterministic solution developed in Section II-B. This is claimed to be a seminal contribution of this work.

IV. Performance of the Method with Non-Ideal Sources

When a fault occurs on a feeder-section in a DC microgrid, the current contributions from the DC link capacitors associated with converters dominate the fault current first^[4],[5]. As capacitors resist rapid change in voltage, for a short period of time after fault, the capacitor will act like a constant voltage DC source. Thus, measurements from this initial period can be used to determine the fault location modeled by Eqs. 11 and 12. This section describes the converter models, and fault detection and location on a feeder fed by converters.

A. LV DC Feeder Description

FIG. 3 shows a two-bus DC microgrid with DC-DC boost converters connected to the buses instead of ideal voltage sources. Feeder parameters are the same as taken in Section III. Parameters of this test system are listed in Table II. Feeder parameters are taken from known literature^[33] to match the ampacity of the 100-kW converter. As LVDC feeders are likely to be short in length, feeder capacitance was not considered in Section II-A while developing the theory. But, in practical cases, every cable is associated with some capacitance. So, the performance of the proposed method was verified with cable capacitance included in the simulation. Equivalent capacitance for the 100 m long cable was divided equally into two parts (C_cab in FIG. 3), which were connected on each end of the feeder to form a pi-section. Since the purpose of this disclosure is to illustrate the performance of the fundamental theory developed in presence of converters, the most basic unipolar microgrid with T(earth)N(neutral) grounding scheme^[26] is chosen, where the grid is unipolar and the neutral is solidly grounded^{[22], [27]}. The protective device based on the proposed theory is placed only on the positive pole^[22].

The DC-DC boost converter model is taken from published literature ^[28]. Converter parameters are chosen using typical values for a 100-kW converter and verified through a number of resources^{[11], [23], [29], [30]}. It is assumed that the converter has an ideal DC voltage source at its low voltage side, representing a PV panel or a battery. This is justified since the method is implemented in microseconds, and the input voltage can be assumed to be constant during that time. This is also justified since the inductor at the input side of the converter (L_cnv) shown in FIG. 3, which is placed to filter out the ripple in the input DC current^{[37], [38]} will oppose any sudden change in current. Within the time frame of a few microseconds after fault inception when the method is applied, any rapid change in the input current is restricted by this inductor, and the voltage across the input source, therefore, remains constant. This was tested by replacing the ideal DC input source in FIG. 3 with a practical input source comprised of a battery in parallel with an input capacitor, and the hypothesis was therefore validated. The duty cycle is kept fixed since the initial period after fault is governed by the natural response of an RLC circuit^{[4], [5], [20], [30]} and the converter control would not activate during that time. Load current is 247 A, representing almost the full load in the system.

B. Currents Under Normal Loading and Fault Conditions in Converter Interfaced Feeders

FIG. 4 shows currents through diode (iBus1_cnv-d), through capacitor (iBus1_cnv-c), the summation of the two (total current iBus1_cnv), and the output voltage of the converter (vBus1) for the converter connected to Bus 1 in FIG. 3. It can be seen that the output current and voltage are practically constant throughout the time. The capacitor current and the diode current change depending on the switching of the IGBT.

A fault was simulated in the DC feeder of FIG. 3 at 0.1 s with a fault resistance of R_f=0.01Ω at a distance x=80 m from Bus 1. The simulation was run for 0.2 s. FIG. 5 shows the currents through different components under this fault condition current through diode iBus1_cnv-d, current through capacitor iBus1_cnv-c, total current from Bus 1 to fault iBus1_cnv.

The same circuit then was simulated replacing the converters on the two buses with ideal DC sources. The voltages of the DC sources were set at the pre-fault voltages of Bus 1 and Bus 2 of the DC feeder with converters. The current from Bus 1 to fault from the circuit with the ideal DC source was plotted in FIG. 5 (iBus1_vs). Notice that total currents from Bus 1 to fault in both cases are practically equal to each other for much longer than 3 μs (equivalent to 3 samples here) after the fault initiation. Thus, Eqs. 11 and 12 can also be applied to DC feeders fed by converters.

C. Fault Detection and Fault Location

Detecting a fault is necessary before applying the proposed method to locate it. This Section shows how Eq. 13 can be used for fault detection as well. If voltage drop per unit length of line is denoted as vu(t), i.e.,

$\mathrm{vu}\left(t\right)=I*\frac{{\mathrm{di}}_1\left(t\right)}{\mathrm{dt}}+r*i_1\left(t\right),$

Eq. 13 becomes

$\begin{array}{cc}x=\frac{❘\begin{array}{cc}{v}_1\left(t_1\right)& i_1\left(t_1\right)-I_0\\ v_1\left(t_2\right)& i_1\left(t_2\right)-I_0\end{array}❘}{❘\begin{array}{cc}{v}_u\left(t_1\right)& i_1\left(t_1\right)-I_0\\ v_u\left(t_2\right)& i_1\left(t_2\right)-I_0\end{array}❘}& \left(15\right)\end{array}$

Under normal loading condition, as seen in FIG. 4, the converter output voltage and current remain practically constant, i.e., v₁(t₁)≈v₁(t₂). Voltage drop across the unit length of line can also be assumed constant, i.e., v_u(t₁)≈v_u(t₂). So,

$\begin{array}{cc}x\approx \frac{❘\begin{array}{cc}{v}_1\left(t_1\right)& i_1\left(t_1\right)-I_0\\ v_1\left(t_1\right)& i_1\left(t_2\right)-I_0\end{array}❘}{❘\begin{array}{cc}{v}_u\left(t_1\right)& i_1\left(t_1\right)-I_0\\ v_u\left(t_1\right)& i_1\left(t_2\right)-I_0\end{array}❘}⟹x\approx \frac{v_1\left(t_1\right)*\left(i_1\left(t_2\right)-i_1\left(t_1\right)\right)}{v_u\left(t_1\right)*\left(i_1\left(t_2\right)-i_1\left(t_1\right)\right)}⟹x\approx \frac{v_1\left(t_1\right)}{v_u\left(t_1\right)}& \left(16\right)\end{array}$

But v₁(t)=L_line*v_u(t)+v₂(t), where L_line is the length of the line. So,

$x\approx \frac{L_{\mathrm{line}}*v_u\left(t_1\right)+v_2\left(t_1\right)}{v_u\left(t_1\right)}$ $⟹x\approx L_{\mathrm{line}}+\frac{v_2\left(t_1\right)}{v_u\left(t_1\right)}$

Eq. 17 implies that under normal operation, the calculated length of fault point from Bus 1 will be larger than the line length. In case of Bus 2, the current in the line is flowing towards the bus. As a result, from the perspective of Bus 2, both the measured current i₂(t) and the voltage drop per unit length of line, v_u(t) are negative. So, from Eq. 16, x becomes a negative number under normal operating condition. Thus, under unfaulted condition, the distance measured will be either greater than the line length or negative. This can be used to distinguish pre-fault condition from fault condition, and hence, can detect a fault. Note that the pre-fault current has to be used with care in this approach. Since the load current can change over time, the pre-fault current should be updated with every new sample if no fault is detected. But, once a fault is detected, the pre-fault current should be fixed at its latest updated value during the fault location process. FIG. 6 shows the flowchart of the proposed fault detection and location.

D. Results

To implement methodology herewith, especially as represented by algorithm and flowchart information presently disclosed, one or more processors may be provided, programmed to perform the steps and functions called for by the algorithm and flowchart information, as will be understood by those of ordinary skill in the art.

To evaluate the performance of the algorithm developed in Section IV-C, data were generated from the fault simulation described in Section IV-B with sampling frequency of 1 MHz. To implement the flowchart of FIG. 6, a moving window consisting of three samples was run through the accumulated data from the simulation to calculate the fault distance before and after the fault initiation. FIG. 7 shows the calculated distance of fault from Bus 1 (dist_Bus1) and Bus 2 (dist_Bus2) from 10 μs before fault inception to 10 μs after fault inception. Clearly, before fault inception the distance from Bus 1 is much larger than the line length, and the distance from Bus 2 is negative, as discussed in Section IV-C. Within 3 samples after the fault inception (at t₀=0.1 s), calculated distances become almost equal to the actual distances of the fault point on the line. Thus, both detection and location of fault are correctly and accurately performed simultaneously in 3 μs after inception of fault.

The accumulated data spanned from 40 μs before the fault inception to 80 ∞s after. From the 3rd sample after the fault inception time to the end of accumulated data, the calculated distances from Bus 1 varied from 79.8 m to 81.4 m. Thus, the proposed method provides accurate fault location over an extended range of data points after fault.

E. A Special Case

Clearly, the derivation of theory assumes DC sources present at both ends of the feeder. Since most of the DC loads and all non-ideal sources connect through converters, this is a reasonable assumption. A DC bus with only purely resistive load is therefore a rare case. However, it should be mentioned that under this unlikely scenario, one of the sources in FIG. 1A (e.g., V₂) will be replaced by a load resistance. This will drastically alter the nature of the current i₂(t) during fault, and the value of m in Eq. 8 will no longer be constant. This means the two foundational Eq. 11 and Eq. 12 that require m to be a constant will no longer be valid, and the method will therefore fail.

It is important to mention here that the DC feeder analyzed here would typically be a part of a DC microgrid. This special case can occur only if such microgrid is single-sourced and there is no converter-based load in the microgrid. This is contrary to the very nature of microgrids, and therefore, this special case would be rare in practice.

V. Using the Method for High Resistance Faults

In order to use the method for high resistance faults, the impact of higher fault resistance on the fault-induced transient needs to be understood. From Eq. 3, fault current in a feeder fed by an ideal source is

$\begin{array}{cc}{i}_1\left(t\right)=K_1+K_3*e^{-\left({\lambda }_L+{\lambda }_f\right)t}⟹i_1\left(t\right)=K_1+K_3*e^{-\left(\frac{R}{L}+\frac{R_f}{L_p}\right)t}⟹i_1\left(t\right)=K_1+K_3*e^{-\left(\frac{1}{{\tau }_L}+\frac{1}{{\tau }_f}\right)t}⟹i_1\left(t\right)=K_1+K_3*e^{-\frac{t}{{\tau }_T}}& \left(18\right)\end{array}$

where, τ_T is the equivalent time constant, and

$\begin{array}{cc}\frac{1}{{\tau }_T}=\frac{1}{{\tau }_L}+\frac{1}{{\tau }_f}& \left(19\right)\end{array}$

Also, τ_T=L/R=time constant of line, and

${\tau }_f=\frac{L_p}{R_f}=\frac{L_1❘❘L_2}{R_f}=\mathrm{time}\mathrm{constant}\mathrm{of}\mathrm{fault}.$

From Eq. 19, τ_T is smaller than both τ_L and τ_f. The smaller the value of τ_T, shorter the time the transient will last. Therefore, as the value of R_f increases, the transient period will be shorter. FIG. 8 shows simulated currents from the circuit of FIG. 1A, with varying fault resistances to verify this argument. In addition, the shorter transient also gets steeper, increasing the chances of erroneous calculation of di/dt. Therefore, to accurately determine location with high resistance faults, sampling frequency needs to be increased, so the required samples with adequate sampling rate for accurate calculation of di/dt can be obtained before the transient subsides.

According to the IEEE Power System Relaying Committee report^[31], a fault is considered a high impedance fault if it results in currents comparable to load currents, not detectable by traditional overcurrent relays or fuses. Based on the converter rating of 400 V, 100 kW, the corresponding load current and load resistance are 250 A and 1.6Ω, respectively. Therefore, any fault with resistance 1.6Ω or higher is considered a high resistance fault for this system.

A fault is simulated in the system described in Section IV-A with R_f=2Ω, at fault inception time t₀=0.1 s, at a distance of 80 m from Bus 1. From the manufacturer's data sheet of the chosen 185 sq mm conductor^[33], τ_L≈2955.6 μs and τ_f≈2.3432 μs. According to Eq. 19, τ_T≈2.34 μs. According to the literature^[32], the transient will settle down approximately within 5τ_T≈11.71 μs after the fault inception. The current plot in FIG. 9A from the simulation supports the argument.

Observe from the voltage plot of FIG. 9B that the change in the capacitor voltage before the current settles to steady state is less than 0.82% of the initial voltage. This phenomenon is characteristic of high resistance faults. Because of low fault currents and fast transients, capacitors do not lose much charge and the voltage remains practically constant. Thus, the proposed theory, developed with ideal voltage sources, can be used to determine fault location for high resistance faults.

FIG. 9C shows the plot of the calculated distance to the fault point from Bus 1 for this high resistance fault simulated at 1 MHz sampling rate. With this sampling rate, it is expected that the method will provide fault location for up to approximately 10 samples after fault inception. FIG. 9C shows that the method provides rational (though incorrect) answers for approximately 15 μs after fault inception. Then, the calculations are affected due to the determinant in Eq. 14 getting close to zero in steady state.

Clearly, there is a significant error in fault location. This is because errors are introduced in the calculation of di/dt due to the much steeper exponential transient. To minimize this error, a higher sampling frequency is required. Table IV confirms this rationale. Conversely, it can be argued that lower sampling rates would suffice for faults with low fault resistances. In the fault simulation case with R_f=0.01Ω in Section IV-B, data were sampled at 1 MHz frequency. The same circuit was simulated and sampled at lower frequencies and the proposed algorithm was implemented for the same amount of time to check the performance of this method at lower frequencies. Table V shows the results. Data points from lower sampling frequency cases result in higher error, but even with 100 kHz sampling frequency, the error is less than 5%. These results illustrate that as long as the sampling frequency is adequate, the proposed method provides accurate results regardless of fault resistance.

To further investigate the performance of the method for high resistance faults, faults with resistances ranging from 0.01Ω to 100Ω were simulated. Table III lists the sampling frequencies required to get the fault location error within ±1.5%. These results illustrate that as long as the sampling frequency is adequate, the proposed method provides accurate results, regardless of fault resistance. The state-of-the-art oscilloscopes have probes that can sample up to 100 GHz^[19], which would enable the method to work for higher fault resistance values as well.

It should be mentioned that all the faults considered were purely resistive. In AC distribution systems, High Impedance Fault (HIF) has a complex model with non-linear elements like diodes and variable resistors, to capture the results obtained by staged faults^[39]. This model represents the arcing that almost always accompanies such faults, which, depending on the ground-surface in the fault path, changes significantly, producing different amounts of heat, making the fault resistance change randomly. Such models have not been developed for faults on low voltage DC circuits, and hence out of scope of this disclosure.

VI. Sensitivity Analysis

A. Fault Distance

As

${\tau }_f=\frac{L_p}{R_f}=\frac{L_1❘❘L_2}{R_f}$

the less L₁ or L₂ will be, the less L_p will become, which will eventually result in lower τ_f. So, if the fault is very close to or very far from the bus, τ_f will be smaller, and according to the trend seen in Section V, errors will be higher, potentially requiring higher sampling frequency. To examine the sensitivity of the method to fault distance, several simulations were performed with varying fault distances and R_f=0.01Ω in the system of FIG. 3. Then, sampling frequency was varied to examine the impact on the location error. Results are tabulated in Table VI and support the argument. Notice that with 1 MHz sampling frequency, the error is quite low for all fault locations, indicating low sensitivity to fault distance and thus, there may not be any need assumed sampling frequency.

B. DC Link Capacitor Size

The proposed fault location method is accurate because the DC link capacitor behaves like an ideal DC source for a short duration after the initiation of a fault; however, the time duration for which the response of the capacitor can be treated as the response of an ideal DC source is dependent on the size of the capacitor. Given the fault resistance, line parameters, and fault distance is fixed, this duration gets larger if the capacitor size (in Farad) gets larger. With the advancement in power electronics and high-speed switching devices, the capacitor size used at the output of converters is getting reduced since the high-speed switching devices can support higher switching frequency. Thus, it is important to check how the method performs with lower values of DC link capacitance.

A general approach to calculating the size of the output capacitor of a DC-DC boost converter is to use the concept of charge balance. According to this concept, during steady state, the average change of the stored charge and, hence, the average change in the capacitor voltage will be zero over a switching period. From Eq. 20, which can be derived from prior publications^[30,38], the minimum capacitance C required to restrict the ripple at the converter output within Δv_max can be obtained.

$\begin{array}{cc}C\ge \frac{{\mathrm{IT}}_s}{8\Delta v_{\max }}& \left(20\right)\end{array}$

Here, 2Δv_max=ripple voltage (peak-to-peak), I=average inductor current, C=DC-link capacitor value, and T_s=switching-period.

Several simulations were performed in the circuit of FIG. 3, adjusting the DC-link capacitor size and the switching frequency according to Eq. 20. Location error was calculated for R_f=0.01Ω and R_f=0.1Ω. Table VII shows the results. It can be seen that even with a very low capacitor size (associated with very high switching frequency), the method performs well.

VII. Conclusion

This disclosure develops a deterministic closed-form mathematical model based on the time-domain physical model of a faulted DC feeder. It is shown that as long as the sampling frequency is high enough to enable accurate calculation of the current derivative (di/dt), the single-ended fault detection and location method derived from this model is immune to fault resistance. This overcomes a well-known hurdle encountered in all single-ended fault location methods proposed in literature. The method is shown to work even when the feeder is fed by converter-based practical DC sources. The detection and location happen simultaneously in 3 samples after inception of fault, which translates to 3 μs for a sampling rate of 1 MHz. This assures the safety of circuit breakers as well as converters. The method works well even for high resistance faults, if the sampling frequency can be increased, a condition that is not unreasonable with the technology available today, as oscilloscopes in the market^[19] support sampling frequency of up to 100 GHz. Since the purpose of this disclosure is to disseminate the seminal theory that enables this application, a single DC feeder is simulated for validation. Future work will be focused on extending the application to build a coordinated protection scheme for an entire DC microgrid.

Moreover, this disclosure reports the discovery of the mathematical foundations and implementation of a fast fault location method for a DC feeder that is independent of the topology of the system built around the feeder. This opens the doors for a communication-free topology-independent protection scheme for an entire DC microgrid. Such a scheme could use the presently disclosed method as a time-domain distance relay, placed on each side of every feeder of a DC microgrid. It could also be possible to adapt the performance of the presently disclosed method for different grounding schemes in a DC microgrid. Further research can be performed to include feeder capacitance in the formulation to adapt the method for HVDC lines fed by voltage source converters (VSCs).

While the present subject matter has been described in detail with respect to specific example embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example rather than by way of limitation, and the subject disclosure does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.

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APPENDIX A

DETAILED PROOF OF FAULT CURRENT EXPRESSION IN DC MICROGRIDS WITH IDEAL VOLTAGE SOURCES Applying KVL in loop 1 for FIG. 1b, the following can be obtained

$\begin{array}{cc}-V_1/s-L_1{I}_0+\left(s*L_1+R_1\right)I_1+R_f\left(I_1+I_2\right)=0\left({\mathrm{sL}}_1+R_1+R_f\right)I_1+R_f{I}_2=V_1/s+L_1{I}_0\left(s^2{L}_1+s\left(R_1+R_f\right)\right)I_1+{\mathrm{sR}}_f{I}_2=V_1+{\mathrm{sL}}_1{I}_0& \left(1\right)\end{array}$

Similarly in loop 2,

$\begin{array}{cc}-V_2/s+L_2{I}_0+\left({\mathrm{sL}}_2+R_2\right)I_2+R_f\left(I_2+I_1\right)=0R_f{I}_1+\left({\mathrm{sL}}_2+R_2+R_f\right)I_2=V_2/s-L_2{I}_0{\mathrm{sR}}_f{I}_1+\left(s^2{L}_2+s\left(R_2+R_f\right)\right)I_2=V_2-{\mathrm{sL}}_2{I}_0& \left(2\right)\end{array}$

From equations 1 and 2 we can get

$\begin{array}{cc}{I}_1=\frac{{\Delta }_1}{\Delta }:I_2=\frac{{\Delta }_2}{\Delta }& \left(A\text{.1}\right)\end{array}$ $\mathrm{where},$ $\begin{array}{cc}\Delta =❘\begin{array}{cc}{s}^2{L}_1+s\left(R_1+R_f\right)& {\mathrm{sR}}_f\\ {\mathrm{sR}}_f& s^2{L}_2+s\left(R_2+R_f\right)\end{array}❘& \left(A\text{.2}\right)\end{array}$ $\Delta =s^2\left[\left({\mathrm{sL}}_1+\left(R_1+R_f\right)\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f^2\right]$ $\Delta =s^2\left[s^2{L}_1{L}_2+s*\left(L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)\right)+\left(R_1+R_f\right)\left(R_2+R_f\right)-R_f^2\right]$ $\Delta =s^2\left[s^2{L}_1{L}_2+s*\left(L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)\right)+R_1{R}_2+R_1{R}_f+R_2{R}_f\right]$ $\mathrm{and},$ $\begin{array}{cc}\Delta =❘\begin{array}{cc}{V}_1+{\mathrm{sL}}_1{I}_0& {\mathrm{sR}}_f\\ V_2+{\mathrm{sL}}_2{I}_0& s^2{L}_2+s\left(R_2+R_f\right)\end{array}❘{\Delta }_1=s\left[\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)\right]& \left(A\text{.3}\right)\end{array}$ $\mathrm{and},$ $\begin{array}{cc}{\Delta }_2=❘\begin{array}{cc}{s}^2{L}_1+s\left(R_1+R_f\right)& V_1+{\mathrm{sL}}_1{I}_0\\ {\mathrm{sR}}_f& V_2+{\mathrm{sL}}_2{I}_0\end{array}❘{\Delta }_2=s\left[\left(V_2-{\mathrm{sL}}_2{I}_0\right)\left({\mathrm{sL}}_1+\left(R_1+R_f\right)\right)-R_f\left(V_1+{\mathrm{sL}}_1{I}_0\right)\right]& \left(A\text{.4}\right)\end{array}$

Putting the values of Δ₁ and Δin eqn. A1 I₁ can be expressed as

$\begin{array}{cc}{I}_1=\text{?}{I}_1=\text{?}& \left(A\text{.5}\right)\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

Let's say the denominator of eqn. A5 is (L₁L₂)*(as²+bs+c) where

$\begin{array}{cc}a=1b=\frac{L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)}{L_1{L}_2}c=\frac{R_1{R}_2+R_1{R}_f+R_2{R}_f}{L_1{L}_2}& \left(A\text{.6}\right)\end{array}$

Roots of as²+bs+c=0 are

$\begin{array}{cc}{r}_1,r_2=\frac{-b\pm \sqrt{b^2-4\mathrm{ac}}}{2a}{r}_1,r_2=1/2*(-b/a\pm \sqrt{{\left(b/a\right)}^2-4\left(c/a\right))}& \left(A\text{.7}\right)\end{array}$ $\mathrm{Now},$ $\begin{array}{cc}\frac{b}{a}=\frac{L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)}{L_1{L}_2}\frac{b}{a}=\frac{R_2+R_f}{L_2}+\frac{R_1+R_f}{L_1}\frac{b}{a}=\frac{R_2}{L_2}+\frac{R_f}{L_2}+\frac{R_1}{L_1}+\frac{R_f}{L_1}\frac{b}{a}=\frac{R_1}{L_1}+\frac{R_2}{L_2}+R_f\left(\frac{1}{L_1}+\frac{1}{L_2}\right)\frac{b}{a}=\frac{R_1}{L_1}+\frac{R_2}{L_2}+\frac{R_f}{L_p}& \left(A\text{.8}\right)\end{array}$

where, 1/L_p=1/L₁+1/L₂, parallel equivalent inductance of L₁, L₂.

• But, R₁/L₁=R₂/L₂=1/τ_L=λ_L, where τ_L=time contant of line.
• Let's say λ_f=1/τ_L=F_f/L_p

So, from eqn. A.8

$\begin{array}{cc}\frac{b}{a}={\lambda }_L+{\lambda }_L+{\lambda }_f\frac{b}{a}=2{\lambda }_L+{\lambda }_f& \left(A\text{.9}\right)\end{array}$ $\mathrm{Now},$ $\begin{array}{cc}4\left(\frac{c}{a}\right)=4*\left(\frac{R_1{R}_2+R_1{R}_f+R_2{R}_f)}{L_1{L}_2}\right)4\left(\frac{c}{a}\right)=4*\left[\frac{R_1{R}_2}{L_1{L}_2}+\frac{\left(R_1+R_2\right)R_f}{L_1{L}_2}\right]4\left(\frac{c}{a}\right)=4*\left[{\lambda }_L^2+\frac{\left(R_1+R_2\right)R_f}{\frac{\left(L_1+L_2\right)L_1\text{?}}{\left(L_1+L_2\right)}}\right]4\left(\frac{c}{a}\right)=4*\left[{\lambda }_L^2+\frac{{\mathrm{RR}}_f}{{\mathrm{LL}}_p}\right]4\left(\frac{c}{a}\right)=4*\left[{\lambda }_L^2+{\lambda }_L*{\lambda }_f\right]& \left(A\text{.10}\right)\end{array}$ $\mathrm{Now},$ $\begin{array}{cc}\begin{array}{c}\sqrt{{\left(\frac{b}{a}\right)}^2-4\left(\frac{c}{a}\right)}=\sqrt{{\left(2{\lambda }_L+{\lambda }_f\right)}^2-4\left[{\lambda }_L^2+{\lambda }_L+{\lambda }_f\right]}\\ =\sqrt{4\text{?}+4{\lambda }_L{\lambda }_f+{\lambda }_f^2-4{\lambda }_L^2-4{\lambda }_L{\lambda }_f}\\ =\sqrt{{\lambda }_f^2}\\ ={\lambda }_f\end{array}& \left(A\text{.11}\right)\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

Now, roots from eqn. A.7

$\begin{array}{cc}{r}_1,r_2=\frac{1}{2}*\left[-\left(2{\lambda }_L+{\lambda }_f\right)\pm {\lambda }_f\right]r_1=-{\lambda }_L;r_2=-\left({\lambda }_L+{\lambda }_f\right)& \left(A\text{.12}\right)\end{array}$

If eqn. A.5 is expanded through partial fraction expansion and subsequent inverse Laplace transform is done on that, the current expressions will get the following forms.

$\begin{array}{cc}{I}_1\left(s\right)=\frac{K_1}{s-0}+\frac{K_2}{s-r_1}+\frac{K_3}{s-r_2}& \left(A\text{.13}\right)\end{array}$ $\mathrm{and},$ $\begin{array}{cc}{i}_1\left(t\right)=K_1+K_2*\text{?}+K_3*\text{?}& \left(A\text{.14}\right)\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

It can be shown that, in eqn. A.14 the coefficient K₂=0. The coefficient K₂ will be

$\begin{array}{cc}{K}_2=\left(s+{\lambda }_L\right)I_1\left(s\right)\text{?}& \left(A\text{.15}\right)\end{array}$ $K_2=\left(s+{\lambda }_L\right)\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\begin{array}{c}\text{?}[\left(L_1{L}_2\right)s^2+\left(L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)\right)s+\\ \left(R_1{R}_2+R_1{R}_f+R_2{R}_f\right)]\end{array}}\text{?}$ $K_2=\left(s+{\lambda }_L\right)\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\left(L_1{L}_2\right)*s\left(s+{\lambda }_L\right)\left(s+{\lambda }_L+{\lambda }_f\right)}\text{?}$ $K_2=\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\left(L_1{L}_2\right)*s\left(s+{\lambda }_L+{\lambda }_f\right)}\text{?}$ $\text{?}\text{indicates text missing or illegible when filed}$

Numerator of eqn. A15 can be reorganized as follows

$\begin{array}{cc}=\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)& \left(A\text{.16}\right)\end{array}$ $={\mathrm{sL}}_2{V}_1+V_1{R}_2+V_1{R}_f+s^2{L}_1{L}_2{I}_0+{\mathrm{sL}}_1{R}_2{I}_0+{\mathrm{sL}}_1{R}_f{I}_0-R_f{V}_2+{\mathrm{sL}}_2{R}_f{I}_0$ $=s^2{L}_1{L}_2{I}_0+s\left(L_2{V}_1+L_1{R}_2{I}_0+L_1{R}_f{I}_0+L_2{R}_f{I}_0\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=s^2{L}_1{L}_2{I}_0+{\mathrm{sL}}_2{V}_1+{\mathrm{sI}}_0\left(L_1{R}_2+L_1{R}_f+L_2{R}_f\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=s^2{L}_1{L}_2{I}_0+{\mathrm{sL}}_2{V}_1+{\mathrm{sI}}_0\left(L_1{R}_2+\left(L_1+L_2\right)R_f\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=s^2{L}_1{L}_2{I}_0+{\mathrm{sL}}_2{V}_1+{\mathrm{sI}}_0\left(L_1{R}_2+{\mathrm{LR}}_f\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=s^2{L}_1{L}_2{I}_0+{\mathrm{sL}}_2{V}_1+{\mathrm{sL}}_1{R}_2{I}_0+{\mathrm{sLR}}_f{I}_0+V_1{R}_2+R_f\left(V_1-V_2\right)$

From the prefault circuit I₀=(V₁−V₂)/R, so the numerator comes

$\begin{array}{cc}=s^2{L}_1{L}_2\left(\frac{V_1-V_2}{R}\right)+{\mathrm{sL}}_2{V}_1+{\mathrm{sL}}_1{R}_2\left(\frac{V_1-V_2}{R}\right)+{\mathrm{sLR}}_f\left(\frac{V_1-V_2}{R}\right)+V_1{R}_2+R_f\left(V_1-V_2\right)& \left(A\text{.17}\right)\end{array}$

When evaluated at s=−λ_L, the numerator becomes

$\begin{array}{cc}={\left(-{\lambda }_L\right)}^2{L}_1{L}_2\left(\frac{V_1-V_2}{R}\right)+\left(-{\lambda }_L\right)L_2{V}_1+\left(-{\lambda }_L\right)L_1(R_2\left(\frac{V_1-V_2}{R}\right)+\left(-{\lambda }_L\right){\mathrm{LR}}_f\left(\frac{V_1-V_2}{R}\right)+V_1{R}_2+R_f\left(V_1-V_2\right)& \left(A\text{.18}\right)\end{array}$ $={\left(-\frac{R}{L}\right)}^2{L}_1{L}_2\left(\frac{V_1-V_2}{R}\right)+\left(-\frac{R}{L}\right)L_2{V}_1+\left(-\frac{R}{L}\right)L_1{R}_2\left(\frac{V_1-V_2}{R}\right)+\left(-\frac{R}{L}\right){\mathrm{LR}}_f\left(\frac{V_1-V_2}{R}\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=\frac{{\mathrm{RL}}_1{L}_2}{L^2}\left(V_1-V_2\right)-\frac{{\mathrm{RL}}_2}{L}{V}_1-\frac{L_1{R}_2}{L}\left(V_1-V_2\right)-R_f\left(V_1-V_2\right)+V_1{R}_2+R_f\left(V_1-V_2\right)$ $=\frac{{\mathrm{RL}}_1{L}_2}{L^2}\left(V_1-V_2\right)-\frac{L_1{R}_2}{L}\left(V_1-V_2\right)+V_1{R}_2-\frac{{\mathrm{RL}}_2}{L}{V}_1$ $=\frac{L_1}{L}\left(\frac{{\mathrm{RL}}_2}{L}-R_2\right)\left(V_1-V_2\right)+\left(R_2-\frac{{\mathrm{RL}}_2}{L}\right)V_1$

But from line parameter, R₂/L₂=R/L, i.e., R₂=RL₂/L. So the numerator becomes

$\begin{array}{cc}=\frac{L_1}{L}\left(\frac{{\mathrm{RL}}_2}{L}-R_2\right)\left(V_1-V_2\right)+\left(R_2-\frac{{\mathrm{RL}}_2}{L}\right)V_1=\frac{L_1}{L}\left(R_2-R_2\right)\left(V_1-V_2\right)+\left(R_2-R_2\right)V_1=0& \left(A\text{.19}\right)\end{array}$

This means coefficient K₂=0 and eventually current i₁(t) reduces to

$\begin{array}{cc}{i}_1\left(t\right)=K_1+K_2*\text{?}& \left(3\right)\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

So the current i₁(t) can be represented through one exponent. In a similar fashion, expression for i₂(t) can be derived and written as

$\begin{array}{cc}{i}_2\left(t\right)=K_1^{\prime }+\text{?}& \left(4\right)\end{array}$ $\text{?}\text{indicates text missing or illegible when filed}$

APPENDIX B

CALCULATION OF COEFFICIENTS

In this section, coefficients K₁ and K₂ are calculated for section III using the relevant data. From eqn. A13

$K_1=s*I_1\text{?}$ $K_1=s*\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\begin{array}{c}s[\left(L_1{L}_2\right)s^2+\left(L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)\right)s+\\ \left(R_1{R}_2+R_1{R}_f+R_2{R}_f\right))]\end{array}}\text{?}$ $K_1=\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\begin{array}{c}s[\left(L_1{L}_2\right)s^2+\left(L_1\left(R_2+R_f\right)+L_2\left(R_1+R_f\right)\right)s+\\ \left(R_1{R}_2+R_1{R}_f+R_2{R}_f\right))]\end{array}}\text{?}$ $K_1=\frac{V_1\left(R_2+R_f\right)-R_f{V}_2}{R_1{R}_2+R_1{R}_f+R_2{R}_f}$ $K_1=2524.2843$ $\mathrm{Similarly}$ $\text{?}=\left(s+{\lambda }_L+{\lambda }_f\right)*I_1\text{?}$ $K_3=\left(s+{\lambda }_L+{\lambda }_f\right)*\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\left(L_1{L}_2\right)*s\left(s+{\lambda }_L\right)\left(s+{\lambda }_L+{\lambda }_f\right)}\text{?}$ $K_3=\frac{\left(V_1+{\mathrm{sL}}_1{I}_0\right)\left({\mathrm{sL}}_2+\left(R_2+R_f\right)\right)-R_f\left(V_2-{\mathrm{sL}}_2{I}_0\right)}{\left(L_1{L}_2\right)*s\left(s+{\lambda }_L\right)}\text{?}$ $K_3=-2487.6497$ $\text{?}\text{indicates text missing or illegible when filed}$

Claims

1. A method of protecting a DC feeder electrical power network, the method including the steps of: providing one or more circuit breaker arrangements which on activation isolate electrical faults within the network;sampling voltage and current of the network at a relatively high sampling rate;determining the occurrence of and location of a fault in the network based on the sampled voltage and current; andactivating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

2. A method as in claim 1, wherein said determining includes calculating a current derivative.

3. A method as in claim 2, wherein said relatively high sampling rate is in a range between 100 KHz and 10 MHz.

4. A method as in claim 3, wherein said relatively high sampling rate is up to about 1 MHz.

5. A method as in claim 2, wherein said determining includes conducting three consecutive samplings of the voltage and current at up to about 1 MHz sampling rate.

6. A method as in claim 5, wherein said determining includes solving the equations:

7. A method as in claim 6, wherein solution for fault location x is determined by solving the equation:

8. A method as in claim 1, wherein the DC feeder electrical power network comprises at least one of a DC microgrid feeder and high voltage DC (HVDC) lines.

9. A method as in claim 1, wherein the circuit breaker arrangements are placed only on the positive pole of the DC feeder electrical power network.

10. A method of detecting and handling faults in a DC power transmission or distribution system network using only single-ended local measurements in time domain, using closed-form deterministic solution for fault location, such method comprising: providing one or more circuit breaker arrangements which on activation isolate electrical faults within the network;conducting three consecutive samplings of the network voltage and current at a relatively high sampling rate of up to about 1 MHz;determining the occurrence of a fault in the network based on calculating a current derivative from the sampled voltage and current; andactivating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

11. A method as in claim 10, further including determining the location of the determined fault in the network using a closed-form deterministic solution for fault location.

12. A method as in claim 11, wherein solution for fault location x is determined by solving the equation:

13. A method as in claim 10, wherein the DC power transmission or distribution system network includes at least one of a DC microgrid feeder and high voltage DC (HVDC) lines.

14. A fault protection system for protecting a DC feeder electrical power network, the system comprising: one or more circuit breaker arrangements which on activation isolate electrical faults within the network; andone or more processors programmed for: sampling voltage and current of the network at a relatively high sampling rate;determining the occurrence of and location of a fault in the network based on the sampled voltage and current; andactivating one or more of the circuit breaker arrangements in response to determining the occurrence of a fault.

15. A fault protection system as in claim 14, wherein said one or more processors are further programmed for calculating a current derivative.

16. A fault protection system as in claim 15, wherein said relatively high sampling rate is in a range between 100 KHz and 10 MHz.

17. A fault protection system as in claim 15, wherein said one or more processors are further programmed for conducting three consecutive samplings of the voltage and current at up to about 1 MHz sampling rate.

18. A fault protection system as in claim 17, wherein one or more processors are further programmed for solving the equations:

19. A fault protection system as in claim 18, wherein said one or more processors are further programmed for solving for fault location x by solving the equation:

20. A fault protection system as in claim 14, wherein: the DC feeder electrical power network comprises at least one of a DC microgrid feeder and high voltage DC (HVDC) lines; andthe circuit breaker arrangements are placed only on the positive pole of the DC feeder electrical power network.