1. Field of the Invention
The application generally relates to a touch panel, and more particularly, to a capacitive touch panel.
2. Description of Related Art
In recent years, along with the rapid advancement and wide application of information technologies, wireless mobile communications, and information appliances, the conventional input devices (for example, keyboards and mouses) of many information products have been replaced by touch panels in order to offer convenience, small volume, light weight, and intuitional experiences to the users.
Touch panels can be categorized into resistive touch panels, capacitive touch panels, optical touch panels, acoustic wave touch panels, and electromagnetic touch panels according to the adopted touch-sensing techniques. Compared to other types of touch panels, capacitive touch panel offers quick response, high reliability, and high definition therefore is broadly applied to various handheld electronic devices.
In a capacitive touch panel, a plurality of driving lines and a plurality of sensing lines are intersected to form a sensing array, so that a surface sensing effect can be achieved. When a user touches the touch panel with a finger, the touch panel determines the position touched by the finger according to capacitance variation on the sensing array. However, in an existing capacitive touch panel, obvious parasitic capacitances are produced at where the driving lines are intersected with the sensing lines. Thus, a touch position may not be correctly determined. As a result, the sensing sensitivity is reduced.
Conventionally, the distances between the intersected driving lines and sensing lines are usually increased (i.e., the thickness of an insulation material between the driving lines and the sensing lines is increased) in order to reduce the impact of the parasitic capacitances. However, such a technique increases the fabrication cost and the thickness of the touch panel and reduces the transmittance of the touch panel.
Accordingly, the application is directed to a touch panel, in which the parasitic capacitance between driving lines and sensing lines is reduced and accordingly an optimal sensing sensitivity is achieved.
The application is directed to a touch panel, in which due to the decrease of parasitic capacitance, the amount of insulation material applied between driving lines and sensing lines is reduced and accordingly the fabrication cost is reduced.
The application is directed to a touch panel, in which due to the decrease of parasitic capacitance, the thickness of the touch panel is reduced and an optimal transmittance is achieved.
The application provides a touch panel including a first substrate, a plurality of driving lines, and a plurality of sensing lines. The driving lines are arranged on a first surface of the first substrate in parallel and are respectively extended along a first direction. Each of the driving lines includes a plurality of first pads and a plurality of first interconnecting portions. Any adjacent two first pads are connected with each other through a first interconnecting portion, and the width of each first interconnecting portion is smaller than the width of each first pad. The sensing lines are arranged on the first substrate in parallel and are respectively extended along a second direction. The second direction intersects the first direction. The sensing lines are electrically insulated from the driving lines. The vertical projection of any sensing line on the first surface intersects a first interconnecting portion of each driving line to form an overlapped area, and the length of the overlapped area in the second direction is smaller than or equal to the length of the overlapped area in the first direction.
These and other exemplary embodiments, features, aspects, and advantages of the application will be described and become more apparent from the detailed description of exemplary embodiments when read in conjunction with accompanying drawings.
The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.
Reference will now be made in detail to the present preferred embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
As shown in
In the present embodiment, the parasitic capacitance produced in the overlapped area R1 is reduced by reducing the size of the overlapped area R1.
First, in the present embodiment, the width L1 of each first interconnecting portion 114 is reduced to make it smaller than the width L2 of each first pad 112. Herein the width L1 of each first interconnecting portion 114 is considered the length of the first interconnecting portion 114 in the direction X, and the width L2 of each first pad 112 is considered the length of the first pad 112 in the direction X. Accordingly, when the width L1 of a first interconnecting portion 114 is reduced, the size of the overlapped area R1 formed by a sensing line 120 and the first interconnecting portion 114 is also reduced, so that the parasitic capacitance produced at where a driving line 110 intersects the sensing line 120 can be reduced.
Additionally, the relationship between the width L1 of the first interconnecting portion 114 and the width L3 of the sensing line 120 within the overlapped area R1 is further considered in the present embodiment. The width L1 of the first interconnecting portion 114 is smaller than or equal to the width L3 of the sensing line 120. Herein the width L3 of the sensing line 120 is the length of the sensing line 120 in the direction Y. In other words, the overlapped area R1 formed by the sensing line 120 and the first interconnecting portion 114 on the first surface 102a has a length L3 along the direction Y and a length L1 along the direction X, and L1≦L3.
In the present embodiment, any adjacent two first pads 112 may be connected with each other through one, two, or more first interconnecting portions 114.
Additionally, referring to
As described above, in the present embodiment, by reducing the size of the overlapped area R1 between each driving line 110 and each sensing line 120, the parasitic capacitance produced between the driving line 110 and the sensing line 120 is reduced, so that an optimal sensing sensitivity is achieved.
Electrical characteristics (for example, the parasitic capacitance between the driving lines and the sensing lines and the resistance of the driving lines) of the touch panel 100 may also be adjusted by changing the shape of the overlapped areas R1 between the driving lines 110 and the sensing lines 120.
The design principle described above can be applied to different types of capacitive touch panels. Below, several possible cross-sectional structures of the touch panel 100 will be described with reference to
In the present embodiment, the parasitic capacitance between the driving lines 110 and the sensing lines 120 is reduced by reducing the size of the overlapped areas R1 between the driving lines 110 and the sensing lines 120. The distance between the driving lines 110 and the sensing lines 120 (i.e., the thickness of the second substrate 104) can be appropriately reduced without affecting the performance of the touch chip. Thus, the amount of material for fabricating the second substrate 104, and accordingly the fabrication cost of the touch panel 100, is reduced. Besides, the overall thickness of the touch panel 100 is reduced, and an optimal transmittance is achieved.
Similarly, in the present embodiment, the parasitic capacitance between the driving lines 110 and the sensing lines 120 is reduced by reducing the size of the overlapped areas R1 between the driving lines 110 and the sensing lines 120. The distance between the driving lines 110 and the sensing lines 120 (i.e., the thickness of the first substrate 102) can be appropriately reduced without affecting the performance of the touch chip. Thus, the amount of material for fabricating the first substrate 102, and accordingly the fabrication cost of the touch panel 100, is reduced. Besides, the overall thickness of the touch panel 100 is reduced, and an optimal transmittance is achieved.
Similarly, in the present embodiment, the parasitic capacitance between the driving lines 110 and the sensing lines 120 is reduced by reducing the size of the overlapped areas R1 between the driving lines 110 and the sensing lines 120. The distance between the driving lines 110 and the sensing lines 120 can be shortened without affecting the performance of the touch chip. Thus, the overall thickness of the touch panel 100 is reduced, and an optimal transmittance is achieved.
Even though several possible structures of the touch panel provided by the application have been described above, the application is not limited thereto. For example, the shapes and layouts of the driving lines and the sensing lines are not limited to those described in foregoing embodiments.
As shown in
In the present embodiment, the first pads 212, the first interconnecting portions 214, and the second pads 222 are coplanar, and each second interconnecting portion 224 is disposed above the corresponding first interconnecting portion 214 to form an overlapped area R2 (as shown in
In the present embodiment, the parasitic capacitance produced in the overlapped areas R2 can be reduced by reducing the size of the overlapped areas R2. The width L4 of each first interconnecting portion 214 is smaller than the width L5 of each first pad 212, and the width L6 of each second interconnecting portion 224 is smaller than the width L7 of each second pad 222. Since both the width L4 of each first interconnecting portion 214 and the width L6 of each second interconnecting portion 224 are reduced, the size of the overlapped area R2 formed by the first interconnecting portion 214 and the second interconnecting portion 224 is also reduced. Accordingly, the parasitic capacitance produced at where the first interconnecting portion 214 intersects the second interconnecting portion 224 is also reduced.
Additionally, in the present embodiment, the relationship between the width L4 of the first interconnecting portion 214 and the width L6 of the second interconnecting portion 224 within the overlapped area R2 is further taken into consideration. Herein the width L4 of the first interconnecting portion 214 is smaller than or equal to the width L6 of the second interconnecting portion 224. In other words, the overlapped area R2 formed by the first interconnecting portion 214 and the second interconnecting portion 224 respectively has a length L6 along the direction Y and a length L4 along the direction X, and L4 <L6.
Additionally, referring to
As described above, in the present embodiment, by reducing the size of the overlapped area R2 between each driving line 210 and each sensing line 220, the parasitic capacitance between the driving line 210 and the sensing line 220 is reduced, so that an optimal sensing sensitivity is achieved.
Similarly, regarding the cross-sectional structure in the present embodiment, the parasitic capacitance produced in the overlapped areas R2 is reduced by reducing the distance between the driving lines 210 and the sensing lines 220. Besides, the thickness of the touch panel 200 is reduced and an optimal transmittance is achieved.
To be specific, when the intersection area between a driving line 210 and a sensing line 220 is too large, a user can easily see the intersection, and accordingly the transmittance uniformity of the touch panel 200 is affected. Thus, in the present embodiment, the shapes of the driving lines 210 and the sensing lines 220 at where they intersect each other are specially designed to improve the transmittance uniformity of the touch panel 200. As shown in
Additionally, as shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the application without departing from the scope or spirit of the application. In view of the foregoing, it is intended that the application cover modifications and variations of this application provided they fall within the scope of the following claims and their equivalents.
This application claims the priority benefits of U.S. provisional application Ser. No. 61/567,057, filed on Dec. 5, 2011. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification
Number | Date | Country | |
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61567057 | Dec 2011 | US |