Data Storage Devices (DSDs) are often used to record data onto or to reproduce data from a storage media. One type of storage media includes a rotating magnetic disk. A magnetic head of the DSD can magnetically read and write data in tracks on a surface of the disk.
The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed.
In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.
Shingled Magnetic Recording (SMR) has recently been introduced as a way of increasing the amount of data that can be stored in a given area on the disk by increasing the number of Tracks Per Inch (TPI) with narrower tracks. SMR increases TPI by using a relatively wide write element of the head with a stronger magnetic field to overlap tracks like roof shingles. The non-overlapping portion then serves as a narrow track that can be read by a read element of the head.
Although a higher number of TPI is ordinarily possible with SMR, the stronger magnetic field of the write element and the closer proximity of tracks can worsen Adjacent Track Interference (ATI) which occurs when data already stored on the disk becomes corrupted due to the magnetic field from writing new data in adjacent tracks. During a product development phase or as part of a manufacturing process, certain track measurement tests may be performed to determine how much encroachment a track on the disk can sustain from an adjacent track without compromising the integrity of the data stored in the track. However, as the proximity of tracks increases, the results of such track placement tests become less reliable. In addition, the closer proximity of tracks makes it more difficult to determine whether the head and disk meet particular specifications.
In the example of
In view of the foregoing, the disclosed processes for track measurement ordinarily improve the accuracy and repeatability of track measurement tests by accounting for variations in track placement caused by Track Mis-Registration (TMR), which is discussed in more detail below with reference to
The disclosed track measurement processes may be performed by DSD 106 or by host device 101, or by a combination of both host device 101 and DSD 106. In addition, those of ordinary skill in the art will appreciate that computer system 100 and DSD 106 can include more or less than those elements shown in
As shown in
Host interface 126 is configured to interface DSD 106 with host device 101 and may interface according to a standard such as, for example, PCI express (PCIe), Serial Advanced Technology Attachment (SATA), or Serial Attached SCSI (SAS). Although
DSD 106 also optionally includes solid state memory 128 for storing data, which stores data that can be retained across power cycles (i.e., after turning DSD 106 off and on). In this regard, DSD 106 can be considered a “hybrid drive” in that it includes multiple types of storage media. However, as will be appreciated by those of ordinary skill in the art, other embodiments may not include solid state memory 128, and may instead only include rotating magnetic disks such as disk 200 as a non-volatile memory.
While the description herein refers to solid state memory generally, it is understood that solid state memory may comprise one or more of various types of memory devices such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., Single-Level Cell (SLC) memory, Multi-Level Cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete Non-Volatile Memory (NVM) chips, or any combination thereof.
In the example of
As understood by those of ordinary skill in the art, disk 200 may form part of a disk pack with additional disks radially aligned below disk 200. In addition, head 136 may form part of a head stack assembly including additional heads with each head arranged to read data from and write data to a corresponding surface of a disk in a disk pack.
Disk 200 includes a number of radially spaced, concentric tracks 202 with each track 202 divided into a plurality of sectors that are spaced circumferentially along track 202. The sectors may be used to store user data or other information.
Disk 200 also includes a plurality of angularly spaced servo wedges 2040-204N, each of which may include embedded servo information that can be read by head 136 to determine a position of head 136 over disk 200. For example, each servo wedge 2040-204N may include a pattern of alternating magnetic transitions (servo burst), which may be read by head 136 and used by servo controller 122 to estimate the position of head 136 relative to disk 200.
Volatile memory 134 can include, for example, a Dynamic Random Access Memory (DRAM) which can be used by DSD 106 to temporarily store data. Data stored in volatile memory 134 can include data read from NVM media (e.g., disk 200 or solid state memory 128) and data to be written to NVM media. As shown in
In operation, host interface 126 receives commands from host device 101 via host interface 126 for reading data from and writing data to non-volatile memory such as solid-state memory 128 or disk 200. In response to a write command from host device 101, controller 120 may buffer the data to be written for the write command in volatile memory 134.
For data to be written to disk 200, read/write channel 124 encodes the buffered data into write signal 32 which is provided to head 136 for magnetically writing data in sectors on disk 200.
In response to a read command for data stored on disk 200, controller 120 positions head 136 via servo controller 122 to magnetically read the data stored in sectors on disk 200. Head 136 sends the read data as read signal 32 to read/write channel 124 for decoding and the data is buffered in volatile memory 134 for transferring to host device 101 via host interface 126.
The write TMR can contribute to errors when performing track measurements where the offset between a test track and an adjacent track are gradually decreased, such as in a squeeze to death test or a zero OTRC test. In such tests, data is read from a test track with the adjacent track at various offset distances from the test track. In addition to the variance caused by the write TMR discussed above, a read TMR caused by similar factors when reading data from the test track can exacerbate the reliability of conventional track measurement tests.
In a conventional squeeze to death test, the offset between the adjacent track and the test track is gradually decreased until an error has been confirmed for one of the sectors in the track. The error may be detected using an Error Correcting Code (ECC) of the sector or by other methods known in the art. This conventional way of performing a squeeze to death test generally measures the amount of encroachment or squeeze a track can handle without errors. This test will indicate an acceptable encroachment distance based on the sector in the test track that is the most prone to an error from the interference of the adjacent track (i.e., the “dead sector”). The repeatability of such a test is typically poor since the dead sector may change from one run of the test to the next. Moreover, the foregoing test does not account for position error caused by write TMR and read TMR which have a greater effect on results when tracks are to be located in close proximity to or partially overlapping each other (i.e., an SMR application).
In a conventional OTRC test, the amount of encroachment or squeeze from an adjacent track that a test track can handle is determined by gradually decreasing the offset distance between the adjacent track and the test track while reading data from the test track from an OTRC position outside the test track. The amount of encroachment or squeeze that the test track can handle is set at the point where no data can be read from the test track from the OTRC position. In other words, the distance the adjacent track is offset from the test track is gradually decreased until all of the sectors of the test track have a zero OTRC where no data can be read from the sectors from the OTRC position.
As with the conventional squeeze to death test discussed above, the conventional OTRC test does not account for TMR when reading and writing data. As a result, the conventional OTRC test often provides inaccurate results because not all of the sectors in the test track reach a zero OTRC at the same time due to TMR. The results of a conventional OTRC test are therefore usually artificially high since read errors will be encountered for many of the sectors before the adjacent track is positioned such that all of the sectors have a zero OTRC.
With reference to
In some implementations, an offset value may be used to represent the change in offset between the test track and the adjacent track as, for example, a percentage of a track pitch change between the test track and the adjacent track or an amount of overlap of the adjacent track onto the test track.
In the example of
As shown by the differences in distances A and B in
Test track 216 and adjacent track 218 are initially located with adjacent track 218 partially overlapping test track 216. Such an initial overlap may be used to tune a track format in an SMR implementation. In this example, an amount of overlap can be gradually increased to determine an amount of track overlap for SMR tracks to better utilize an area of the disk surface.
As indicated in
An OTRC value for each sector can be determined based on whether the sector meets a criterion for correctly reading data from the sector at the different OTRC positions. Such a criterion can include whether head 136 can correctly read data from the sector in a certain number of read attempts or revolutions of disk 200. In one implementation, a sector meets the criterion if data can be correctly read from the sector when head 136 is at the OTRC position three out of five times. Other criterion for correctly reading data from the sector may be used in other embodiments. The correctness of the data read from the sector can be determined by evaluating an ECC of the sector or by other methods known in the art for checking data.
After determining whether each of the plurality of sectors passes or fails the criterion at a first OTRC position, such as OTRC position 300, head 136 is moved to a second OTRC position such as OTRC position 302 and the processes of determining whether each of the plurality of sectors in test track 216 meet the criterion repeats for the new location of adjacent track 218. Head 136 is then moved to a third OTRC position such as OTRC position 304 where it is determined whether data can be correctly read from each sector in test track 216. In general, the farther the OTRC position is from test track 216, the more likely that read errors will occur when attempting to read test track 216 from the OTRC position.
As noted above, the order of the OTRC positions can vary such that head 136 may move from OTRC position 304 to OTRC position 300 in other examples. In addition, other embodiments may include more or less OTRC positions than those shown in
An OTRC value is determined for each sector in test track 216 by evaluating whether the sector met the criterion for correctly reading data at the different OTRC positions. In one example implementation, the OTRC value can include a ratio of the number of successful reads to the total number of read attempts from the different OTRC distances.
As the offset distance of adjacent track 218 is decreased to that of
In one embodiment, adjacent track 218 is repeatedly rewritten at decreasing offset distances from test track 216 until the average OTRC value for the sectors in the test track are not greater than or equal to a predetermined multiple of the standard deviation of the OTRC values. This track positioning is shown in
In block 502, controller 120 controls head 136 via servo controller 122 to write test data in a plurality of sectors in a test track (e.g., test track 216 in
In block 506, controller 120 controls head 136 to read data from the plurality of sectors in the test track from an OTRC position outside of the test track. An OTRC value is determined for each of the plurality of sectors in block 508 by varying the OTRC position and determining whether the sector meets a criterion for correctly reading data from the sector. The OTRC positions may include a series of steps or distances from the test track or its centerline. As noted above, the criterion for correctly reading data from the test track can include determining whether data can be read from a particular sector without errors for a predetermined number of read attempts. The OTRC value can represent the OTRC for the particular sector in the test track. In one implementation, the OTRC value can include a ratio of the number of successful reads to the total number of read attempts at the different OTRC positions. Other known methods of calculating an OTRC value can be used in other implementations.
In block 510, controller 120 calculates an average OTRC value for the plurality of sectors in the test track. In the example track placement of
In block 512, controller 120 calculates a standard deviation of the OTRC values for the plurality of sectors in the test track. Controller 120 in block 514 determines whether the average OTRC value is greater than or equal to a predetermined multiple of the standard deviation calculated in block 512. The predetermined multiple can be based on design criteria such as, for example, to adjust the sensitivity to variations in track boundaries from TMR. In some implementations, the predetermined multiple can be 1 so that the comparison in block 514 determines whether the average OTRC value is greater than or equal to the standard deviation of the OTRC values.
If it is determined in block 514 that the average OTRC value is greater than or equal to the predetermined multiple of the standard deviation, controller 120 in block 516 controls head 136 via servo controller 122 to rewrite the adjacent track at a decreased offset distance from the test track. The process of
On the other hand, if it is determined in block 514 that the average OTRC value is not greater than or equal to the predetermined multiple of the standard deviation, controller 120 in block 518 sets a system squeeze setting based on the current offset distance for the adjacent track. In some embodiments, controller 120 may set the system squeeze setting using a curve fit or linear interpolation using the current offset distance. In block 520, the system squeeze setting can be optionally used, as indicated by the dashed box, to tune a track format for disk 200 or to determine whether components of DSD 106 fail a quality assurance test.
The head-media squeeze setting can be used to determine whether head 136 and disk 200 meet particular specifications without most of the influence of TMR caused by the servo system. In addition, the following process of
In block 602, controller 120 correlates different average OTRC values calculated in block 510 of
An example of such a correlation is depicted in the graph of
The predetermined multiple of the standard deviations of the OTRC values are also plotted as curve 420 in
Returning to the process of
In other embodiments, controller 120 may estimate where curve 418 would reach an average OTRC value of zero using a linear fit of a portion of the correlation between the average OTRC values and their respective offset distances or offset values. For example, controller 120 may use a linear fit of the last three average OTRC values including additional OTRC value 428 to estimate the offset distance or offset value for an average OTRC value of zero.
The point at which curve 422 reaches the x-axis with an average OTRC value of zero at offset value 426 represents an offset value that can be achieved without significant influence of TMR from the servo system. By reducing the influence of servo TMR, it is ordinarily possible to more accurately determine specifications for head 136 and disk 200.
In block 606 of
Tests conducted using the foregoing track measurement processes have shown a significant reduction in study variation when comparing the above-described track measurement processes to a conventional squeeze to death test.
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.
To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.
The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
This application claims the benefit of U.S. Provisional Application No. 61/980,472, filed on Apr. 16, 2014, which is hereby incorporated by reference in its entirety.
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| Number | Date | Country | |
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| 61980472 | Apr 2014 | US |