Trans-admittance trans-impedance logic for integrated circuits

Abstract

A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage input to the trans-admittance stage. The circuit output is taken from the output of the trans-admittance stage. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch to form a register.

Description

FIELD OF THE INVENTION

[0002] The present invention relates to an improved integrated circuit, and in particular, to an integrated circuit that enhances the performance of logic gates when operating at the limits of the transistor bandwidth.

DESCRIPTION OF RELATED ART

[0003] FIG. 1 is a conventional logic gate 100, such as an emitter-coupled logic (ECL) or current-mode-logic (CML) integrated circuit, that may be cascaded in a chain to form a register. This conventional logic block receives differential input voltage signals Vin, Vinb on terminals 12,13 respectively, where “b” represents “bar,” i.e., the inverse or complementary signal. The circuit produces differential output voltage signals Vout, Voutb on terminals 14, 15, respectively. Each logic gate includes a current switching stage or clocked trans-admittance stage (TAS) 110 comprising transistors T1, T2, T3, T4, T5, T6; a passive load resistance 120 comprising resistors R1, R2; and two emitter follower transisters T7, T8. These emitter follower transistors buffer the wire/fan-out capacitance driven by the logic gate and provide level-shifting.

[0004] The conventional logic gate of FIG. 1 is disadvantageous in that its use of a passive load 120 does not produce enough gain at the limit of the transistor bandwidth, e.g., gain greater than one, so that when a series of latches are driven, e.g., as part of a shift register, the signal will properly propagate.

[0005] Further, if the latch circuit of FIG. 1 is connected to other similar circuits to form a register, voltage interfaces occur. This effects the frequency response in view of the stray and loading capacitance, thus reducing the speed to the register.

[0006] At multi-GHz frequencies the capacitance of the wire fan out creates significant transit delay. To reduce or eliminate impedance mismatch, interconnects are implemented on the collectors of the transistors T3, T4, T5, T6 to reduce the capacitance and increase the speed. The resistance and the capacitance from the interconnect and loading stages on the collector nodes of the transistors reduces the peak clock frequency.

[0007] It is therefore desirable to develop a logic gate that is better suited for signal routing and less sensitive to capacitance from wiring while providing more gain at a higher bandwidth.

SUMMARY OF THE INVENTION

[0008] In one aspect, the present invention is directed to a logic circuit that solves the aforementioned problems through the use of a clocked trans-admittance stage circuit for receiving a voltage input and producing a current output and an active load, in the form of a trans-impedance stage, connected to receive the current output for said trans-admittance circuit and produce a voltage output.

[0009] In an illustrative embodiment, the trans-admittance stage circuit includes first and second transistors, a current source connected to the emitter of each of the first and second transistors, third and fourth transistors with the emitter of each of the third and fourth transistors being connected to the collector of said first transistor; and fifth and sixth transistors with the emitter of each being connected to the collector of the second transistor.

[0010] The trans-impedance stage circuit includes seventh and eighth transistors with their emitters and collectors connected together. The collector of fifth transistor of the trans-admittance stage is connected to the base of the seventh transistor of the trans-impedance stage and the collector of the sixth transistor of the trans-admittance stage is connected to the base of the eighth transistor of the trans-impedance stage. The gate output comes from the collectors of the fifth and sixth transistors, and the input being to the bases of the seventh and eighth transistors.

[0011] Compared to prior logic gates, the TAS-TIS pair of the present invention (1) uses current signals between gates, which are less effected by interconnect and loading capacitance, (2) allows for a balancing of the line impedance with the TIS gate input impedance to minimize reflections and absorb the line capacitance; (3) and provides more common-mode rejection between successive gates of a cascaded chain; (4) allows for a better circuit layout; and (5) has better noise or spurious signal rejection.

[0012] The invention is also directed to a cascaded latch chain including a clocked trans-admittance stage latch which receives an input current and produces a voltage output.

[0013] In a further embodiment, the latch chain may also include a trans-impedance circuit and one or more latch pairs, with each pair having two independent trans-admittance and trans-impedance stages.

[0014] Yet another aspect of the invention relates to a latch pair including two independent combined trans-admittance and trans-impedance stages, with each latch pair clocked to opposite phases of a clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The foregoing and other features of the present invention will be more readily apparent from the following detailed description and drawings of illustrative embodiments of the invention wherein like reference numbers refer to similar elements throughout the several views and in which:

[0016] FIG. 1 is a prior art logic gate circuit;

[0017] FIG. 2 a is an exemplary embodiment of a TAS latch portion of the prior art logic gate of FIG. 1;

[0018] FIG. 2 b is an exemplary embodiment of a resistive load (RL)-TAS latch rearranged to show the TAS separated from the RL;

[0019] FIG. 2 c is a block diagram, using logic gate symbols, of an exemplary cascaded chain comprising a TAS and two RL-TAS latches;

[0020] FIG. 3 a is an exemplary single stage TAS-TIS latch according to the present invention;

[0021] FIG. 3 b is an exemplary Dual TAS-TIS latch or latch pair with two independent TAS-TIS stages according to the present invention;

[0022] FIG. 3 c is a logic gate symbol for the TAS-TIS latch pair of FIG. 3b;

[0023] FIG. 4 a is a portion of the Dual clocked TAS of FIG. 3b;

[0024] FIG. 4 b is a logic gate symbol for the Dual clocked TAS of FIG. 4a; and

[0025] FIGS. 5 a -5c are exemplary functional blocks with logic gates in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026] To increase the operating speed and size of registers implemented with logic gates, the passive load resistance 120 of a conventional trans-admittance stage (“TAS”) logic circuit as shown in FIG. 1, is replaced with an active load resistance, such as a trans-impedance stage (“TIS”) amplifier. The input to the TAS-TIS pair logic gate is a current signal applied to the TIS and the output is a current signal from the TAS. An active load resistance provides more gain at a higher bandwidth, so that a larger shift register can be constructed with the new logic gates without the signal degrading before the end of the register. The TIS further has a voltage output which is applied to the input of the TAS, which in turn produces a current output that is applied to the next stage. This arrangement makes the interface signals between successive gates in a cascaded series of gates, e.g. a shift register, into current signals. Current signals are much less susceptible to capacitances, both transistor capacitance and wiring capacitance. This keeps the speed of signal transition from being reduced by these capacitances. Basically the circuit is rearranged as a conventional trans-admittance stage (TAS) with a trans-impedance stage (TIS) load.

[0027] The line impedance and the TIS input impedance are chosen to minimize reflections and absorb the line capacitance. In addition, this arrangement provides more common-mode rejection between successor gates and has better noise or spurious signal rejection.

[0028] Further, the new gate is laid out to have the TIS as the input and the TAS as the output. The current from the switched TAS output of one gate is received by the TIS input stage of the next gate in a cascaded logic chain to form the register. The two latches are conveniently bunched together in one building block so that the power and chip areas are efficiently used. This permits a better circuit layout.

[0029] According to one feature of the invention, a digital circuit comprising several conventional digital gates as shown in FIG. 1, is modified so the gates are divided into blocks and regrouped to provide current rather than voltage interfaces at the inputs and outputs. Current interfaces are better suited for signal routing since the capacitance on current signal lines has only a minor impact on circuit speed and does not degrade circuit stability. In particular, the digital circuit is divided into a latch chain comprising a TAS latch connected in series to one or more resistive load (“RL”)-TAS latches.

[0030] FIG. 2 a is a circuit diagram of the TAS latch portion of FIG. 1. The TAS latch, which is formed by transistors T1, T2, T3, T4, receives clocked signals (e.g., clock (clk) and the complementary signal clock bar (clkb)) on terminals 110, 11 and a differential input voltage Vin, Vinb on terminals 12,13. The TAS latch produces a differential output current Iout, Ioutb on terminals 16,17.

[0031] The circuit diagram for the RL-TAS latch, as shown in FIG. 2b, comprises a passive resistance load block RL comprised of resistors R1, R2 and a TAS block formed by transistors T1, T2, T3, T4, T5, T5′, T6, T6′. The transistors T1, T2 receive the clock signals on their bases and alternately enable transistor pairs T3, T4 and T5, T6. T3 and T4 could be connected (or be part of) to another register that is active, when the clock is high. There could be another set of transistors connected to transistors T3 and T4 like transistors T5′, T6, T7, T8, and resistors R1, R2 connected to transistor T5, T6. Further, the bases of transistors T3, T4 are connected together and attached between resistors R3,R4, which receive bias voltages Vcc and Vee. Thus, in the embodiment shown the transistor pair T3,T4 does not process the signal.

[0032] The differential input signals Iin, Iinb to the circuit of FIG. 2b could be the current outputs at terminals 16,17 of the TAS of FIG. 2a. In effect, lout at terminal 16 would be applied to input terminal 21 of FIG. 2b and Ioutb at terminal 17 would be applied to input terminal 22. Thus, it can be seen that the input is applied to the RL portion of the circuit of FIG. 2b. Also included in the RL-TAS latch are emitter follower transistors T7, T8 which provide voltage outputs from the RL portion which drive the bases of transistors T5,T6. The collectors of T5,T6 provide a differential current drive signal lout, Ioutb for the next gate circuit, e.g. in a register.

[0033] A chain may be formed by cascading a series of RL-TAS latches clocked on opposite phases of the system clock. FIG. 2c is an exemplary block diagram of a cascaded latch chain in which the first TAS 24 in the chain has the form shown in FIG. 2a and receives an input voltage and its complement Vin, Vinb and produces a current output and its complement lout, Ioutb. This current output is applied to the input of the RL-TAS 26 having the form shown in FIG. 2b. By way of example, the chain in FIG. 2c has two RL-TAS latches 26,28; however, any number of one or more RL-TAS latches may be cascaded together, as desired. Each RL-TAS latch receives a current input signal and its complement Iin1, Iin1b and produces a differential current output Iout1, Iout1b.

[0034] In accordance with one embodiment of the present invention, the load resistors R1,R2 in the TAS latch shown in FIG. 1, are replaced with an active resistance load, for example, a trans-impedance amplifier stage (TIS) as shown in FIG. 3a to form a TAS-TS latch. In FIG. 3a the TIS is an amplifier including transistors T7′, T8′, T9, T10 and resistors R5, R6, R7, R8. The TIS load converts an input current from T3,T4 of the TAS switch (or a prior gate connected to terminals 21,22) to an output current at the collectors of T5,T6. Transistor T9, produces an amplified signal that is buffered by emitter follower transistor T7, whose output drives the base of transistor T5. Likewise, transistor T10 produces an amplified signal that is buffered by emitter follower transistor T8, whose output drives the base of transistor T6.

[0035] Logic gates configured in accordance with the present invention are less sensitive to transistor capacitance and/or capacitance caused by wiring connected to the collectors of the transistors T3, T4, T5, T6. In addition, the topology shown in FIG. 3a provides a convenient node, terminals 21,22 in the circuit that can be used for input/output connections between logic gates. Specifically, logic gates in accordance with the present embodiment are arranged to have a TIS input stage and a TAS output stage. Thus, the current from the switched TAS output is received by the TIS input stage of the next logic block in the cascaded logic chain.

[0036] A gain greater than one is required in the TAS-TIS combination in order to propagate a digital signal along a chain of logic gates. The TAS-TIS logic gate in accordance with the present invention provides more differential gain than conventional logic gates when operating at maximum frequency. In addition, the bandwidth or corner frequency for gain roll-off is extended by the TAS-TIS logic gate relative to that achieved using conventional logic gates. The TAS-TIS logic gate also provides more common-mode rejection between gates than with conventional logic gates. Improved noise or spurious signal rejection may also be obtained using the TAS-TIS logic gate construction. This characteristic is particularly advantageous at relatively high frequency where noise or spurious signals may be coupled into the circuit.

[0037] For efficient use of power and area, two independent TAS-TIS stages may be grouped in the same block. FIG. 3b shows a latch pair comprising two independent TAS TIS stages, i.e., a Dual TAS-TIS latch, wherein the two stages are clocked on opposite phases of a clock signal clk (clock) and clkb (clock bar). FIG. 3c is a digital logic circuit symbol for the Dual or two stage TAS-TIS latch.

[0038] FIG. 4 a is a clocked Dual TAS in accordance with the invention which receives two differential input voltages Vin1, Vin1b, Vin2, Vin2b and produces two differential output currents Iout1, Iout1b, Iou2, Iout2b. Transmission lines TL 1, TL2, TL3, TL4 may be coupled between the outputs of the TAS circuit and the inputs of the TIS circuit. The nominal frequency range of oscillation of the overall circuit may be adjusted by selecting the length of the transmission lines TL1, TL2, TL3, TL4. A clock signal acts as a selector between Vin1, Vin2. In particular, when the clock signal (clk) is active, the input voltage Vin1, Vin1b is output as current Iout1, Iout1b, whereas when clock bar signal (clkb) is active, the input voltage Vin2, Vin2b is output as Iout2, Iout2b. The logic gate symbol of the two stage clocked TAS latch or Dual TAS is shown in FIG. 4b.

[0039] The modified logic gates in accordance with the present invention have a wide range of functional applications. By way of example, in FIG. 5a, a clocked Dual TAS latch 52 as shown in FIG. 4a is coupled with a TIS 305 as shown in FIG. 3a to form a two-in-one selector for voltages. The clocked Dual TAS selectively receives two input voltages Datal (Vin1,Vin1b) and Data2 (Vin2, Vin2b) and selectively produces output current Iout1, Iout1b or Iout2, Iout2b. The TIS 54 selectively receives as a current input Iin, Iinb outputs Iout1 or Iout2b from Dual TAS 52. The current Iinb received in TIS 54 is the output current Iout2 or Iout2b of the clocked Dual TAS 52. The output of TIS 54 produces a single voltage output Vout1, Voutb.

[0040] In another exemplary application of the logic gates in accordance with the present invention, FIG. 5b shows a two-to-one multiplexer constructed of a cascaded chain comprising clocked Dual TAS latch 52, two Dual TAS-TIS latch pairs 56,56′ (in the form shown in FIG. 3c) and a TIS 54. FIG. 5c shows the reverse processing of a one-to-two demultiplexer which includes Dual TAS latch 52, and a pair of Dual TAS-TIS latches 56,56′. Other functional applications of the logic circuits in accordance with the present invention are contemplated and within the intended scope of the invention.

[0041] The logic gate in accordance with the present invention provides more gain at higher bandwidth than conventional logic gates. Line impedance and TIS input impedance are selected to minimize reflections and adsorb the line capacitance, thereby increasing the peak clock frequency.

[0042] Thus, while there have been shown, described, and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions, substitutions, and changes in the form and details of the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit and scope of the invention. For example, it is expressly intended that all combinations of those elements and/or steps which perform substantially the same function, in substantially the same way, to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.

Claims

1. A latch comprising: a clocked trans-admittance stage circuit for receiving a voltage on an input and producing a current output; and an active load connected to receive a current on an input and produces a voltage output delivered to the input of the trans-admittance stage, the input of the active load being the input of the latch and the output of the trans-admittance stage being the output of the latch.

2. The latch in accordance with claim 1, wherein the active load is a trans-impedance stage circuit.

3. The latch in accordance with claim 1, wherein said trans-admittance stage circuit comprises: a first pair of transistors including a first transistor and a second transistor; a current source connected to the emitter of each of said first and second transistors; a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.

4. The latch in accordance with claim 2, wherein said trans-impedance stage circuit comprises: a fourth pair of transistors including seventh and eighth transistors with their emitters and collectors connected together, the collector of fifth transistor of the trans-admittance stage bing connected to the base of the seventh transistor of the trans-impedance stage and the collector of the sixth transistor of the trans-admittance stage being connected to the base of the eighth transistor of the trans-impedance stage, the latch output being taken from the collectors of the fifth and sixth transistors, and the input being to the bases of the seventh and eighth transistors.

5. The latch in accordance with claim 4, wherein said trans-impedance stage circuit further comprises a fifth pair of transistors including ninth and tenth transistors, wherein said ninth and tenth transistors are connected as emitter followers for the seventh and eighth transistors respectively.

6. The latch in accordance with claim 3, wherein the base of said first and second transmitters are clocked on opposite phases of a clock signal.

7. The latch in accordance with claim 6, wherein the base of said third transistor receives as an input a voltage signal and the base of said fourth transistor receives as an input an inverted voltage signal, said third transistor produces a current output signal based on the inverted voltage signal, and said fourth transistor produces an inverted current output signal based on the voltage signal.

8. The latch in accordance with claim 1, further comprising transmission lines coupled between said clocked trans-admittance circuit and said active load.

9. A cascaded latch chain comprising: a first stage with a clocked trans-admittance stage latch receiving an input voltage and producing an output current; and a second stage with a trans-impedance stage receiving the output current of the trans-admittance stage latch of said first stage.

10. The cascaded latch in accordance with claim 9, wherein said second stage is at least one trans-admittance stage—trans-impedance stage latch pair connected to receive the output current of said clocked trans-admittance stage latch of said first stage and producing an output current, said at least one latch pair including two independent combined trans-admittance and trans-impedance stages.

11. The cascaded latch chain in accordance with claim 10, comprising at least two latch pairs including a first latch pair and a last latch pair, each latch pair having two independent trans-admittance and trans-impedance stages, the two trans-admittance and trans-impedance stages of each latch pair being clocked on opposite phases of a clock signal.

12. The cascaded latch chain in accordance with claim 11, wherein said trans-admittance stage in each latch pair comprises: a first pair of transistors including a first transistor and a second transistor,; a current source connected to the emitter of each of said first and second transistors; a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.

13. The cascaded latch chain in accordance with claim 11, wherein the two trans-admittance and trans-impedance stages in said at least one latch pair are clocked on opposite phases of a clock signal.

14. The cascaded latch chain in accordance with claim 9, further comprising a trans-impedance stage latch connected to receive the output current of the last latch pair and produce an output voltage.

15. The cascaded latch chain in accordance with claim 10, further comprising a trans-impedance stage latch connected to receive the output current of the last latch pair and produce an output voltage.

16. A latch pair comprising: two independent combined trans-admittance and trans-impedance stages.

17. The latch pair in accordance with claim 16, wherein each trans-admittance stage comprises: a first pair of transistors including a first transistor and a second transistor; a current source connected to the emitter of each of said first and second transistors; a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.

18. The latch in accordance with claim 17, wherein said trans-admittance stage circuit comprises: a first pair of transistors including a first transistor and a second transistor; a current source connected to the emitter of each of said first and second transistors; a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.

19. The latch pair in accordance with claim 17, wherein the two trans-admittance and trans-impedance stages are clocked on opposite phases of a clock signal.