In order that the invention may be more fully understood, embodiments thereof will now be described, purely by way of example, with reference to the accompanying drawings, in which:
FIG. 1(
a) illustrates a conventional single-ended transconductor circuit;
FIG. 1(
b) is a schematic illustration of a single-ended transconductor;
FIG. 2 is a schematic illustration of a conventional balanced feedback transconductor circuit;
FIG. 3 illustrates a portion of a conventional gyrator channel filter;
FIG. 4(
a) illustrates a single-ended transconductor circuit according to the invention;
FIG. 4(
b) illustrates a balanced transconductor circuit according to the invention formed by two of the single-ended transconductor circuits of FIG. 4(a);
FIG. 5 is a schematic illustration of one example of a balanced feedback transconductor circuit according to the invention;
FIG. 6 is a schematic illustration of another example of a balanced feedback transconductor circuit according to the invention; and
FIG. 7 illustrates a portion of a gyrator channel filter according to the invention.
FIG. 4(
a) illustrates a single-ended transconductor circuit 50 according to the invention. In this example, a CMOS inverter 51 comprises a p-channel MOSFET 52 and an n-channel MOSFET 53. The p-channel and n-channel MOSFETs 52, 53 have equal transconductances, gm, and are arranged with their gate terminals, g, connected to an input terminal 54 and their drain terminals, d, connected to an output terminal 55. The source terminal of the p-channel MOSFET 52 is connected to a first power supply rail 56 and the source terminal of the n-channel MOSFET 53 is connected to a second power supply rail 57. A resistor 58 having a resistance R is arranged between the input and output terminals 54, 55.
In use, a voltage source is connected across the first and second power supply rails 56, 57, an input voltage Vin is applied at the input terminal 54 and an output current Iout is thus provided at the output terminal 55.
The single-ended transconductor of FIG. 4(a) can be considered to be the single-ended transconductor of FIG. 1(a) with a low pass feedback path formed by the combination of the resistor 58 and a transconductor input capacitance C′, illustrated by a dashed capacitor 59 in FIG. 4(a). The dc voltage at the input and output terminals 54, 55 is therefore substantially equal.
So long as the cut-off frequency of the low pass filter is low, there is negligible signal feedback and the signal transmission through the transconductor is substantially unimpaired. Accordingly, the resistance R of the resistor 58 is preferably set to be substantially greater than 1/G, where -G is the overall transconductance of the single-ended transconductor circuit 50.
Although a resistor 58 is used to provide dc feedback in the example of FIG. 4(a), this element can be replaced by an alternative resistive element such as a transistor. An arrangement using a transistor can have the advantage of having reduced substrate area in comparison to the illustrated arrangement using a resistor. In one example, the main current path of the transistor is connected between the input and output terminals 54, 55 and the input terminal is connected to a constant voltage source. For instance, in the case that a MOSFET is used, the source is connected to the input terminal 54, the drain is connected to the output terminal 55 and the gate is connected to the first power supply rail 56. The resistance of the main current path of the MOSFET would be predetermined by setting the dimensions of the MOSFET accordingly, for instance the width of the source, drain and gate regions of the MOSFET. Alternatively, the magnitude of the control signal applied to the gate of the MOSFET or other transistor used could be selectively set to give the transistor its appropriate resistance, R.
FIG. 4(
b) illustrates a balanced transconductor circuit 60 according to the invention formed by two single-ended transconductor circuits each similar to that illustrated in FIG. 4(a). A first inverter 61 comprises a first p-channel MOSFET 62 and a first n-channel MOSFET 63. The first p-channel and n-channel MOSFETs 62, 63 have equal transconductances, gm, and are arranged with their gate terminals, g, connected to a positive input terminal 64 and their drain terminals, d, connected to a negative output terminal 65. The source terminal of the p-channel MOSFET 62 is connected to a first power supply rail 66 and the source terminal of the n-channel MOSFET 63 is connected to a second power supply rail 67. A first resistor 68 having a resistance R is arranged between the positive input and negative output terminals 64, 65.
A second inverter 69 comprises a second p-channel MOSFET 70 and a second n-channel MOSFET 71. The second p-channel and n-channel MOSFETs 70, 71 have equal transconductances, gm, and are arranged with their gate terminals, g, connected to a negative input terminal 72 and their drain terminals, d, connected to a positive output terminal 73. The source terminal of the p-channel MOSFET 70 is connected to the first power supply rail 66 and the source terminal of the n-channel MOSFET 71 is connected to the second power supply rail 67. A second resistor 74 having a resistance R is arranged between the negative input and positive output terminals 72, 73.
In operation, a voltage source is connected across the first and second power supply rails 66, 67. The positive input terminal 64 receives a positive input voltage Vin(+) and the negative input terminal 72 receives a negative input voltage. The positive output terminal 73 provides a positive output current Iout(+) and the negative output terminal 65 provides a negative output current lout( ).
Each of the two single-ended transconductor circuits is therefore used to convert either a positive or a negative input voltage to a negative or positive output current respectively. The first and second resistors are not limited to having the same resistance, R, but could have different resistances. Either or both of the resistors may alternatively be replaced with a transistor such as a MOSFET in a similar manner to that described above with reference to FIG. 4(a). The resulting balanced transconductor circuit 60, as well as the individual single-ended transconductor 50, can have applications in circuits such as the input and output stages of gyrator channel filters, for instance those suitable for use in wireless transceivers that operate according to Bluetooth™ and/or ZigBee™ standards.
FIG. 5 is a schematic illustration of one example of a balanced transconductor circuit 80 according to the invention. A first conventional single-ended transconductor 81, for instance as illustrated in FIG. 1(a) and having a transconductance -G, is arranged with its input connected to a positive input voltage terminal 82 and its output connected to a negative output current terminal 83. A second conventional single-ended transconductor 84, for instance as illustrated in FIG. 1(a) and having a transconductance -G, is arranged with its input connected to a negative input voltage terminal 85 and its output connected to a positive output current terminal 86. A first resistive element 87 has a resistance R1 and is connected between the positive input voltage terminal 82 and the negative output current terminal 83. A second resistive element 88 has a resistance R1, in this example equal to the resistance of the first resistive element 87, and is connected between the negative input voltage terminal 85 and the positive output current terminal 86. A third resistive element 89 has a resistance R2 and is connected between the positive input voltage terminal 82 and the positive output current terminal 86. A fourth resistive element 90 has a resistance R2, in this is example equal to the resistance of the third resistive element 89, connected between the negative input voltage terminal 85 and the negative output current terminal 83. First, second, third and fourth resistive elements 87, 88, 89, 90 are resistors in this embodiment.
This circuit 80, for instance when included in circuits such as filter circuits, can have the advantage of blocking low-frequency differential input signals whilst at the same time having a relatively high cut-off frequency for common-mode signals, thus resulting in the circuit having a high common-mode rejection ratio. With a differential input voltage present and with, in one example, R1=R2, the feedforward and feedback via the resistive elements is cancelled.
FIG. 6 illustrates another example of a balanced transconductor circuit 100 according to the invention, similarly arranged to the circuit described with reference to FIG. 5, but in which the first, second, third and fourth resistive elements are n-type MOSFETs 101, 102, 103, 104. Each of the MOSFETs is arranged with its main current path between an output and an input of the balanced transconductor circuit 100 and is supplied with a control signal ‘c’ at a gate terminal such that it operates in a triode or linear region. The gates could be connected to a supply rail (not shown) of the circuit 100. This enables the MOSFETs 101, 102, 103, 104 to operate in a similar manner as variable resistors, their resistance being dependent on the dimensions of the MOSFET, for instance the dimensions of the source, drain and/or gate regions. The use of MOSFETs as resistive elements in this circuit 100 results in an arrangement having reduced substrate area when compared to a circuit such as that previously described 80 using resistors. The resistances R1 and R2 can be set to be equal, in order to cancel out feedback and feedforward signals, or may alternatively be set individually to allow greater control over the operational characteristics of the circuit 100, as will be described.
FIG. 7 illustrates an input stage 110 of a filter according to the invention comprising a balanced transconductor circuit 100 as previously described with reference to FIG. 6. In this example the filter is a gyrator channel filter for use in a wireless transceiver. The input stage comprises positive and negative input terminals 111, 112 connected to the inputs of first and second single-ended transconductors 113, 114 respectively. The input stage 110 has first and second output terminals 115, 116 for connecting to the next stage in the filter.
The input stage 110 has dc blocking capacitors 117, 118 each having capacitance C and arranged in series between the input terminals 111, 112 and the first and second single-ended transconductors 113, 114 respectively. An effective input capacitance C′, illustrated in FIG. 7 by dashed capacitors 119, 120, is present between each of the first and second single-ended transconductor 113, 114 inputs and a ground terminal 121 respectively. Resistive loads 122, 123 of value RL are present between each of the output terminals 115, 116 and the ground terminal 121 respectively.
For a filter input stage receiving differential-mode signals, such as that illustrated in FIG. 7, and in the case in which R1, the resistance of the first and second resistive elements, is not set equal in value to R2, the resistance of the third and fourth resistive elements, this produces a first-order high pass response with a cut-off frequency of wco given by,
where RF, the effective feedthrough resistance, is given by,
and an approximate high frequency gain, A, is given by A≈-GmRL.
For common-mode input signals, the effective feedthrough resistance becomes,
Accordingly, the value of R1 and R2 can be chosen such that low frequency differential signals are blocked thus avoiding the need for large blocking capacitors 117, 118, without impairing the channel filter response. Also, the cut-off frequency for common-mode signals can be much higher thus resulting in the circuit 110 having a high common-mode rejection ratio.
The example depicted in FIG. 7 is an input stage for a gyrator channel filter for a Bluetooth™ wireless transceiver. Component values for the circuit could be, for example, blocking capacitances, C, set to 10 pF, resistive loads, RL, equal to 12.5 kΩ and the transconductance, G, equal to 320 μS. Setting R1 to 1 MΩ and R2 to 1.1 MΩ results in an effective feedthrough resistance, RF, of 11 MΩ. The n-type MOSFET transistors used as the first and second resistive elements 101, 102, can, for example, have widths of 0.28 μm and lengths of 42 μm. The n-type MOSFET transistors used as the third and fourth resistive elements 103, 104 can, for example, have widths of 0.28 μm and lengths of 46 μm. Using the above formulae, the cut-off frequency is thus approximately 7.2 kHz and the high frequency gain, A, is approximately 4. For common-mode signals, the cut-off frequency is larger, at approximately 152 kHz.
When the above component values are used in a simulation of the circuit of FIG. 7, the dc blocking capacitors 117, 118 require substrate areas of about 1160 μm2 each in comparison to the 62 pF capacitors requiring an area of about 7200 μm2 that can be required with a conventional prior art circuit such as that depicted in FIG. 3. The input referred noise density is also reduced from that of the prior art design, this being 37 nV/√ Hz in the example of FIG. 7 compared to 45 nV/√ Hz in a conventional design. The actual power consumption is also reduced by 11%, which, when combined with the implied power saving resulting from the input referred noise reduction, results in total filter power savings of about 40%.
In an alternative example, the balanced transconductor circuit 100 of FIG. 6 can be used in the output stage of a filter such as a gyrator channel filter for use in a wireless transceiver that operates according to Bluetooth™ and/or ZigBee™ standards. In this case, the circuit would have the advantage of blocking low frequency common-mode signals that can arise from the gyrator filter as a result of random mismatches of its transistors.
From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of transconductor circuits and which may be used instead of or in addition to features already described herein.
Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.
Patent Application
20080094110
