1. Field
The present disclosure relates generally to processing, and more specifically to techniques for performing transform on data.
2. Background
Transforms are commonly used to convert data from one domain to another domain. For example, discrete cosine transform (DCT) is commonly used to transform data from spatial domain to frequency domain, and inverse discrete cosine transform (IDCT) is commonly used to transform data from frequency domain to spatial domain. DCT is widely used for image/video compression to spatially decorrelate blocks of picture elements (pixels) in images or video frames. The resulting transform coefficients are typically much less dependent on each other, which makes these coefficients more suitable for quantization and encoding. DCT also exhibits energy compaction property, which is the ability to map most of the energy of a block of pixels to only few (typically low order) transform coefficients. This energy compaction property can simplify the design of encoding algorithms.
Transforms such as DCT and IDCT may be used for various applications that may support different image and video coding standards. Hence, it is desirable to provide interfaces that can receive and provide data in formats suitable for these applications. Furthermore, since transforms may be performed on large quantity of data, it is desirable to perform transforms as efficiently as possible.
Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described herein. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients (or simply, transform coefficients). A full transform may also be referred to as a non-scaled transform, a complete transform, etc. A scaled transform is a transform that operates on or provides scaled transform coefficients, which are scaled versions of the full transform coefficients. The scaled transform may have lower computational complexity and may be used by applications that can accept scaled transform coefficients. The full transform may be used by applications that desire to exchange full transform coefficients. The full and scaled transforms may be for a two-dimensional (2D) IDCT, which may be implemented in a separable manner with one-dimensional (1D) IDCTs. The full and scaled transforms may also be for a 2D DCT, which may be implemented in a separable manner with 1D DCTs. The 1D IDCTs and 1D DCTs may be implemented in a computationally efficient manner, as described below.
Various aspects and features of the disclosure are described in further detail below.
The techniques described herein may be used for various types of transforms such as DCT, IDCT, discrete Fourier transform (DFT), inverse DFT (IDFT), modulated lapped transform (MLT), inverse MLT, modulated complex lapped transform (MCLT), inverse MCLT, etc. The techniques may also be used for various applications such as image, video, and audio processing, communication, computing, data networking, data storage, graphics, etc. In general, the techniques may be used for any application that uses a transform. For clarity, the techniques are described below for DCT and IDCT, which are commonly used in image and video processing.
An N-point 1D DCT and an N-point 1D IDCT of type II may be defined as follows:
x[n] is a 1D spatial domain function, and
X[k] is a 1D frequency domain function.
The 1D DCT in equation (1) operates on N input samples or spatial domain values x[0] through x[N−1] and generates N transform coefficients X[0] through X[N−1]. The 1D IDCT in equation (2) operates on N transform coefficients and generates N output samples. Type II DCT is one type of transform and is commonly believed to be one of the most efficient transforms among various energy compacting transforms often proposed for image/video compression.
The 1D DCT and 1D IDCT may be implemented in their original forms shown in equations (1) and (2), respectively. However, substantial reduction in computational complexity may be realized by finding factorizations that result in as few multiplications and additions as possible, as described below.
The 1D DCT in equation (1) may be expressed in matrix form, as follows:
x=Ty, Eq (3)
where y is an N×1 vector of input samples,
T is an N×N matrix of a full 1D DCT, and
x is an N×1 vector of transform coefficients.
y contains input samples x[0] through x[N−1], and x contains transform coefficients X[0] through X[N−1]. The elements of T may be obtained based on equation (1).
The 1D DCT may be factored into a product of matrices, as follows:
T=STS, Eq (4)
where S=diag (A0, . . . , AN-1) is a diagonal matrix of scale factors, and
T
S is an N×N matrix of a scaled 1D DCT.
Equations (3) and (4) indicate that a full 1D DCT may be performed on y by first performing a scaled 1D DCT on y and then scaling the results with S.
An advantage of decomposing a full transform into a scaled transform and a scaling operation, e.g., as shown in equation (4), is that by properly choosing the scale factors, the multiplicative complexity of the scaled transform may be reduced. For example, a well-known decomposition of Arai, Agui, and Nakajima (AAN) in “A Fast DCT-SQ Scheme for Images,” Transactions of the IEICE, November 1988, produces a scaled 8-point DCT that may be implemented with only five multiplications by irrational factors. In contrast, the best-known full 8-point DCT requires 11 such multiplications.
An N×N 2D DCT may be defined as follows:
T{circle around (×)}T=(STS){circle around (×)}(STS)=(S{circle around (×)}S)(TS{circle around (×)}TS), Eq (5)
where T{circle around (×)}T is a Kroneker product of T with itself and is a matrix of a full 2D DCT,
T
S{circle around (×)}TS is a matrix of a scaled 2D DCT, and
S{circle around (×)}S is a matrix of scale factors for the scaled 2D DCT.
The result of the operation in equation (5) is a matrix of an N×N 2D DCT.
A 2D DCT may be performed on an N×N matrix of input samples Y in a separable manner, for one dimension at a time. For example, a 1D DCT may be performed on each row of Y to obtain an intermediate matrix, and a 1D DCT may then be performed on each column of the intermediate matrix. Alternatively, a 1D DCT may be performed on each column of Y followed by a 1D DCT on each row of the intermediate matrix.
Equation (5) indicates that a 2D DCT may be performed on Y by first performing a scaled 2D DCT on Y and then scaling the results. Equation (5) also indicates that the scaling for the row and column 1D DCTs may be merged into a single step (which is matrix product by S{circle around (×)}S) applied to the results of the scaled 2D DCT.
The 1D IDCT in equation (2) may be expressed in matrix form, as follows:
T−1=Tt=TStS, Eq (6)
where Tt is an N×N matrix of a full 1D IDCT and “t” denotes the transpose.
A 2D IDCT may be expressed as:
(T{circle around (×)}T)−1=T−1{circle around (×)}T−1=(TStS){circle around (×)}(TStS)=(TSt{circle around (×)}TSt)(S{circle around (×)}S). Eq (7)
Equation (7) indicates that a 2D IDCT may be performed on an N×N matrix of transform coefficients X by first scaling the transform coefficients and then performing a scaled 2D IDCT on the scaled transform coefficients. Equation (7) also indicates that the scaling for the row and column 1D IDCTs may be merged into a single step preceding the scaled 2D IDCT.
A scaled architecture is a design that uses a scaled transform, and a full architecture is a design that uses a full transform. A scaled architecture may have lower multiplicative complexity than a full architecture. For example, a scaled architecture may perform a scaled 2D IDCT (TSt{circle around (×)}TSt) in a separable row-column fashion and may use an 8-point scaled 1D IDCT TS from the AAN decomposition for each row and each column. The multiplicative complexity of this scaled architecture may be 8*8+16*5=64+80=144, or 64 multiplications for scaling and 5 multiplications for each of the 8 rows and 8 columns. In certain situations, the scaling may be combined with quantization, in which case the multiplicative complexity of the scaled architecture may be reduced to about 80 multiplications. A full architecture may perform a 2D IDCT (T{circle around (×)}T) in a row-column fashion and may use the best-known full 8-point 1D IDCT T for each row and each column. The multiplicative complexity of this full architecture may be 16*11=176, or 11 multiplications for each of the 8 rows and 8 columns. For the separable implementation, the scaled architecture may have lower multiplicative complexity than the full architecture.
A scaled architecture may be used in designs that favor low complexity. The scaled architecture may be advantageous when there are only few non-zero transform coefficients to scale, which may often be the case for 2D IDCT in an image/video decoder. The scaled architecture may also be advantageous in designs that allow the scaling of transform coefficients to be combined with quantization and/or inverse quantization in an image/video encoder/decoder (codec), e.g., as shown in
A full architecture may be desirable in designs that favor ease of use. For example, many computing environments and applications may support multiple image and video coding standards. In these instances, it may be more convenient to have a transform engine that implements full transform and to provide a flexible input/output interface to allow the transform engine to be used with various quantizers and codecs. The full architecture may provide simple interface and may be more suitable in such environments.
A transform design that can flexibly support different applications via scaled and full interfaces are described herein. The transform design may receive full input values via the full interface, perform a full transform on these input values, and provide full output values, similar to the full architecture. The transform design may also receive scaled input values via the scaled interface, perform a scaled transform on these input values, and provide scaled output values, similar to the scaled architecture. The transform design may internally implement a separable scaled transform to potentially achieve lower complexity and/or improved precision. The transform design may thus be able to achieve lower complexity for certain applications, provide ease of use for other applications, or provide both lower complexity and ease of use in certain instances. The transform design may be used for both forward transforms (e.g., DCT) and inverse transforms (e.g., IDCT). For clarity, the transform design is specifically described below for IDCT.
The scaled and non-scaled/full 2D IDCT architectures may be expressed as follows.
scaled 2D IDCT: T−1{circle around (×)}T−1=(TSt{circle around (×)}TSt)(S{circle around (×)}S), and Eq (8)
non-scaled 2D IDCT: T−1{circle around (×)}T−1=(TStS){circle around (×)}(TStS). Eq (9)
A full/non-scaled interface may receive transform coefficients. A full 2D IDCT may be performed on these transform coefficients, as follows:
Y=Θ(X)≈TtXT, Eq (10)
where X is a matrix of transform coefficients,
Θ(.) is an approximation of the full 2D IDCT, and
Y is a matrix of output samples.
The operator notation (.) in equation (10) is used to indicate that fixed-point approximations may not be based solely on linear operations.
The full 2D IDCT may be achieved by performing a full 1D IDCT on each row and each column of X, as follows:
θ(xi)≈Ttxi, Eq (11)
where xi is the i-th row or column of X, and
θ(.) is an approximation of the full 1D IDCT.
θ(.) may be used for row-column implementation of 2D operator Θ(.).
A scaled interface may receive scaled transform coefficients, which may be obtained as follows:
XS=Σ(X)≈StXS, Eq (12)
where Σ(.) is an approximation of the 2D scaling operation, and
X
S is a matrix of scaled transform coefficients.
A scaled 2D IDCT may be performed on the scaled transform coefficients, as follows:
Y=Ξ(XS)=TStXSTS, Eq (13)
where Ξ(.) is an approximation of the scaled 2D IDCT.
The scaled 2D IDCT may be achieved by performing a scaled 1D IDCT on each row and each column of XS, as follows:
ξ(xS,i)≈TStxS,i, Eq (14)
where xS,i is the i-th row or column of XS, and
ξ(.) is an approximation of the scaled 1D IDCT.
ξ(.) may be used for row-column implementation of 2D operator Ξ(.).
As shown in equation (13), the scaled interface may be realized by implementing the 2D operator Ξ(.). As shown in equations (12) and (13), the full interface may be realized by implementing the 2D scaling operator Σ(.) in addition to the 2D operator Ξ(.). The full 2D IDCT may then be performed as follows:
Y=Ξ(Σ(X))=:Ξ(X). Eq (15)
Equation (15) indicates that a full 2D IDCT may be performed on full transform coefficients X by first scaling these transform coefficients with the 2D scaling operator Σ(.) and then performing a scaled 2D IDCT on the scaled transformed coefficients with the 2D operator Ξ(.). The 2D operator Ξ(.) may, in turn, be implemented by a row-column cascade of 1D operators ξ(.).
The 2D operator Θ(.) for a separable full 2D IDCT may thus be implemented with the 2D operator Ξ(.) for a separable scaled 2D IDCT and the 2D scaling operator Σ(.). The 2D scaling may be implemented in various manners, as described below. The resulting complexity and performance of the separable full 2D IDCT implemented with separable scaled 2D IDCT and 2D scaling may be comparable with a natively implemented full 2D IDCT.
IDCT stage 114 performs an N-point scaled 1D IDCT on each row of the block of scaled transform coefficients from 2D scaling stage 112. IDCT stage 116 performs an N-point scaled 1D IDCT on each column of an intermediate block generated by IDCT stage 114. The scaled 1D IDCTs for stages 114 and 116 may operate directly on their input data without doing any internal pre- or post scaling. After all of the rows and columns are processed, output formatting stage 118 may shift the resulting quantities from IDCT stage 116 by P bits to the right to generate an N×N block of output samples Y for the full 2D IDCT. The scale factors and the precision constant P may be chosen such that the entire 2D IDCT may be implemented using registers of the desired width.
The 2D scaling in stage 112 may be expressed as:
XS,ij=(Xij·Ai·Aj)>>R, Eq (16)
where Xij is a transform coefficient in the i-th row and j-th column of X,
Ai and Aj are the i-th and j-th diagonal elements, respectively, of S,
XS,ij is a scaled transform coefficient in the i-th row and j-th column of XS, and
“>>R” denotes a signed right shift operation by R bits.
R is a constant ensuring P bits of added fixed-point precision in scaled transform coefficients XS,ij.
A table may store scale factors Aij=Ai·Aj, for i=0, . . . , N−1 and j=0, . . . , N−1. Each element of X may be multiplied by a corresponding scale factor in the table. Up to N·N multiplications may be performed for the N·N elements of X.
X′ij=Xij·Ai,
XS,ij=(X′ij·Aj)>>R. Eq (17)
Scaling stage 122 may thus perform 2D scaling in a separable manner on rows followed by columns (or on columns followed by rows). Separable row-column scaling may allow the same hardware to be used for scaling of rows and scaling of columns, which may reduce implementation complexity. Up to 2·N·N multiplications may be performed for the N·N elements of X. However, the actual number of multiplications may be much fewer than 2·N·N since some of the scale factors A0 through AN-1 may have trivial values (e.g., 256), and multiplication with these trivial scale factors may be implemented with simple shift operations. Stages 124, 126, and 128 may operate in the same manner as stages 114, 116, and 118, respectively, in
As shown in
Various types of scaled 1D IDCT may be used for the row-column 1D IDCTs in
α1=α2=1,
β1=β2=Cπ/4=cos(π/4)≈0.707106781
γ1=C3π/8=cos(3π/8)≈0.382683432, and
δ1=S3π/8=sin(3π/8)≈0.923879533. Eq (18)
Flow graph 200 may receive eight transform coefficients X[0] through X[7] and scale these transform coefficients with scale factors A0 through A7 to obtain eight scaled transform coefficients A0·X[0] through A7·X[7]. Alternatively, flow graph 200 may receive the eight scaled transform coefficients directly. In either case, flow graph 200 performs an 8-point 1D IDCT on the eight scaled transform coefficients and generates eight output samples x[0] through x[7]. The scale factors A0 through A7 are as follows:
Flow graph 200 includes a number of butterfly operations. A butterfly operation receives two input values and generates two output values, where one output value is the sum of the two input values and the other output value is the difference of the two input values. For example, the butterfly operation on input values A0·X[0] and A4·X[4] generates an output value A0·X[0]+A4·X[4] for the top branch and an output value A0·X[0]−A4·X[4] for the bottom branch.
The factorization shown in
Multiplication of an integer variable x with an irrational constant μ in fixed-point integer arithmetic may be achieved by approximating the irrational constant with a rational dyadic constant, as follows:
μ≈c/2b, Eq (19)
where μ is the irrational constant to be approximated, and
c/2b is the rational dyadic constant.
Given integer variable x and rational dyadic constant u=c/2b an integer-valued product
y=(x·c)/2b Eq (20)
may be approximated using a series of intermediate values
x0, x1, x2, . . . , xt, Eq (21)
where x0=0, x1=x, and for all 2≦i≦t values, xi is obtained as follows:
xi=±xj±xk·2s
where xk·2s
In equation (22), xi may be equal to xj+xk·2s
xt≈y. Eq (23)
Multiplication of an integer variable x with two irrational constants μ and η in fixed-point integer arithmetic may be achieved by approximating the irrational constants with rational dyadic constants, as follows:
μ≈c/2b and η≈e/2d, Eq (24)
where c/2b and e/2d are two rational dyadic constants, and
b, c, d and e are integers, with b>0 and d>0.
Given integer variable x and rational dyadic constants u=c/2b and v=e/2d, two integer-valued products
y=(x·c)/2b and z=(x·e)/2d Eq (25)
may be approximated using a series of intermediate values
x0, x1, x2, . . . , xt, Eq (26)
where x0=0, x1=x, and for all 2≦i≦t values, xi is obtained as follows:
xi=±xj±xk·2s
The series is defined such that the desired integer-valued products are obtained at steps m and n, as follows:
xm≈y and xn≈z, Eq (28)
where m, n≦t and either m or n is equal to t.
As shown in equations (24) through (28), the multiplication of integer variable x with irrational constants μ and η may be approximated with a common series of intermediate values generated by shift and add operations and using intermediate results to reduce the total number of operations.
In the computation described above, trivial operations such as additions and subtractions of zeros and shifts by zero bits may be omitted. The following simplifications may be made:
xi=±x0±xk·2s
xi=±xj±xk·20xi=±xj±xk. Eq (30)
In equation (29), the expression to the left of “” involves an addition or subtraction of zero (denoted by x0) and may be performed with one shift, as shown by the expression to the right of “”. In equation (30), the expression to the left of “” involves a shift by zero bits (denoted by 20) and may be performed with one addition, as shown by the expression to the right of “”. Equations (29) and (30) may be applied to equations (22) and (27) in the computation of xi.
To reduce computation, a first common factor F1 may be applied to constant factors α1 and β1 in flow graph 200, and second common factor F2 may be applied to constant factors α2, β2, δ1 and γ1, as follows:
α′1=α1·F1, β′1=β1·F1, and
α′2=α2·F2, β′2=β2·F2, γ′1=γ1·F2, δ′1=δ1·F2. Eq (31)
The scale factors A0 through A7 may also be scaled to account for the common factors F1 and F2, as follows:
A′0=A0, A′4=A4,
A′2=A2/F1, A′6=A6/F1, and
A′1=A1/F2, A′5=A5/F2, A′3=A3/F2, A′7=A7/F2. Eq (32)
Different combinations of values for common factors F1 and F2 may be evaluated. For each combination of F1 and F2 values, the total number of logical and arithmetic operations for the 1D IDCT and the precision of the output samples may be determined.
Table 1 shows an example fixed-point approximation for the 1D IDCT in
In Table 1, right shift by 8 cancels out multiplication by a factor of 256 in scale factors A′0, A′1, A′2, and A′4, which enables additional complexity reduction.
In the design shown in Table 1, an 8-point scaled 1D IDCT may be performed with 50 add operations and 24 shift operations. An 8-point full 1D IDCT may be performed with 61 add operations and 39 shift operations. The scaling with scale factors A′0 through A′7 may be performed prior to the scaled 1D IDCT (as shown in
Table 1 shows an example fixed-point approximation for the 1D IDCT in
As shown in
Various types of scaled 1D DCT may be used for the scaled 1D DCTs in
αa=αb=1,
βa=βb=1/Cπ/4=1/cos(π/4)
γa=2C3π/8=2 cos(3π/8), and
δa=2S3π/8=2 sin(3π/8). Eq (33)
The flow graphs for the IDCT and DCT in
IDCT engine 516 may perform scaled 1D IDCTs on rows of the block of scaled transform coefficients from multiplexer 512 and provide rows of a block of intermediate results to buffer 518. IDCT engine 516 may then perform scaled 1D IDCTs on columns of the block of intermediate results from buffer 518 and provide a block of final results to buffer 518. A unit 520 performs output formatting on the final results in buffer 518 and provides output samples.
For clarity, much of the description above is for DCT and IDCT. In general, the techniques described herein may be used for any type of transform such as DCT, IDCT, DFT, IDFT, MLT, inverse MLT, MCLT, inverse MCLT, etc. The techniques may also be used for any factorization of a transform, with several example factorizations being given in
The full transform may be a full 2D inverse transform. In this case, a block of first input values may be received via the first interface and scaled to obtain a block of scaled input values. A scaled 1D transform may be performed on each row of the block of scaled input values to obtain an intermediate block. A scaled 1D transform may be performed on each column of the intermediate block to obtain a block of first output values. The scaled 1D transforms may also be performed on columns followed by rows.
The full transform may also be a full 2D forward transform. In this case, a block of first input values may be received via the first interface. A scaled 1D transform may be performed on each row of the block of input values to obtain a first intermediate block. A scaled 1D transform may be performed on each column of the first intermediate block to obtain a second intermediate block. The second intermediate block may be scaled to obtain a block of first output values.
The full transform may be a full 2D IDCT. In this case, a block of transform coefficients may be received via the first interface and scaled to obtain a block of scaled transform coefficients. Each transform coefficient may be scaled with a respective scale factor to obtain a corresponding scaled transform coefficient, e.g., as shown in
The scaled transform may be a scaled 2D IDCT. In this case, a block of scaled transform coefficients may be received via the second interface. A scaled 1D IDCT may then be performed on each row of the block of scaled transform coefficients to obtain an intermediate block. A scaled 1D IDCT may be performed on each column of the intermediate block to obtain a block of output samples.
The full transform may be a full 2D DCT, and the scaled transform may be a scaled 2D DCT. A full 2D DCT may be performed on a block of input samples as described above to obtain a block of full transform coefficients for the first interface. A scaled 2D DCT may also be performed on the block of input samples to obtain a block of scaled transform coefficients for the second interface.
At decoding system 850, an entropy decoder 860 may perform entropy decoding on the compressed data in a manner complementary to the entropy encoding by encoder 826 and provide quantized coefficients. An inverse quantizer 862 may map the quantized coefficients to full or scaled transform coefficients. A unit 862 may perform full 2D IDCT on full transform coefficients or scaled 2D IDCT on scaled transform coefficients and provide blocks of output samples. Unit 862 may support both full and scaled interfaces. An image/video decoder 866 may perform decompression on the blocks of output samples and provide blocks of pixels.
At encoding system 810, unit 822 may perform scaled 2D DCT and provide scaled transform coefficients. Quantizer 824 may perform scaling (e.g., stage 318 in
A storage unit 940 may store the compressed data from processor 920. A transmitter 942 may transmit the compressed data. A controller/processor 950 controls the operation of various units in encoding system 900. A memory 952 stores data and program codes for encoding system 900. One or more buses 960 interconnect various units in encoding system 900.
A display unit 1040 displays reconstructed images and video from processor 1020. A controller/processor 1050 controls the operation of various units in decoding system 1000. A memory 1052 stores data and program codes for decoding system 1000. One or more buses 1060 interconnect various units in decoding system 1000.
Processors 920 and 1020 may each be implemented with one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), and/or some other type of processors. Alternatively, processors 920 and 1020 may each be replaced with one or more random access memories (RAMs), read only memory (ROMs), electrical programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), magnetic disks, optical disks, and/or other types of volatile and nonvolatile memories known in the art.
The techniques described herein may be implemented in various types of apparatus. For example, the techniques may be implemented in different types of processors, different types of integrated circuits, different types of electronics devices, different types of electronics circuits, etc.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other designs without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claims priority to provisional U.S. Application Serial No. 60/797,562, entitled “CONVERGENCE OF SCALED AND NON-SCALED IDCT ARCHITECTURES,” filed Mar. 29, 2006, assigned to the assignee hereof and incorporated herein by reference.
Number | Date | Country | |
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60787562 | Mar 2006 | US |