1. Field
The present disclosure relates generally to processing, and more specifically to techniques for performing transforms on data.
2. Background
Transforms are commonly used to convert data from one domain to another domain. For example, discrete cosine transform (DCT) is commonly used to transform data from spatial domain to frequency domain, and inverse discrete cosine transform (IDCT) is commonly used to transform data from frequency domain to spatial domain. DCT is widely used for image/video compression to spatially decorrelate blocks of picture elements (pixels) in images or video frames. The resulting transform coefficients are typically much less dependent on each other, which makes these coefficients more suitable for quantization and encoding. DCT also exhibits energy compaction property, which is the ability to map most of the energy of a block of pixels to only few (typically low order) transform coefficients. This energy compaction property can simplify the design of encoding algorithms.
Transforms such as DCT and IDCT may be performed on large quantity of data. Hence, it is desirable to perform transforms as efficiently as possible. Furthermore, it is desirable to perform computation for transforms using simple hardware in order to reduce cost and complexity.
There is therefore a need in the art for techniques to efficiently perform transforms on data.
Techniques for efficiently performing transforms on data are described herein. According to an aspect, an apparatus performs multiplication of a group of data values with a group of rational dyadic constants that approximates at least one irrational constant scaled by a common factor. Each rational dyadic constant is a rational number with a dyadic denominator. The common factor is selected based on pre-computed numbers of operations for multiplication of a data value by different possible values of at least one rational dyadic constant. The pre-computed numbers of operations may be stored in a look-up table or some other data structure and may be used to evaluate different possible values for the common factor. The use of the common factor may reduce complexity and/or improve precision. The multiplication may be performed for various transforms such DCT, IDCT, etc.
Various aspects and features of the disclosure are described in further detail below.
The techniques described herein may be used for various types of transforms such as DCT, IDCT, discrete Fourier transform (DFT), inverse DFT (IDFT), modulated lapped transform (MLT), inverse MLT, modulated complex lapped transform (MCLT), inverse MCLT, etc. The techniques may also be used for various applications such as image, video, and audio processing, communication, computing, data networking, data storage, graphics, etc. In general, the techniques may be used for any application that uses a transform. For clarity, the techniques are described below for DCT and IDCT, which are commonly used in image and video processing.
A one-dimensional (1D) N-point DCT and a 1D N-point IDCT of type II may be defined as follows:
x[n] is a 1D spatial domain function, and
X[k] is a 1D frequency domain function.
The 1D DCT in equation (1) operates on N spatial domain values x[0] through x[N-1] and generates N transform coefficients X[0] through X[N-1]. The 1D IDCT in equation (2) operates on N transform coefficients and generates N spatial domain values. Type II DCT is one type of transform and is commonly believed to be one of the most efficient transforms among several energy compacting transforms proposed for image/video compression.
The 1D DCT may be used for a two 2D DCT, as described below. Similarly, the 1D IDCT may be used for a 2D IDCT. By decomposing the 2D DCT/IDCT into a cascade of 1D DCTs/IDCTs, the efficiency of the 2D DCT/IDCT is dependent on the efficiency of the 1D DCT/IDCT. In general, 1D DCT and 1D IDCT may be performed on any vector size, and 2D DCT and 2D IDCT may be performed on any block size. However, 8×8 DCT and 8×8 IDCT are commonly used for image and video processing, where N is equal to 8. For example, 8×8 DCT and 8×8 IDCT are used as standard building blocks in various image and video coding standards such as JPEG, MPEG-1, MPEG-2, MPEG-4 (P.2), H.261, H.263, etc.
The 1D DCT and 1D IDCT may be implemented in their original forms shown in equations (1) and (2), respectively. However, substantial reduction in computational complexity may be realized by finding factorizations that result in as few multiplications and additions as possible. A factorization for a transform may be represented by a flow graph that indicates specific operations to be performed for that transform.
Cπ/4=cos (π/4)≈0.707106781,
C3π/8=cos(3π/8)≈0.382683432, and
S3π/8=sin(3π/8)≈0.923879533.
Flow graph 100 receives eight scaled transform coefficients A0·X[0] through A7·X[7], performs an 8-point IDCT on these coefficients, and generates eight output samples x[0] through x[7]. A0 through A7 are scale factors and are given below:
Flow graph 100 includes a number of butterfly operations. A butterfly operation receives two input values and generates two output values, where one output value is the sum of the two input values and the other output value is the difference of the two input values. For example, the butterfly operation on input values A0·X[0] and A4·X[4] generates an output value A0·X[0]+A4·X[4] for the top branch and an output value A0·X[0]−A4·X[4] for the bottom branch.
The flow graphs for the IDCT and DCT in
The factorization shown in
The multiplications in
In an aspect, common factors are used to reduce the total number of operations for a transform and/or to improve the precision of the transform results. A common factor is a constant that is applied to one or more intermediate variables in a transform. An intermediate variable may also be referred to as a data value, etc. A common factor may be absorbed with one or more transform constants and may also be accounted for by altering one or more scale factors. A common factor may improve the approximation of one or more (irrational) transform constants by one or more rational dyadic constants, which may then result in a fewer total number of operations and/or improved precision.
In general, any number of common factors may be used for a transform, and each common factor may be applied to any number of intermediate variables in the transform. In one design, multiple common factors are used for a transform and are applied to multiple groups of intermediate variables of different sizes. In another design, multiple common factors are applied to multiple groups of intermediate variables of the same size.
A first common factor F1 is applied to a first group of two intermediate variables X1 and X2, which is generated based on transform coefficients X[2] and X[6]. The first common factor F1 is multiplied with X1, is absorbed with transform constant Cπ/4, and is accounted for by altering scale factors A2 and A6. A second common factor F2 is applied to a second group of four intermediate variables X3 through X6, which is generated based on transform coefficients X[1], X[3], X[5] and X[7]. The second common factor F2 is multiplied with X4, is absorbed with transform constants Cπ/4, C3π/8 and S3π/8, and is accounted for by altering scale factors A1, A3, A5 and A7.
The first common factor F1 may be approximated with a rational dyadic constant α1, which may be multiplied with X1 to obtain an approximation of the product X1·F1. A scaled transform factor F1·Cπ/4 may be approximated with a rational dyadic constant β1, which may be multiplied with X2 to obtain an approximation of the product X2·F1·Cπ/4. An altered scale factor A2/F1 may be applied to transform coefficient X[2]. An altered scale factor A6/F1 may be applied to transform coefficient X[6].
The second common factor F2 may be approximated with a rational dyadic constant α2, which may be multiplied with X4 to obtain an approximation of the product X4·F2. A scaled transform factor F2·Cπ/4 may be approximated with a rational dyadic constant β2, which may be multiplied with X3 to obtain an approximation of the product X3·F2·Cπ/4. A scaled transform factor F2·C3π/8 may be approximated with a rational dyadic constant γ2, and a scaled transform factor F2·S3π/8 may be approximated with a rational dyadic constant β2. Rational dyadic constant γ2 may be multiplied with X5 to obtain an approximation of the product X5·F2·C3π/8 and also with X6 to obtain an approximation of the product X6·F2·C3π/8. Rational dyadic constant β2 may be multiplied with X5 to obtain an approximation of the product X5·F2·S3π/8 and also with X6 to obtain an approximation of the product X6·F2·S3π/8. Altered scale factors A1/F2, A3/F2, A5/F2 and A7/F2 may be applied to transform coefficients X[1], X[3], X[5] and X[7], respectively.
Six rational dyadic constants α1, β1, α2, β2, γ2 and δ2 may be defined for six constants, as follows:
α1≈F1, β1≈F1·cos(π/4), Eq (3)
α2≈F2, β2≈F2·cos(π/4), γ2≈F2·cos(3π/8).
Multiple common factors may be applied to multiple groups of intermediate variables, and each group may include any number of intermediate variables. The selection of the groups may be dependent on various factors such as the factorization of the transform, where the transform constants are located within the transform, etc. Multiple common factors may be applied to multiple groups of intermediate variables of the same size (not shown in
Multiplication of an intermediate variable x with a rational dyadic constant u may be performed in various manners in fixed-point integer arithmetic. The multiplication may be performed using logical operations (e.g., left shift, right shift, bit-inversion, etc.), arithmetic operations (e.g., add, subtract, sign-inversion, etc.) and/or other operations. The number of logical and arithmetic operations needed for the multiplication of x with u is dependent on the manner in which the computation is performed and the value of the rational dyadic constant u. Different computation techniques may require different numbers of logical and arithmetic operations for the same multiplication of x with u. A given computation technique may require different numbers of logical and arithmetic operations for the multiplication of x with different values of u.
A common factor may be selected for a group of intermediate variables based on criteria such as:
In general, it is desirable to minimize the number of logical and arithmetic operations for multiplication of an intermediate variable with a rational dyadic constant. On some hardware platforms, arithmetic operations (e.g., additions) may be more complex than logical operations, so reducing the number of arithmetic operations may be more important. In the extreme, computational complexity may be quantified based solely on the number of arithmetic operations, without taking into account logical operations. On some other hardware platforms, logical operations (e.g., shifts) may be more expensive, and reducing the number of logical operations (e.g., reducing the number of shift operations and/or the total number of bits shifted) may be more important. In general, a weighted average number of logical and arithmetic operations may be used, where the weights may represent the relative complexities of the logical and arithmetic operations.
The precision of the results may be quantified based on various metrics such as those given in Table 6 below. In general, it is desirable to reduce the number of logical and arithmetic operations (or computational complexity) for a given precision. It may also be desirable to trade off complexity for precision, e.g., to achieve higher precision at the expense of some additional operations.
As shown in
Multiplications in a transform, e.g., the IDCT shown in
μ≈c/2b, Eq (4)
where μ is the irrational constant to be approximated, c/2b is the rational dyadic constant, b and c are integers, and b>0. The series of intermediate values is determined by the one or more rational dyadic constants being multiplied with integer variable x. The computation techniques may be illustrated by the following examples.
In
where Cπ/48 is a rational dyadic constant that is an 8-bit approximation of Cπ/4.
Multiplication of integer variable x by constant Cπ/48 may be expressed as:
y=(x·181)/256 . Eq (6)
The multiplication in equation (6) may be achieved with the following series of operations:
The binary value to the right of “//” is an intermediate constant that is multiplied with variable x.
The desired product is equal to y4, or y4=y. The multiplication in equation (6) may be performed with three additions and three shifts to generate three intermediate values y2, y3 and y4.
In
where C3π/87 is a rational dyadic constant that is a 7-bit approximation of C3π/8, and S3π/89 is a rational dyadic constant that is a 9-bit approximation of S3π/8.
Multiplication of integer variable x by constants C3π/87 and S3π/89 may be expressed as:
y=(x·49)/128 and z=(x·473)/512. Eq (10)
The multiplications in equation (10) may be achieved with the following series of operations:
The desired products are equal to w6 and w8, or w6=y and w8=z. The two multiplications in equation (10) may be jointly performed with five additions and five shifts to generate seven intermediate values w2 through w8. Additions of zeros are omitted in the generation of w3 and w6. Shifts by zero are omitted in the generation of w4 and w5.
For the 8-point IDCT shown in
For the 8-point DCT shown in
For the IDCT shown in
For a given value of F1, rational dyadic constants α1 and β1 may be obtained for F1 and F1·Cπ/4, respectively. The numbers of logical and arithmetic operations may then be determined for multiplication of X1 with α1 and multiplication of X2 with β1. For a given value of F2, rational dyadic constants α2, β2, γ2 and δ2 may be obtained for F2, F2 Cπ4, F2·C3π/8 and F2·S3π/8, respectively. The numbers of logical and arithmetic operations may then be determined for multiplication of X4 with α2, multiplication of X3 with β2, and multiplications of X5 with both 72 and β2. The number of operations for multiplications of X6 with γ2 and δ2 is equal to the number of operations for multiplications of X5 with δ2 and δ2.
To facilitate the evaluation and selection of the common factors, the number of logical and arithmetic operations may be pre-computed for multiplication with different possible values of rational dyadic constants. The pre-computed numbers of logical and arithmetic operations may be stored in a data structure such as a look-up table, a list, a linked list, a sorted list (a priority queue), an orthogonal sorted list, multiple tables or lists, a combination of table and/or list, etc.
The entry in the i-th column and j-th row of look-up table 400 contains the number of logical and arithmetic operations for joint multiplication of intermediate variable x with both ci for the first rational dyadic constant C1 and cj for the second rational dyadic constant C2. The value for each entry in look-up table 400 may be determined by evaluating different possible series of intermediate values for the joint multiplication with ci and cj for that entry and selecting the best series, e.g., the series with the fewest operations. The entries in the first row of look-up table 400 (with c0=0 for the second rational dyadic constant C2) contain the numbers of operations for multiplication of intermediate variable x with just ci for the first rational dyadic constant C1. Since the look-up table is symmetrical, entries in only half of the table (e.g., either above or below the main diagonal) may be filled. Furthermore, the number of entries to fill may be reduced by considering the irrational constants being approximated with the rational dyadic constants C1 and C2.
For a given value of F1, rational dyadic constants α1 and β1 may be determined. The numbers of logical and arithmetic operations for multiplication of X1 with α1 and multiplication of X2 with β1 may be readily determined from the entries in the first row of look-up table 400, where α1 and β1 correspond to C1. Similarly, for a given value of F2, rational dyadic constants α2, β2, γ2 and δ2 may be determined. The numbers of logical and arithmetic operations for multiplication of X4 with α2 and multiplication of X3 with β2 may be determined from the entries in the first row of look-up table 400, where α2 and β2 correspond to C1. The number of logical and arithmetic operations for joint multiplication of X5 with γ2 and δ2 may be determined from an appropriate entry in look-up table 400, where γ2 may correspond to C1 and δ2 may correspond to C2, or vice versa.
For each possible combination of values for F1 and F2, the precision metrics in Table 6 may be determined for a sufficient number of iterations with different random input data. The values of F1 and F2 that result in poor precision (e.g., failure of the metrics) may be discarded, and the values of F1 and F2 that result in good precision (e.g., pass of the metrics) may be retained.
Tables 1 through 5 show five fixed-point approximations for the IDCT in
Table 1 gives the details of algorithm A, which uses a common factor of 1/1.0000442471 for each of the two groups.
Table 2 gives the details of algorithm B, which uses a common factor of 1/1.0000442471 for the first group and a common factor of 1/1.02053722659 for the second group.
Table 3 gives the details of algorithm C, which uses a common factor of 1/0.87734890555 for the first group and a common factor of 1/1.02053722659 for the second group.
Table 4 gives the details of algorithm D, which uses a common factor of 1/0.87734890555 for the first group and a common factor of 1/0.89062054308 for the second group.
Table 5 gives the details of algorithm E, which uses a common factor of 1.087734890555 for the first group and a common factor of 1/1.22387468002 for the second group.
The precision of the output samples from an approximate IDCT may be quantified based on metrics defined in IEEE Standard 1180-1190 and its pending replacement. This standard specifies testing a reference 64-bit floating-point DCT followed by the approximate IDCT using data from a random number generator. The reference DCT receives random data for a block of input pixels and generates transform coefficients. The approximate IDCT receives the transform coefficients (appropriately rounded) and generates a block of reconstructed pixels. The reconstructed pixels are compared against the input pixels using five metrics, which are given in Table 6. Additionally, the approximate IDCT is required to produce all zeros when supplied with zero transform coefficients and to demonstrate near-DC inversion behavior. All five algorithms A through E given above pass all of the metrics in Table 6.
For clarity, much of the description above is for an 8-point scaled IDCT and an 8-point scaled DCT. The techniques described herein may be used for any type of transform such as DCT, IDCT, DFT, IDFT, MLT, inverse MLT, MCLT, inverse MCLT, etc. The techniques may also be used for any factorization of a transform, with several example factorizations being given in
The number of operations for a transform may be dependent on the manner in which multiplications are performed. The computation techniques described above unroll multiplications into series of shift and add operations, use intermediate results to reduce the number of operations, and perform joint multiplication with multiple constants using a common series. The multiplications may also be performed with other computation techniques, which may influence the selection of the common factors.
The transforms with common factors described herein may provide certain advantages such as:
Transforms with common factors may be used for various applications such as image and video processing, communication, computing, data networking, data storage, graphics, etc. Example use of transforms for video processing is described below.
A display unit 540 displays reconstructed images and video from processor 520. A controller/processor 550 controls the operation of various units in decoding system 500. A memory 552 stores data and program codes for decoding system 500. One or more buses 560 interconnect various units in decoding system 500.
Processor 520 may be implemented with one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), and/or some other type of processors. Alternatively, processor 520 may be replaced with one or more random access memories (RAMs), read only memory (ROMs), electrical programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), magnetic disks, optical disks, and/or other types of volatile and nonvolatile memories known in the art.
The techniques described herein may be implemented in hardware, firmware, software, or a combination thereof. For example, the logical (e.g., shift) and arithmetic (e.g., add) operations for multiplication of a data value with a constant value may be implemented with one or more logics, which may also be referred to as units, modules, etc. A logic may be hardware logic comprising logic gates, transistors, and/or other circuits known in the art. A logic may also be firmware and/or software logic comprising machine-readable codes.
In one design, an apparatus comprises a first logic to receive a group of data values and a second logic to perform multiplication of the group of data values with a group of rational dyadic constants that approximates at least one irrational constant scaled by a common factor. Each rational dyadic constant is a rational number with a dyadic denominator. The common factor is selected based on pre-computed numbers of operations for multiplication of a data value by different possible values of at least one rational dyadic constant. The first and second logics may be separate logics, the same common logic, or shared logic.
For a firmware and/or software implementation, multiplication of a data value with a constant value may be achieved with machine-readable codes that perform the desired logical and arithmetic operations. The codes may be hardwired or stored in a memory (e.g., memory 552 in
The techniques described herein may be implemented in various types of apparatus. For example, the techniques may be implemented in different types of processors, different types of integrated circuits, different types of electronics devices, different types of electronics circuits, etc.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other designs without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claims priority to provisional U.S. Application Ser. No. 60/758,464, filed Jan. 11, 2006, entitled “Efficient Multiplication-Free Implementations of Scaled Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT),” assigned to the assignee hereof and incorporated herein by reference.
Number | Date | Country | |
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60758464 | Jan 2006 | US |