Patent Application
20250116906
This application claims the benefit of priority to Japanese Patent Application Number 2023-174163 filed on Oct. 6, 2023. The entire contents of the above-identified application are hereby incorporated by reference.
The technology described in the present specification relates to a transistor and a manufacturing method for the transistor.
In the related art, an example of a transistor is known, as described in JP 2000-332253 A. The transistor disclosed in JP 2000-332253 A includes a semiconductor film constituted of a polysilicon film that constitutes an active layer of a TFT, and the semiconductor film has a plurality of high-concentration source/drain regions formed at predetermined intervals in a channel width direction. All of the high-concentration source/drain regions are formed at positions shifted in a channel length direction when viewed from an end of a gate electrode. A plurality of contact holes are formed corresponding to the respective high-concentration source/drain regions. In the semiconductor film, a portion facing the end of the gate electrode and portions between adjacent high-concentration source/drain regions in the channel width direction are low-concentration regions.
JP 2000-332253 A discloses a structure in which a semiconductor film is divided into a plurality of small island regions arranged in parallel at predetermined intervals in the channel width direction. With this structure, it is unlikely that grain boundaries will concentrate in some of the small island regions, and thus it is possible to prevent concentration of source-drain current caused by uneven distribution of grain boundaries. However, when the semiconductor film is divided into the plurality of small island regions, each small island region has an outer peripheral end, and thus the sum of the lengths of the outer peripheral ends in the plurality of small island regions is greater than the length of the outer peripheral end of the semiconductor film when the semiconductor film has a single structure. For this reason, there is a high possibility that localized protrusions caused by minute pieces of foreign matter will occur at the outer peripheral ends of the plurality of small island regions, or that minute foreign matter will remain and become protrusions. When such protrusions occur at the outer peripheral ends of the small island regions, a locally thin film portion will occur in a gate insulating film formed on an upper layer side, causing problems such as a deterioration in voltage resistance performance due to the thin film portion or an increased susceptibility to leakage. As a result, there is a concern of a decrease in yield.
The technology described in this specification has been contrived in view of the above circumstances, and an object thereof is to improve a yield.
(1) A transistor according to the technology described in this specification includes a semiconductor portion extending in a first direction, the semiconductor portion being made of a semiconductor material, a first electrode extending in a second direction intersecting the first direction, the first electrode being disposed overlapping a portion of the semiconductor portion, a first insulating film interposed between the first electrode and the semiconductor portion, a second electrode disposed overlapping a portion of the semiconductor portion, the second electrode being connected to the semiconductor portion, and a third electrode disposed overlapping a portion of the semiconductor portion at a position spaced apart from a connection position between the second electrode and the semiconductor portion in the first direction, the third electrode being connected to the semiconductor portion, in which the first insulating film includes a first thick portion and a second thick portion having a film thickness greater than a thickness of the first thick portion, at least two of the first thick portions are disposed at intervals in the second direction at positions overlapping both the first electrode and the semiconductor portion, and the second thick portion is disposed to be interposed between the two first thick portions in the second direction at a position overlapping both the first electrode and the semiconductor portion.
(2) In addition to (1) described above, in the transistor, the first insulating film may have a layered structure of a lower insulating film disposed on an upper layer side of the semiconductor portion and an upper insulating film disposed on an upper layer side of the lower insulating film and made of a material different from a material of the lower insulating film.
(3) In addition to (2) described above, in the transistor, the first thick portion may be constituted of the lower insulating film, and the second thick portion may be constituted of the upper insulating film and the lower insulating film.
(4) In addition to (1) described above, in the transistor, the first insulating film may have a single-layer structure.
(5) In addition to any one of (1) to (4) described above, in the transistor, the first insulating film may include a third thick portion having a film thickness greater than a thickness of the first thick portion, and the third thick portion may be disposed overlapping an outer peripheral end of the semiconductor portion.
(6) In addition to (5) described above, in the transistor, the third thick portion may have the same film thickness as that of the second thick portion.
(7) In addition to any one of (1) to (6) described above, in the transistor, at least three of the first thick portions may be disposed at intervals in the second direction, at least two second thick portions may be disposed at intervals in the second direction, and among the at least three first thick portions, the first thick portion located at other than both ends in the second direction may have a dimension in the second direction which is smaller than a dimension of the two first thick portions located at the both ends in the second direction.
(8) In addition to any of (1) to (7) described above, in the transistor, at least three of the first thick portions may be disposed at intervals in the second direction, at least two of the second thick portions may be disposed at intervals in the second direction, the first electrode may include a first overlapping portion that overlaps the first thick portion located at other than both ends in the second direction among the at least three of the first thick portions, and two second overlapping portions that overlap the two first thick portions located at the both ends in the second direction among the at least three of the first thick portions, and the first overlapping portion may have a dimension which is larger in the first direction than a dimension of the second overlapping portion.
(9) A manufacturing method for a transistor according to the technology described in this specification includes forming a semiconductor film made of a semiconductor material, forming a first resist film made of a photosensitive material on an upper layer side of the semiconductor film, exposing and developing the first resist film, providing a semiconductor portion extending in a first direction by etching the semiconductor film using the first resist film as a mask, forming a first insulating film on an upper layer side of the semiconductor portion, forming a second resist film made of a photosensitive material on an upper layer side of the first insulating film, exposing and developing the second resist film, etching the first insulating film using the second resist film as a mask to provide at least two first thick portions disposed at intervals in a second direction intersecting the first direction so as to overlap the semiconductor portion, and a second thick portion that is disposed to be interposed between the two first thick portions in the second direction at positions overlapping the semiconductor portion and has a film thickness greater than a thickness of the first thick portion, forming a first conductive film on an upper layer side of the first insulating film and patterning the first conductive film to provide a first electrode that extends in the second direction, overlaps a portion of the semiconductor portion, and is disposed to overlap the at least two first thick portions and the second thick portion, and forming a second conductive film on an upper layer side of the first electrode and patterning the second conductive film to provide a second electrode that is disposed to overlap a portion of the semiconductor portion and is connected to the semiconductor portion, and a third electrode that is disposed to overlap a portion of the semiconductor portion at a position spaced apart from a connection position between the second electrode and the semiconductor portion in the first direction and is connected to the semiconductor portion.
(10) In addition to (9) described above, the manufacturing method for the transistor, may further comprise: forming the first resist film made of a negative photosensitive material on the upper layer side of the semiconductor film, exposing the first resist film through a photomask and then developing the first resist film, the photomask having a light shielding region disposed not to overlap a formation area for the semiconductor portion to be formed to block light, at least two transmissive regions disposed at intervals in the second direction so as to overlap the formation area for the semiconductor portion to be formed and transmitting light, and a semi-transmissive region overlapping the formation area for the semiconductor portion to be formed, disposed to be interposed between the at least two transmissive regions in the second direction, and having a light transmittance higher than a light transmittance of the light shielding region and lower than light transmittance of the transmissive region, forming the second resist film made of a positive photosensitive material on the upper layer side of the first insulating film, and exposing the second resist film through the photomask and then developing the second resist film.
According to the technology described in this specification, it is possible to improve a yield.
The disclosure will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
A first embodiment will be described with reference to
The liquid crystal display device 10, as shown in
As shown in
The liquid crystal panel 11 will be described in detail with reference to
As shown in
The driver 12 shown in
The liquid crystal panel 11 according to this embodiment has both a display function of displaying an image and a touch panel function of detecting a position (input position) input by a user based on the displayed image. In the liquid crystal panel 11, a touch panel pattern for exhibiting the touch panel function is integrated (in an in-cell form). The touch panel pattern is a so-called projected capacitive type, and the detection type thereof is a self-capacitance type. As shown in
Next, a configuration of the display region AA in the array substrate 21 will be described with reference to
As shown in
As shown in
Next, various films layered on the glass substrate (substrate) 21GS of the array substrate 21 will be described in detail with reference to
The first metal film, the second metal film, the third metal film and the fourth metal film are each configured as a single layer film made of one type of metal material or configured as a layered film or an alloy made of different types of metal materials, and thus have conductivity and light shielding properties. Specifically, the first metal film is a single layer film made of, for example, Mo (molybdenum) and has a film thickness of, for example, approximately 50 nm. The second metal film is a single layer film made of, for example, Mo (molybdenum) and has a film thickness of, for example, approximately 300 nm. The second metal film is a layered film including, for example, Ti (titanium)/Al (aluminum)/Ti in this order from the upper layer side, and has a film thickness of, for example, approximately 50 nm/approximately 350 nm/approximately 100 nm. The third metal film is a layered film including, for example, Mo/Al/Mo in this order from the upper layer side, and has a film thickness of, for example, approximately 100 nm/approximately 300 nm/approximately 30 nm. The semiconductor film 32 is made of a polysilicon semiconductor material (semiconductor material) having a crystalline substance created by a known method such as laser crystallization, and the polysilicon semiconductor material of the semiconductor film 32, which has a film thickness of, for example, approximately 50 nm, has a higher electron mobility than that of an amorphous silicon semiconductor material or an oxide semiconductor material. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material such as ITO (indium tin oxide), and each has a film thickness of, for example, approximately 60 nm.
The base coat film 31, the gate insulating film 33, the first interlayer insulating film 34, the second interlayer insulating film 36, the third interlayer insulating film 37 and the fourth interlayer insulating film 38 are all made of SiO2 (silicon oxide) or SiNx (silicon nitride) which is a type of an inorganic material (inorganic resin material). Specifically, the base coat film 31 is a layered film made of SiO2/SiNx in this order from the upper layer side and has a film thickness of, for example, approximately 200 nm/approximately 100 nm. The gate insulating film 33 is a layered film made of SiN/SiO2 in this order from the upper layer side and has a film thickness of, for example, approximately 50 nm/approximately 100 nm. The first interlayer insulating film 34 is a layered film made of SiNx/SiO2 in this order from the upper layer side and has a film thickness of, for example, approximately 300 nm/approximately 300 nm. The second interlayer insulating film 36 is a single layer film of SiNx and has a film thickness of, for example, approximately 100 nm. The third interlayer insulating film 37 is a single layer film of SiNx and has a film thickness of, for example, approximately 100 nm. The fourth interlayer insulating film 38 is a single layer film of SiNx and has a film thickness of, for example, approximately 200 nm. The flattening film 35 is made of PMMA (acrylic resin), which is a type of organic material (organic resin material), and has a film thickness in the range of, for example, approximately 1 μm to 3 μm. In other words, the flattening film 35 has a film thickness greater than those of the other insulating films 31, 33, 34, 36, 37, and 38 that are made of inorganic materials.
Next, a cross-sectional configuration of the circuit portion 14 will be described in detail. As shown in
As shown in
As shown in
Next, a cross-sectional configuration of the display region AA will be described in detail. As shown in
As shown in
As shown in
As shown in
The common electrode 28 is constituted of a first transparent electrode film. As shown in
Further, as shown in
Furthermore, in the display region AA, a light shielding portion 39 is provided at a position overlapping at least the entire region of the second semiconductor portion 24D. The light shielding portion 39 is constituted of a first metal film. The light shielding portion 39 is disposed to overlap the second semiconductor portion 24D on the lower layer side via the base coat film 31. Thus, the light shielding portion 39 can shield light that is emitted from the lower layer side from a backlight device to a channel region of the second semiconductor portion 24D. Thereby, it is possible to suppress fluctuations in the characteristics of the second TFT 24 which may occur when light is emitted to the channel region of the second semiconductor portion 24D.
A detailed configuration of the first TFT 15 included in the circuit portion 14 will be described with reference to
As shown in
As described above, when the first semiconductor portion 15D constituting the first TFT 15 is formed wide and the amount of current handled is increased, there is a concern that the transistor characteristics may deteriorate due to self-heating. In the related art, a first semiconductor portion is divided into a plurality of small island regions, and thus the sum of the lengths of outer peripheral ends of the plurality of small island regions became larger, thereby increasing the possibility of defects occurring near the outer peripheral ends (deterioration of voltage resistance and the occurrence of leakage due to minute protrusions).
In this regard, in this embodiment, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D is configured to include a first thick portion 33A and a second thick portion 33B having a film thickness greater than that of the first thick portion 33A, as shown in
According to such a configuration, when a predetermined voltage is applied to the first gate electrode 15A, the channel region 15D1 is generated in the first semiconductor portion 15D. The channel region 15D1 is selectively generated in a portion of the first semiconductor portion 15D which overlaps the first thick portion 33A having a smaller film thickness, and is not generated in a portion which overlaps the second thick portion 33B having a larger film thickness. That is, the channel region 15D1 can be generated in each of three locations spaced apart from each other in the Y-axis direction in the first semiconductor portion 15D, and thus it is possible to reduce self-heating while securing a sufficient amount of current. As in the related art, it is not necessary to divide the first semiconductor portion 15D into a plurality of small island regions, and thus the length of an outer peripheral end 15D2 of the first semiconductor portion 15D is smaller than the sum of the lengths of outer peripheral ends of the plurality of small island regions in the related art. Thereby, the possibility of defects occurring near the outer peripheral end 15D2 of the first semiconductor portion 15D is decreased, and consequently, it is possible to improve a yield.
As shown in
In this embodiment, as shown in
In addition, as shown in
As shown in
As shown in
This embodiment has the above-described structure, and a manufacturing method for the liquid crystal panel 11 will be subsequently described. The manufacturing method for the liquid crystal panel 11 includes a counter substrate manufacturing step (CF substrate manufacturing step) of manufacturing the counter substrate 20, an array substrate manufacturing step of manufacturing the array substrate 21, and a bonding step of bonding the manufactured counter substrate 20 and array substrate 21 together. Hereinafter, among the above steps, the array substrate manufacturing step will be described.
The array substrate manufacturing step includes at least a first step of forming and patterning the first metal film, a second step of forming the base coat film 31, a third step of forming the semiconductor film 32, performing a laser crystallization process, and then patterning the semiconductor film 32, a fourth step of forming and patterning the gate insulating film 33, a fifth step of forming and patterning the second metal film, a sixth step of forming and patterning the first interlayer insulating film 34, a seventh step of forming and patterning the third metal film, an eighth step of forming the flattening film 35, a ninth step of forming the second interlayer insulating film 36, a tenth step of forming and patterning the fourth metal film, an eleventh step of forming the third interlayer insulating film 37, a twelfth step of forming and patterning the first transparent electrode film, a thirteenth step of forming and patterning the fourth interlayer insulating film 38, a fourteenth step of forming and patterning the second transparent electrode film, and a fifteenth step of forming the alignment film and performing an alignment process. Among these, the third and fourth steps will be described in detail below with reference to
The term “patterning” described above means a process of a film based on a general photolithography method. Specifically, the process, that is, the patterning of a film to be processed is performed by forming a photoresist film on the film to be processed, exposing the photoresist film with an exposure device through a photomask having a predetermined pattern, developing the photoresist film, and performing etching through the developed photoresist film.
In the third step, the semiconductor film 32 is formed, and then a laser crystallization process is performed on the semiconductor film 32, thereby making the semiconductor film 32 polycrystalline. Next, as shown in
As shown in
As shown in
In the third step, the first resist film R1 is irradiated with exposure light emitted from the light source of the exposure device through the photomask P configured as described above. The amount of exposure of the first resist film R1 varies for each portion overlapping each of the regions A1 to A3 of the photomask P, as shown in
After the third step is performed as described above, the fourth step is performed. In the fourth step, as shown in
In the fourth step, the second resist film R2 is irradiated with exposure light emitted from the light source of the exposure device through the photomask P having the same exposure pattern as the photomask P used in the first exposure step of the third step. The amount of exposure of the second resist film R2 varies for each portion overlapping each of the regions A1 to A3 of the photomask P, as shown in
The gate insulating film 33 is etched using the second resist film R2 developed in this manner as a mask (second etching step). In this etching, etching conditions (such as the type of etching gas in the case of dry etching, and such as the type of etching solution in the case of wet etching) are set such that an etching rate for the upper insulating film 41 constituting the gate insulating film 33 is high and an etching rate for the lower insulating film 40 is low. When the second etching step is performed, as shown in
As described above, the first TFT (transistor) 15 of this embodiment includes the first semiconductor portion (semiconductor portion) 15D extending in a first direction and made of a semiconductor material, the first gate electrode (first electrode) 15A extending in a second direction intersecting the first direction and disposed to overlap a portion of the first semiconductor portion 15D, the gate insulating film (first insulating film) 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D, the first source electrode (second electrode) 15B disposed to overlap a portion of the first semiconductor portion 15D and connected to the first semiconductor portion 15D, and the first drain electrode (third electrode) 15C disposed to overlap a portion of the first semiconductor portion 15D at a position spaced apart from a connection position between the first source electrode 15B and the first semiconductor portion 15D in the first direction and connected to the first semiconductor portion 15D, the gate insulating film 33 includes the first thick portion 33A and the second thick portion 33B having a film thickness greater than that of the first thick portion 33A, at least two first thick portions 33A are disposed at intervals in the second direction at a position overlapping both the first gate electrode 15A and the first semiconductor portion 15D, and the second thick portion 33B is disposed to be interposed between the two first thick portions 33A in the second direction at a position overlapping both the first gate electrode 15A and the first semiconductor portion 15D.
When a voltage equal to or greater than a threshold voltage of the first TFT 15 is applied to the first gate electrode 15A, the channel region 15D1 is generated in the first semiconductor portion 15D. Thus, electrons move between the first source electrode 15B and the first drain electrode 15C via the channel region 15D1. Here, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D includes the first thick portion 33A and the second thick portion 33B having a film thickness greater than that of the first thick portion 33A. Thus, the channel region 15D1 is selectively generated in a portion of the first semiconductor portion 15D which overlaps the first thick portion 33A, and is not generated in a portion overlapping the second thick portion 33B. That is, the channel region 15D1 can be generated in each of at least two locations in the first semiconductor portion 15D which are spaced apart from each other in the second direction, and thus it is possible to reduce self-heating while securing a sufficient amount of current. As in the related art, it is not necessary to divide the first semiconductor portion 15D into a plurality of small island regions, and thus the length of an outer peripheral end 15D2 of the first semiconductor portion 15D is smaller than the sum of the lengths of outer peripheral ends of the plurality of small island regions in the related art. Thereby, the possibility of defects occurring near the outer peripheral end 15D2 of the first semiconductor portion 15D is decreased, and consequently, it is possible to improve a yield.
Furthermore, the gate insulating film 33 has a layered structure of the lower insulating film 40 disposed on the upper layer side of the first semiconductor portion 15D, and the upper insulating film 41 disposed on the upper layer side of the lower insulating film 40 and made of a material different from that of the lower insulating film 40. In this manner, the gate insulating film 33 is formed to have a layered structure of the lower insulating film 40 and the upper insulating film 41, which are made of different materials, and thus the first thick portion 33A and the second thick portion 33B, which have different film thicknesses, can be easily provided.
In addition, the first thick portion 33A is made of a lower insulating film 40, and the second thick portion 33B is made of an upper insulating film 41 and a lower insulating film 40. During manufacture, the lower insulating film 40 and the upper insulating film 41 are formed in sequence, and then the upper insulating film 41 is selectively removed, making it possible to easily provide the first thick portion 33A made of the lower insulating film 40 and the second thick portion 33B made of the lower insulating film 40 and the upper insulating film 41.
In addition, the gate insulating film 33 includes the third thick portion 33C having a film thickness greater than that of the first thick portion 33A, and the third thick portion 33C is disposed to overlap the outer peripheral end 15D2 of the first semiconductor portion 15D. The outer peripheral end 15D2 of the first semiconductor portion 15D is covered by the third thick portion 33C having a film thickness greater than that of the first thick portion 33A from the upper layer side, further reducing the possibility of defects occurring near the outer peripheral end 15D2 of the first semiconductor portion 15D. Thereby, it is possible to further improve a yield.
In addition, the third thick portion 33C has the same film thickness as that of the second thick portion 33B. It makes it easier to perform manufacturing than when all of the first thick portion 33A, the second thick portion 33B, and the third thick portion 33C have different film thicknesses.
Further, in the manufacturing method for the first TFT 15 according to this embodiment, the semiconductor film 32 made of a semiconductor material is formed, the first resist film R1 made of a photosensitive material is formed on the upper layer side of the semiconductor film 32, the first resist film R1 is exposed and developed, and the semiconductor film 32 is etched using the first resist film R1 as a mask, thereby providing the first semiconductor portion 15D extending in a first direction. The gate insulating film 33 is formed on the upper layer side of the first semiconductor portion 15D, the second resist film R2 made of a photosensitive material is formed on the upper layer side of the gate insulating film 33, the second resist film R2 is exposed and developed, and the gate insulating film 33 is etched using the second resist film R2 as a mask, thereby forming at least two first thick portions 33A that overlap the first semiconductor portion 15D and are disposed at intervals in a second direction intersecting the first direction, and the second thick portion 33B that is disposed to be interposed between the two first thick portion 33A in the second direction at a position overlapping the first semiconductor portion 15D and has a film thickness greater than that of the first thick portion 33A. The first conductive film is formed on the upper layer side of the gate insulating film 33 and is patterned, thereby providing the first gate electrode 15A disposed to extend in the second direction and overlap a portion of the first semiconductor portion 15D, and disposed to overlap at least the two first thick portions 33A and the second thick portion 33B. The second conductive film is formed on the upper layer side of the first gate electrode 15A and is patterned, thereby providing the first source electrode 15B disposed to overlap a portion of the first semiconductor portion 15D and connected to the first semiconductor portion 15D, and the first drain electrode 15C that is disposed to overlap a portion of the first semiconductor portion 15D at a position spaced apart from a connection position between the first source electrode 15B and the first semiconductor portion 15D in the first direction, and is connected to the first semiconductor portion 15D.
After the semiconductor film 32 and the first resist film R1 are sequentially formed, the first resist film R1 is exposed and developed. When the semiconductor film 32 is etched through the patterned first resist film R1, the first semiconductor portion 15D is provided. When the gate insulating film 33 and the second resist film R2 are sequentially formed on the upper layer side of the first semiconductor portion 15D, the second resist film R2 is exposed and developed. When the gate insulating film 33 is etched through the patterned second resist film R2, the first thick portion 33A and the second thick portion 33B are provided. The first conductive film is formed on the upper layer side of the gate insulating film 33 and is patterned, thereby providing the first gate electrode 15A. The second conductive film is formed on the upper layer side of the first gate electrode 15A and is patterned, thereby providing the first source electrode 15B and the first drain electrode 15C.
When a voltage equal to or greater than a threshold voltage of the first TFT 15 manufactured in this manner is applied to the first gate electrode 15A, the channel region 15D1 is generated in the first semiconductor portion 15D. Thus, electrons move between the first source electrode 15B and the first drain electrode 15C via the channel region 15D1. Here, the gate insulating film 33 interposed between the first gate electrode 15A and the first semiconductor portion 15D includes the first thick portion 33A and the second thick portion 33B having a film thickness greater than that of the first thick portion 33A. Thus, the channel region 15D1 is selectively generated in a portion of the first semiconductor portion 15D which overlaps the first thick portion 33A, and is not generated in a portion overlapping the second thick portion 33B. That is, the channel region 15D1 can be generated in each of at least two locations in the first semiconductor portion 15D which are spaced apart from each other in the second direction, and thus it is possible to reduce self-heating while securing a sufficient amount of current. As in the related art, it is not necessary to divide the first semiconductor portion 15D into a plurality of small island regions, and thus the length of an outer peripheral end 15D2 of the first semiconductor portion 15D is smaller than the sum of the lengths of outer peripheral ends of the plurality of small island regions in the related art. Thereby, the possibility of defects occurring near the outer peripheral end 15D2 of the first semiconductor portion 15D is decreased, and consequently, it is possible to improve a yield.
In addition, the first resist film R1 made of a negative photosensitive material is formed on the upper layer side of the semiconductor film 32, the first resist film R1 is exposed to light through the photomask P having the light shielding region A1 that is disposed not to overlap a formation area for the first semiconductor portion 15D to be formed and blocks light, at least two transmissive regions A2 that overlap the formation area for the first semiconductor portion 15D to be formed, are disposed at intervals in the second direction, and transmit light, and the semi-transmissive region A3 that overlaps the formation area for the first semiconductor portion 15D to be formed, are disposed to be interposed between the two transmissive regions A2 in the second direction, and has a light transmittance higher than a light transmittance of the light shielding region A1 and lower than that of the transmissive region A2, the first resist film R1 is then developed, the second resist film R2 made of a positive photosensitive material is formed on the upper layer side of the gate insulating film 33, and the second resist film R2 is exposed to light through the photomask P and then developed.
The first resist film R1 formed on the upper layer side of the semiconductor film 32 is exposed through the photomask P. The amount of exposure of the first resist film R1 varies for each portion overlapping each region of the photomask P. That is, in the first resist film R1, the portion overlapping the light shielding region A1 is hardly exposed, the portion overlapping the transmissive region A2 is sufficiently exposed, and the portion overlapping the semi-transmissive region A3 is exposed with a smaller amount of light than the portion overlapping the transmissive region A2. The first resist film R1 is made of a negative photosensitive material, and thus, when the first resist film R1 is developed, the unexposed portion (the portion overlapping the light shielding region A1) is removed, the exposed portion (the portion overlapping the transmissive region A2) remains, and the semi-exposed portion (the portion overlapping the semi-transmissive region A3) remains with a film thickness corresponding to the amount of exposure. The semiconductor film 32 is etched using the developed first resist film R1 as a mask, thereby providing the first semiconductor portion 15D located in an area overlapping the transmissive region A2 and the semi-transmissive region A3 of the photomask P.
The second resist film R2 formed on the upper layer side of the gate insulating film 33 is exposed through the photomask P having the same exposure pattern as that of the photomask P used to expose the first resist film R1. The amount of exposure of the second resist film R2 varies for each portion overlapping each of the regions A1 to A3 of the photomask P. That is, in the second resist film R2, the portion overlapping the light shielding region A1 is hardly exposed, the portion overlapping the transmissive region A2 is sufficiently exposed, and the portion overlapping the semi-transmissive region A3 is exposed with a smaller amount of light than the portion overlapping the transmissive region A2. The second resist film R2 is made of a positive photosensitive material, and thus, when the second resist film R2 is developed, the exposed portion (the portion overlapping the transmissive region A2) is removed, the unexposed portion (the portion overlapping the light shielding region A1) remains, and the semi-exposed portion (the portion overlapping the semi-transmissive region A3) remains with a film thickness corresponding to the amount of exposure. The gate insulating film 33 is etched using the developed second resist film R2 as a mask, thereby providing the first thick portion 33A located in an area overlapping the transmissive region A2 of the photomask P, and the second thick portion 33B located in an area overlapping the semi-transmissive region A3.
As described above, the photomask P having the same exposure pattern can be used in the step of exposing the first resist film R1 and the step of exposing the second resist film R2, which is suitable for reducing costs associated with the equipment required for manufacturing.
A second embodiment will be described with reference to
The gate insulating film 133 in this embodiment has a single-layer structure as shown in
As described above, according to this embodiment, the gate insulating film 133 has a single-layer structure. Compared to a case where the gate insulating film has a layered structure including a plurality of insulating films, a film formation process required for manufacturing can be reduced.
A third embodiment will be described with reference to
As shown in
Here, the center-side portion of the first semiconductor portion 215D in the Y-axis direction dissipates less heat than the end-side portions in the Y-axis direction, and thus heat tends to be accumulated. For this reason, there is a concern that a large temperature difference will occur between the center-side portion and the end-side portion of the first semiconductor portion 215D in the Y-axis direction. In this regard, the width dimension W3 of the center-side first thick portion 233A2 located in the center in the Y-axis direction is smaller than the width dimensions W1 and W2 of the two end-side first thick portions 233A1 located at both ends in the Y-axis direction, and thus a center-side channel region (the other channel region) 215D1B generated in the center-side portion in the Y-axis direction of the first semiconductor portion 215D has a width dimension (dimension in the Y-axis direction (second direction)) smaller than those of the two end-side channel regions (one channel region) 215D1A generated in the both end-side portions in the Y-axis direction. Thus, the amount of current flowing through the center-side channel region 215D1B is smaller than the amount of current flowing through each of the two end-side channel regions 215D1A, and thus self-heating occurring in the center-side channel region 215D1B is also less than self-heating occurring in each of the two end-side channel regions 215D1A. Thereby, it is possible to reduce a temperature difference that may occur between the center-side portion in the Y-axis direction and the end-side portions in the Y-axis direction in the first semiconductor portion 215D.
As described above, according to this embodiment, at least three first thick portions 233A are disposed at intervals in the second direction, at least two second thick portions 233B are arranged at intervals in the second direction, and the first thick portions 233A located at other than both ends in the second direction, among the at least three first thick portions 233A, have dimensions in the second direction which are smaller than those of the two first thick portions 233A located at both ends in the second direction. According to such a configuration, a channel region 215D1 is selectively generated in each of the portions of the first semiconductor portion 215D which overlap the at least three first thick portions 233A. The center-side portion of the first semiconductor portion 215D in the second direction dissipates less heat than the end-side portions in the second direction, and thus heat tends to be accumulated. In this regard, the first thick portions 233A located at other than both ends in the second direction have a dimension in the second direction which is smaller than those of the two first thick portions 233A located at both ends in the second direction, and thus the channel region 215D1 generated in the center-side portion of the first semiconductor portion 215D in the second direction has a dimension in the second direction which is smaller than those of the two channel regions 215D1 generated at both end-side portions in the second direction. Thus, the amount of current flowing through the channel region 215D1 generated in the center-side portion of the first semiconductor portion 215D in the second direction is reduced, and self-heating is reduced. Thereby, it is possible to reduce a temperature difference that may occur between the center-side portion in the second direction and the end-side portions in the second direction in the first semiconductor portion 215D.
A fourth embodiment will be described with reference to
As shown in
Here, a center-side portion of the first semiconductor portion 315D in the Y-axis direction dissipates less heat than the end-side portions in the Y-axis direction, and thus heat tends to be accumulated. Thus, there is a concern that a large temperature difference will occur between the center-side portion and the end-side portion of the first semiconductor portion 315D in the Y-axis direction. In this regard, the width dimension W6 of the first overlapping portion 42 overlapping the center-side first thick portion 333A2 of the first gate electrode 315A is larger than the width dimensions W4 and W5 of the two second overlapping portions 43 overlapping the two end-side first thick portions 333A1 of the first gate electrode 315A, and thus a center-side channel region 315D1B generated in the center-side portion in the Y-axis direction in the first semiconductor portion 315D has a length dimension (dimension in the X-axis direction (first direction)) which is larger than those of two end-side channel regions 315D1A generated in the both end-side portions in the Y-axis direction. Thus, the amount of current flowing through the center-side channel region 315D1B is smaller than the amount of current flowing through each of the two end-side channel regions 315D1A, and thus self-heating occurring in the center-side channel region 315D1B is also less than self-heating occurring in each of the two end-side channel regions 315D1A. Thereby, it is possible to reduce a temperature difference that may occur between the center-side portion in the Y-axis direction and the end-side portions in the Y-axis direction in the first semiconductor portion 315D.
As described above, according to this embodiment, at least three first thick portions 333A are disposed at intervals in the second direction, at least two second thick portions 333B are disposed at intervals in the second direction, and the first gate electrode 315A includes a first overlapping portion 42 which overlaps the first thick portions 333A located at other than both ends in the second direction among the at least three first thick portions 333A, and two second overlapping portions 43 that overlap the two first thick portions 333A located at both ends in the second direction among the at least three first thick portions 333A, and the first overlapping portion 42 has a dimension in the first direction which is larger than that of the second overlapping portion 43. According to such a configuration, the channel region 315D1 is selectively generated in each of the portions of the first semiconductor portion 315D which overlap the at least three first thick portions 333A. The center-side portion of the first semiconductor portion 315D in the second direction dissipates less heat than the end-side portions in the second direction, and thus heat tends to be accumulated. In this regard, the first overlapping portion 42 of the first gate electrode 315A has a dimension in the first direction which is larger than that of the second overlapping portion 43, and thus the channel region 315D1 generated in the center-side portion of the first semiconductor portion 315D in the second direction has a dimension in the first direction which is larger than those of the two channel regions 315D1 generated at both end-side portions in the second direction. Thus, the amount of current flowing through the channel region 315D1 generated in the center-side portion of the first semiconductor portion 315D in the second direction is reduced, and self-heating is reduced. Thereby, it is possible to reduce a temperature difference that may occur between the center-side portion in the second direction and the end-side portions in the second direction in the first semiconductor portion 315D.
The technology described in the present specification is not limited to the embodiments described above and shown in the drawings, and the following embodiments, for example, are also included within the technical scope.
(1) The formation ranges for the first thick portions 33A, 133A, 233A, and 333A in a plan view can be changed as appropriate to areas other than those shown in the drawings. For example, the formation ranges for the first thick portions 33A, 133A, 233A, and 333A may be limited to areas which overlap the first gate electrodes 15A and 315A.
(2) In the configurations described in the first, third and fourth embodiments, the first thick portion 33A, 233A, and 333A may partially include the upper insulating film 41 in addition to the lower insulating film 40. That is, when etching is performed in the fourth step, an upper layer portion of the upper insulating film 41 may be removed, and a lower layer portion of the upper insulating film 41 may be left.
(3) Regarding each of the first thick portions 33A, 133A, 233A, and 333A, two or four or more first thick portions may be provided lined up at intervals in the Y-axis direction.
(4) In (3) described above, when the configuration in which four or more first thick portions of each of the first thick portions 33A, 133A, 233A, and 333A are lined up is applied to the configuration described in the third and fourth embodiments, a configuration in which a plurality of center-side first thick portions of each of the center-side first thick portions 233A2 and 333A2 are provided is obtained. In this case, the width dimension of each of the plurality of center-side first thick portions 233A2 and 333A2 may be made smaller than the width dimension of each of the end-side first thick portions 233A1 and 333A1. Furthermore, when there are three or more center-side first thick portions of each of the first thick portions 233A2 and 333A2, it is also possible to make the width dimension 233A2 and 333A2 located on the center side smaller than the width dimension of each of the center-side first thick portions 233A2 and 333A2 located on the end side for the three or more center-side first thick portions 233A2 and 333A2.
(5) In (3) described above, when the configuration in which four or more first thick portions of each of the first thick portions 33A, 133A, 233A, and 333A are lined up is applied to the configuration described in the fourth embodiment, a configuration in which a plurality of first overlapping portions 42 are provided in the first gate electrode 315A is obtained. In this case, the width dimension of each of the plurality of first overlapping portions 42 may be made larger than the width dimension of the second overlapping portion 43. Furthermore, when there are three or more first overlapping portions 42, it is also possible to make the width dimension of the first overlapping portion 42 located on the center side larger than the width dimension of the first overlapping portion 42 located on the end side for the three or more first overlapping portions 42.
(6) The configuration described in the third embodiment may be combined with the configuration described in the second embodiment.
(7) The configuration described in the fourth embodiment may be combined with the configurations described in the first and second embodiments.
(8) Specific materials used for the films on the array substrate 21 and specific numerical values of film thicknesses of the films can be changed as appropriate to those not mentioned above.
(9) The first gate electrodes 15A and 315A may be configured to intersect the first semiconductor portions 15D, 215D and 315D at an angle other than 90°.
(10) Specific planar shapes of the first gate electrodes 15A and 315A and the first semiconductor portions 15D, 215D, and 315D can be changed as appropriate to those not shown in the drawings. When the first semiconductor portions 15D, 215D, and 315D include a portion extending in the X-axis direction, it may be bent midway. When the first gate electrodes 15A and 315A include a portion extending in the Y-axis direction, it may be bent midway.
(11) In each of the exposure steps included in the third and fourth steps, a gray-tone mask may be used as the photomask P in addition to the half-tone mask.
(12) It is also possible to make the exposure pattern of the photomask P used in the third step different from that of the photomask P used in the fourth step.
(13) Instead of the driver 12, a source shared driving (SSD) circuit or the like may be monolithically provided on the array substrate 21. In this case, circuit elements of the SSD circuit may also include the first TFT 15.
(14) The driver 12 may be attached to the flexible substrate 13.
(15) Instead of the circuit portion 14, a gate driver may be attached to the array substrate 21.
(16) It is also possible to reverse the order of layering the semiconductor film 32 and the second metal film. That is, in the first TFT 15, the gate insulating films 33, 133, 233, and 333 may be located on the upper layer sides of the first gate electrode 15A and 315A constituted of the second metal film, and the first semiconductor portions 15D, 215D, and 315D constituted of the semiconductor film 32 may be located on the upper layer sides of the gate insulating films 33, 133, 233, and 333. In this case, the first TFT 15 is a bottom gate type. The semiconductor film 32 may also be constituted of an amorphous silicon thin film or an oxide semiconductor thin film. The second TFT 24 is also a bottom gate type.
(17) The first TFT 15 and the second TFT 24 may be of a double gate type or the like other than a top gate type or a bottom gate type.
(18) In the pixel electrode 25 and the common electrode 28, an “upper electrode” which is an electrode located on the upper layer side may be the common electrode 28, and a “lower electrode” which is an electrode located on the lower layer side may be the pixel electrode 25. In this case, a slit is provided in the common electrode 28 which is the “upper electrode”.
(19) The touch panel pattern may be a mutual capacitance type other than a self-capacitance type.
(20) The liquid crystal panel 11 may not have a touch panel pattern (touch panel function). In this case, the common electrode 28 has a non-divided structure, the touch electrode 29 is not formed, and the touch wiring line 30 (third metal film) is not formed.
(21) The color filter 29 may be provided on the array substrate 21. That is, the liquid crystal panel 11 may have a color filter on array (COA) structure.
(22) The number of colors of the color filter 29 may be four or more. The color filter 29 to be added may be a yellow color filter exhibiting yellow, a transparent color filter transmitting light of a full wavelength region, or the like.
(23) A display mode of the liquid crystal panel 11 may be a VA mode, an IPS mode, or the like other than an FFS mode.
(24) The liquid crystal panel 11 may be a reflective type or a semi-transmissive type other than a transmissive type. When the liquid crystal panel 11 is a reflective type, the backlight device can be omitted.
(25) A display panel other than the liquid crystal panel 11 (such as an organic EL display panel) may be used.
(26) In addition to the head mounted display (HMD) 10, the present disclosure can also be applied to devices such as head-up displays and projectors that use lenses or the like to enlarge and display an image displayed on the liquid crystal panel 11. The present disclosure can be also applied to a display device that does not have an enlarged display function (a television receiver, a tablet terminal, a smartphone, or the like).
While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, Thus, is to be determined solely by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-174163 | Oct 2023 | JP | national |
