Patent Application
20190229725
Transistors can be used as programmable, adjustable resistors. However, the response of the transistor in the ohmic region can be non-linear due to various voltages applied to terminals of the transistor.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
Field-effect transistors (FETs) can be used as adjustable resistors where a control voltage applied to the gate node of the can control the resistance between the drain node of the FET and the source node of the FET. However, for a given control voltage present at the gate of the FET, the resistance can change because the voltage between the source and drain can also affect the resistance of the FET. For example, current (Id) through a FET can be given by,
where, μ is the mobility, Cox is the capacitance per unit area of the gate oxide, W is the width of the gate, L is the length of the gate, vg is the voltage applied at the gate, vt is the threshold voltage of the FET, vd is the voltage at the drain node of the FET, vs is the voltage at the source node of the FET, and vds id the voltage across the drain and source nodes. In operation, vg can receive a control voltage (Vctl) to turn the FET on and off and to control the resistance. It has been recognized, that if the voltage at the gate also include an average of the voltages applied to the drain and source nodes with proper polarity, such that,
the relationship of the resistance of the FET and the control voltage can be quite stable even with changing voltages at the drain and source nodes. For example, Substituting Eq. 2 into Eq. 1, the current through the FET can be,
which can provide a very linear relationship between Vds and Id, and can make the resistance across the FET independent of the voltages applied to the drain and source nodes of the FET. In certain examples, where the FET is operating at high frequencies, the average of the voltages applied to the drain and source nodes,
can be added to the gate node, along with the control voltage (Vctl), by connecting the control voltage to the gate node with an isolation resistor (Riso). In such an arrangement, an isolation resistor can work in cooperation with the parasitic capacitances (Cgs, Cgd) between the source and gate (Cgs), and between the drain and the gate (Cgd), to apply an average of the voltages present at the drain and the source nodes to the gate node. Unfortunately, the beneficial effect deteriorates as the frequency of operation falls below the corner frequency (fc) defined by the parasitic capacitances and the isolation resistor, where,
Two resistors (Ravg) can couple the source node and the drain node to a non-inverting input of the amplifier. A gain resistor (Rg) can couple an inverting input of the amplifier with the output of the amplifier. An isolation resistor (Riso) can couple the output of the amplifier with the gate node of the FET. The control signal (CNTL) can be received at the inverting input of the amplifier. In certain example, a source of the control signal can be a current source 109, such as one that provides a signal with a magnitude of VCNTL/Rg, where VCNTL is a control voltage to be applied to the gate node of the FET. The speed of the amplifier can be higher than the corner frequency discussed above to maintain the linearizing compensation up to the corner frequency.
In some examples, the signal provided by the signal source can be an analog signal having one or more frequency components and that can vary the voltage provided on the source and drain nodes of the FET 101. As discussed above, the voltages at the source and drain nodes of the FET 101 can affect the on-resistance of the FET for a given voltage at the gate node. If the on-resistance of the FET changes when the FET is coupling the signal source to the input, distortion can be introduced to the signal provided by the signal source. As a result, the signal received by the input circuit 103 may not be a true representation of the signal generated by the signal source. The compensation provided by applying the average of the voltages at the drain and source nodes of the FET 101 can stabilize the resistance of the FET 101 for a given control signal and can help provide a true representation of the signal provided by the signal source 102 to the input circuit 103.
In some situations, for example when the signal generated by the signal source is a high frequency signal, parasitic capacitances, in cooperation with an isolation resistance, can apply an average voltage of the voltages applied to the source and drain nodes to the gate node. At high frequency, the resistance of the FET can be stabilized for a given control signal applied to the gate, and can provide a substantially linear relationship between the control signal and the resistance of the FET for a range of values of the control signal. Below a corner frequency defined by the parasitic capacitances and the isolation resistor (Riso), the effects of the voltages at the source and drain nodes of the FET deteriorate the stability of the resistance of the FET 101 as voltage changes at the drain and source nodes of the FET 101. Such stabilization can assist in making the resistance of the FET 101 independent of the signal applied to the drain and source nodes of the FET 101 such that the signal received at the input circuit 103, or input device, is a linear representation of the signal received from the signal source 102.
The second amplifier can be similarly employed to assist the stabilization the resistance of the FET between the drain and source nodes via the backgate (b). In certain examples, the output of the second amplifier can be coupled to the backgate (b) via a second isolation resistor (R2iso). The set of two resistors (Rang) can couple the source node and the drain node to a non-inverting input of the second amplifier. The second amplifier can be arranged in a voltage follower mode to apply the average of the voltages present at the drain and source nodes of the FET to the backgate (b). Applying an average of the voltages at the drain and source nodes of the FET 201 to the gate (g) and backgate (b) of the FET 201 can assist in making the resistance of the FET 201 independent of the signal applied to the drain and source nodes such that the signal received at the input circuit 203, or input device, is an improved linear representation of the signal received from the signal source 202.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples,” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.
In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” Also, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term are still deemed to fall within the scope of subject matter discussed. Moreover, such as may appear in a claim, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of a claim. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. The following aspects are hereby incorporated into the Detailed Description as examples or embodiments, with each aspect standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations.
