"An Electrical Optimizer that Considers Physical Layout" by F. W. Obermeier et al., 25th ACM/IEEE Design Automation Conference, 1988, pp. 453-459. |
"Synchronous Path Analysis in MOS Circuit Simulator," IEEE Proc. 19th Design Automation Conf., V. D. Agrawal, 1982, pp. 629-635. |
"Analytical Power/Timing Optimization Technique for Digital System," IEEE Proc. 14th Design Automation Conf., A. E. Ruehli, Jun. 1977, pp. 142-146. |
"Optimization of Digital MOS VLSI Circuits," Proc. Chapel Hill Conf. on VLSI, M. D. Matson, University of North Carolina, May 1985, pp. 109-126. |
"Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits," 1984 Conf. on Advanced Research in VLSI, T. Lin et al., MIT Jan. 1984, pp. 93-99. |
"Electrical Optimization of PLAs," IEEE 22nd Design Automation Conf., K. S. Hedlund, 1985, pp. 681-687. |
"Switch-Level Delay Models for Digital MOS VLSI," IEEE 21st Design Automation Conf., J. K. Ousterhout, 1984, pp. 542-548. |
"Timing Analysis for nMOS VLSI," IEEE 20th Design Automation Conf., N. P. Jouppi, 1983, pp. 411-418. |
"Signal Delay in RC Tree Networks," IEEE Transactions on Computer Aided Design, J. Rubinstein, Jul. 1983, vol. CAD-2, No. 3, pp. 202-210. |