1. Field of the Invention
The invention relates to a voltage-controlled oscillator, and more specifically, to a transistor voltage-controlled oscillator.
2. Prior Art
Design of a voltage-controlled oscillator has always been the design focus in the field of wireless communications circuit design. In the wireless RF circuit, the voltage-controlled oscillator plays an extremely crucial role in the modulation/demodulation process of the RF front-end circuit. Also, as a voltage-controlled oscillator often comprises quite a number of capacitors, inductors, transistors and other active or passive components, therefore the voltage-controlled oscillating circuit has always been the part in the wireless RF circuit that takes up the largest area and consumes the most power.
Firstly, power consumption of the voltage-controlled oscillating circuit is discussed. Inductors and other passive components included in the circuit shall not consume any signal power under ideal condition, and parasitic resistance does not exist in an ideal equivalent circuit, therefore an ideal inductor shall store and release the energy of the signal without loss in the form of electromagnetic field. Only under practical circumstances, when passive components are integrated into silicon chips in particular, can the effect of parasitic resistance appear significantly in passive components and the silicon substrate.
The parasitic capacitance refers to a very small, undesired capacitance existing between conducting wires and the silicon substrate of an integrated circuit. Under the condition of low oscillating frequency, the effect of parasitic capacitance is not obvious and therefore can be ignored. As the oscillating frequency is increased, the effect of parasitic capacitance will gradually become more apparent, wherein the frequency suppression effect shall be carefully taken into consideration.
In order to describe the effect of parasitic resistance on the power consumed by passive components, a quality factor Q, representing the degree of which the signal power is consumed by the components, is defined. The quality factor Q is defined as the ratio of the maximum stored energy in an ideal inductor to the energy consumed by the parasitic resistance during every signal cycle. In other words, the greater is the Q-factor, the lesser the impact of the parasitic resistance on the passive component. The Q-factor of an ideal component shall approach infinity.
When passive components are integrated into a silicon chip, the parasitic capacitance often appears at the border where conducting wires and silicon substrate are connected. As the area of the contact between the conducting wire and the substrate is increased, the parasitic capacitance effect shall also become more obvious. As shown in
As described above, even though integrating chip inductor on the silicon substrate leads to substrate parasitic resistance that attenuates the signal, thereby causing the problem of low Q-factor, most researches still focus on integrating inductors into the chip. The primary reason is that if passive components such as inductor can be integrated into a single chip, then the external component count can be significantly reduced, thus lowering the cost and the die size.
Hence, it has become an urgent issue to designers in the voltage-controlled oscillator to devise a way to design a voltage-controlled oscillating circuit that not only enables integration of multiple inductors into a single chip such that the die size is greatly reduced but also lowers the energy consumed by the parasitic resistance present in the silicon substrate during the process of integrating inductors into a silicon chip, thereby avoiding the problem of low Q-factor.
In view of the above disadvantages of the conventional technique, it is a primary objective of the present invention to provide a transistor voltage-controlled oscillator that allows an integration of multiple inductors into a single chip, thereby reducing the die size significantly.
Another objective of the invention is to provide a transistor voltage-controlled oscillator that allows integrating inductors into the silicon chip during the chip process, thereby lowering the power consumption due to parasitic resistance of the silicon substrate, such that the problem of low Q-factor is avoided.
In order to achieve the aforementioned objectives, the present invention provides a transistor voltage-controlled oscillator. The transistor voltage-controlled oscillator in the present invention includes at least: a cross-coupled LC-tank transistor voltage-controlled oscillating circuit having a first transistor with a first gate terminal, a first source terminal and a first drain terminal, and a second transistor with a second gate terminal, a second source terminal and a second drain terminal; a first transformer inductor used as a coupling inductor in the cross-coupled LC-tank transistor voltage-controlled oscillating circuit includes a first induction coil and a second induction coil, further the first induction coil is connected to the first drain terminal, and the second induction coil is connected to the first source terminal; and a second transformer inductor used as another coupling inductor in the cross-coupled LC-tank transistor voltage-controlled oscillating circuit includes a third induction coil and a fourth induction coil, further the third induction coil is connected to the second drain terminal and the fourth induction coil is connected to the second source terminal.
In comparison to the conventional technique, the transistor voltage-controlled oscillator in the present invention includes a first transformer inductor having a first induction coil and a second induction coil, further the first induction coil is connected to the first drain terminal, the second induction coil is connected to the first source terminal; and a second transformer inductor including a third induction coil and a fourth induction coil, further the third induction coil is connected to the second drain terminal, the fourth induction coil is connected to the second source terminal. The two above-mentioned transformer inductors are used as the coupling inductors in the cross-coupled LC-tank transistor voltage-controlled oscillating circuit thus, the area taken up by the inductor of the transistor voltage-controlled oscillator can be greatly reduced. As reducing the inductor area lowers the parasitic capacitance present between the inductor and the silicon substrate, a significant reduction in the power consumption can be achieved, which in turn increases the Q-factor of the inductor.
a is a block diagram of a planar transformer of a transistor voltage-controlled oscillator in the present invention;
b is an equivalent circuit diagram of a planar transformer of a transistor voltage-controlled oscillator in the present invention;
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.
The following embodiments further illustrate the points of the present invention in detail, however the invention is not limited to any points.
Referring to
Moreover the third induction coil 241 is connected to the second drain terminal 223, the fourth induction coil 242 is connected to the second source terminal 222; and the first induction coil 231 and the third induction coil 241 are connected to a working voltage supply 26; the second induction coil 232 and the fourth induction coil 242 are connected to ground.
As shown in
Regarding the planar transformer technique replacing the conventional inductors in the voltage-controlled oscillator,
Referring to
Also, the third transistor 251 includes a third gate terminal 2511, a third source terminal 2512, a third drain terminal 2513 and a third substrate 2514, and the fourth transistor 252 includes a fourth gate terminal 2521, a fourth source terminal 2522, a fourth drain terminal 2523 and a fourth substrate 2524. The third source terminal 2512 is coupled to the third drain terminal 2513, the fourth source terminal 2522 is coupled to the fourth drain terminal 2523. Furthermore the third substrate 2514 is coupled to the first drain terminal 213, and the fourth substrate 2524 is coupled to the second drain terminal 223. In addition, the third gate terminal 2511 and the fourth gate terminal 2521 are coupled to a control voltage source 27. The control voltage source 27 serves the purpose of adjusting the capacitance of the NMOS transistor variable capacitor set 250.
Referring to
The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.
Number | Date | Country | Kind |
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097101742 | Jan 2008 | TW | national |