Claims
- 1. A content addressable memory apparatus comprising:
- a plurality of tag registers;
- a plurality of data registers, each data register having an output enable for enabling contents of the data register onto an output bus;
- means for loading information into a first one of the tag registers independently of contents of a second one of the tag registers;
- a plurality of comparators, each of the comparators corresponding with a respective one of the tag registers and generating a match signal indicative of whether contents of the respective one of the tag registers matches an incoming tag signal;
- first detection means for activating a multiple match signal when at least a given number of the comparators generate match signals indicating contents of respective ones of the tag registers match the incoming tag signal, the given number being greater than one; and
- means for coupling each of the match signals to a respective one of the output enables, the means for coupling to all of the output enables being inhibited if the multiple match signal is active.
- 2. The content addressable memory apparatus according to claim 1, wherein the first detection means operates in an analog fashion, and wherein the given number is at least equal to a number needed to exceed a threshold of electrical noise.
- 3. The content addressable memory apparatus according to claim 1, further comprising a second detection means for activating a first signal if a first system condition is present, a probability that contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present; the means for coupling to all of the output enables being further inhibited if the first signal is active.
- 4. The content addressable memory apparatus according to claim 1, further comprising a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required; the means for coupling to all of the output enables being further inhibited if the second signal is active.
- 5. The content addressable memory apparatus according to claim 1, further comprising:
- a second detection means for activating a first signal if a first system condition is present, a probability that the contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present; and
- a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;
- the means for coupling to all of the output enables being further inhibited if the first signal is active or the second signal is active.
- 6. A content addressable memory apparatus comprising:
- a plurality of tag registers;
- a plurality of data registers, each data register having an output enable for enabling contents of the data register onto an output bus;
- means for loading information into a first one of the tag registers independently of contents of a second one of the rag registers;
- a plurality of comparators, each of the comparators corresponding with a respective one of the tag registers and generating a match signal indicative of whether contents of the respective one of the tag registers matches an incoming tag signal;
- first detection means for activating a multiple match signal when at least a given number of the comparators generate match signals indicating contents of respective ones of the tag registers match the incoming tag signal, the given number being greater than one; and
- means for coupling each of the match signals to a respective one of the output enables, the means for coupling to all of the output enables except a preselected one of the output enables being inhibited if the multiple match signal is active.
- 7. The content addressable memory apparatus according to claim 6, wherein the first detection means operates in an analog fashion, and wherein the given number is at least equal to a number needed to exceed a threshold of electrical noise.
- 8. The content addressable memory apparatus according to claim 6, further comprising a second detection means for activating a first signal if a first system condition is present, a probability that contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the system condition is not present; the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the first signal is active.
- 9. The content addressable memory apparatus according to claim 6, further comprising a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required; the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the second signal is active.
- 10. The content addressable memory apparatus according to claim 6, further comprising:
- a second detection means for activating a first signal if a first system condition is present, a probability that the contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present; and
- a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;
- the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the first signal is active or the second signal is active.
Parent Case Info
This application is a continuation of Ser. No. 07/366,344, filed on Jun. 14, 1989 now U.S. Pat. No. 5,237,671.
US Referenced Citations (15)
Foreign Referenced Citations (1)
Number |
Date |
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0127008 |
May 1984 |
EPX |
Continuations (1)
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Number |
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Parent |
366344 |
Jun 1989 |
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