Transmission of pulse power and data over a wire pair

Abstract

In one embodiment, a method includes applying Forward Error Correction (FEC) to data at power sourcing equipment, transmitting the data and pulse power over a wire pair to a powered device, identifying data transmitted during power transitions between a pulse power on time and a pulse power off time in the pulse power at the powered device, and applying FEC decoding to at least a portion of the data based on said identified power transitions.

Description

TECHNICAL FIELD

The present disclosure relates generally to network communications systems, and more particularly, to transmission of pulse power and data.

BACKGROUND

Conventional Ethernet cabling uses four-pair cables to transmit data over networks and deliver low power via Power over Ethernet (PoE) with constant voltages under 60 volts. With the growth of Internet of Things (IoT) along with other applications, interest has increased for Single Pair Ethernet (SPE), which provides a more compact and economical solution for delivering low Power over Data Line (PoDL).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a network in which embodiments described herein may be implemented.

FIG. 2 depicts an example of a network device useful in implementing embodiments described herein.

FIG. 3 illustrates an example of pulse power and data transmission with avoidance of data transmission during pulse power transition time.

FIG. 4 is a schematic of a system for delivering pulse power and data on a single wire pair with use of pulse power transition edges to control data transmission at a transmitter, in accordance with one embodiment.

FIG. 5 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to control a MAC/PHY to hold off data transmission at the transmitter, in accordance with one embodiment.

FIG. 6 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to mark packets for possible error at a receiver, in accordance with one embodiment.

FIG. 7 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to mark packets for discard at the receiver, in accordance with one embodiment.

FIG. 8 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to mark data for possible error at the receiver for use with FEC (Forward Error Correction), in accordance with one embodiment.

FIG. 9 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to control data transmission at the transmitter and a buffer and FEC decoder at the receiver, in accordance with one embodiment.

FIG. 10 is a schematic of a system for delivering pulse power and data on the single wire pair with use of pulse power transition edges to control the MAC/PHY to hold off data transmission at the transmitter and a buffer and FEC decoder at the receiver, in accordance with one embodiment.

FIG. 11A is a flowchart illustrating an overview of a process for transmitting pulse power and data on the single wire pair with control of data transmission at power sourcing equipment, in accordance with one embodiment.

FIG. 11B is a flowchart illustrating an overview of a process for transmitting pulse power and data on the single wire pair with FEC, in accordance with one embodiment.

FIG. 11C is a flowchart illustrating an overview of a process for transmitting pulse power and data on the single wire pair with marking of packets at a powered device, in accordance with one embodiment.

FIG. 11D is a flowchart illustrating an overview of a process for modulation of the pulse power for use in transmitting control plane data.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Overview

In one embodiment, an apparatus generally comprises an interface for transmitting pulse power and data to a powered device over a wire pair and a controller for receiving input identifying power transitions in the pulse power and suspending data transmission during the power transitions.

In one or more embodiments, the controller comprises a buffer for buffering the data based on the identified power transitions. In one or more embodiments, the controller is configured to use the identified power transitions to control a MAC (Media Access Control)/PHY (Physical layer entity) to hold off the data transmission during the identified power transitions. In one or more embodiments, the controller is operable to apply Forward Error Correction (FEC) to the data. In one or more embodiments, the FEC protects data not suspended during the power transitions.

In one or more embodiments, the wire pair comprises a Single Pair Ethernet (SPE) cable. In one or more embodiments, the pulse power and data are transmitted over a cable comprising multiple wire pairs. In one or more embodiments, the pulse power and data are transmitted over two wire pairs and the pulse power is applied at a pair center tap.

In one or more embodiments, each of the power transitions comprises an approximately 0.5 ms window during transition from power on to power off or from power off to power on. In one or more embodiments, the pulse power comprises power over 100 watts. In one or more embodiments, the apparatus is configured to modulate pulses of the pulse power to transmit control plane data to the powered device.

In another embodiment, an apparatus generally comprises an interface for receiving pulse power and data from power sourcing equipment on a wire pair and a controller for receiving input identifying power transitions in the pulse power and processing the data based on the identified power transitions.

In one or more embodiments, the controller marks the data received during the identified power transitions. At least a portion of the marked data may be dropped or retransmitted. In one or more embodiments, FEC is applied to the data at the power sourcing equipment and the controller marks the data received during the identified power transitions for decoding. In one or more embodiments the FEC comprises an erasure-correcting code.

In one or more embodiments, data transmission is suspended during power transitions at the power sourcing equipment and FEC is applied to the data, and the controller comprises a gate and a buffer for use in identifying the data received during the power transitions and reassembling the data.

In one or more embodiments, the apparatus further comprises a decoder for decoding encoded modulation of the pulse power at the power sourcing equipment for transmission of control plane data.

In yet another embodiment, a method generally comprises applying FEC to data at power sourcing equipment, transmitting the data and pulse power over a wire pair to a powered device, identifying data transmitted during power transitions in the pulse power at the powered device, and applying FEC decoding to at least a portion of the data based on the identified power transitions.

In one or more embodiments, the method further comprises suspending transmission of the data during power transitions at the power sourcing equipment, buffering the data transmitted during the identified power transitions at the powered device, and decoding the FEC for remaining data.

In one or more embodiments, the method further comprises marking the data transmitted during the identified pulse power transitions to identify possible errors for decoding.

In one or more embodiments, the method further comprises modulating pulses of the pulse power at the power sourcing equipment for use in transmitting control plane data to the powered device.

Further understanding of the features and advantages of the embodiments described herein may be realized by reference to the remaining portions of the specification and the attached drawings.

EXAMPLE EMBODIMENTS

The following description is presented to enable one of ordinary skill in the art to make and use the embodiments. Descriptions of specific embodiments and applications are provided only as examples, and various modifications will be readily apparent to those skilled in the art. The general principles described herein may be applied to other applications without departing from the scope of the embodiments. Thus, the embodiments are not to be limited to those shown, but are to be accorded the widest scope consistent with the principles and features described herein. For purpose of clarity, details relating to technical material that is known in the technical fields related to the embodiments have not been described in detail.

With the growing need to provide cost effective power and data connectivity to the large number of end point devices that will be deployed in the future, Single Pair Ethernet (SPE) has emerged as a promising technology. SPE enables data transmission over Ethernet via a single pair of wires while also providing a power supply (e.g., Power over Data Line (PoDL)) to pass electrical power along with data to allow a single cable to provide both data connectivity and electrical power to end point devices. New Ethernet applications are planned for use with single pair copper cables in the Enterprise, industrial applications, automotive Ethernet, and IoT devices (e.g., sensors, actuators, appliances, vehicles, lighting, health care monitoring devices, traffic control, phones, video cameras, point-of-sale devices, security access control devices and systems, residential devices, building and home automation, energy management, manufacturing equipment, smart systems, 5G Wi-Fi, 5G cellular data, and many more applications).

Conventional Power over Ethernet (PoE) or PoDL systems used to simultaneously transmit power and data communications over the same twisted pair cable are typically limited in range and power capacity. The maximum power delivery capacity of standard PoE is approximately 100 W (watts) and standard PoDL is approximately 50 W, but many classes of powered devices would benefit from power delivery over 100 W and in some cases up to 1000 W to 2000 W. In conventional systems, when larger power delivery ratings are needed, power is supplied to a remote device through a local power source. It is therefore desirable to increase the power available over cables using one or more balanced transmission pairs to hundreds and even thousands of watts. This capability may enable many new choices in network deployments where major devices such as workgroup routers, multi-socket servers, large displays, wireless access points, fog nodes, IoT devices, or other devices operated over cables using one or more balanced transmission pairs. This capability would greatly decrease installation complexity and improve the total cost of ownership of a much wider set of devices that have their power and data connectivity needs met from a central device.

In order to increase available power, high voltage pulses (referred to herein as pulse power) may be used. One example for delivering pulse power is described in U.S. patent application Ser. No. 15/971,729, filed May 4, 2018, entitled “High Power and Data Delivery in a Communications Network with Safety and Fault Protection”, which is incorporated herein by reference in its entirety.

Pulse power may be delivered along with data over a single balanced copper wire pair. The wire pair may be located within a Single Pair Ethernet (SPE) cable or a multi-pair cable (e.g., two-pair cable, four-pair cable, or any other number of pairs). A problem that may occur with transmission of data with pulse power on a wire pair is that edges of high voltage pulses may corrupt Ethernet packets. Thus, a simple summing of the pulse power and data signals together may result in data corruption on the pulse power edges and the data frequency spectrum may be washed out during pulse power transitions.

The embodiments described herein provide for mitigation of corruption of data due to pulse edges during pulse power transition with transmission of data and pulse power on a wire pair. As described in detail below, the embodiments allow data transmission while avoiding potential interference that may be caused by the pulse power that is coupled onto the same pair of wires transmitting data. In one or more embodiments, a control circuit from the pulse power circuitry may hold the data during pulse power transitions at a transmitter. Data may also be marked for possible error at the receiver based on the pulse power transitions. In one or more embodiments, FEC (Forward Error Correction) may be added to the control circuit to minimize the window in which data is held and maximize the overall data rate. In one or more embodiments, modulation of the high voltage pulses may also be used in parallel with the SPE (or multi-wire pair) transmission for control plane data.

It is to be understood that the term “wire pair” as used herein may refer to a single wire pair (single twisted pair, single balanced copper wire pair, single wire pair Ethernet) located in a single pair cable (e.g., SPE, Base-T1 Ethernet) or a wire pair located in a multi-pair cable (e.g., two-pair cable, four-pair cable, Base-T Ethernet). The other wire pairs in a multi-pair cable may deliver data, power, data and power (PoE, PoDL), or data and pulse power as described herein. The multi-pair cable may comprise multiple instances of single wire pairs (e.g., SPE, PoDL) in parallel or multiple wire pairs connected between a pair center tap (e.g., PoE). A system for transmitting pulse power and data over a multi-pair cable comprising more than one wire pair configured to transmit data and pulse power may comprise more than one circuit or additional components described below with respect to FIGS. 4-10 to prevent data corruption during power transitions for each wire pair.

As described in detail below, various logic and circuits may be used to provide pulse power and data on a single wire pair while avoiding Ethernet corruption during the pulse power transition times due to the pulse power transition edges. The circuits may be used to avoid potential interference caused by the pulse power that is coupled on the same pair of wires as the data.

Referring now to the drawings and first to FIG. 1, an example of a network in which the embodiments described herein may be implemented is shown. PSE (Power Sourcing Equipment) 10 transmits pulse power and data to a plurality of PDs 12 on single wire pair cables 14. In one example, the cables 14 are referred to herein as SPE cables, however, as previously described, each of the single wire pair cables 14 may comprise an SPE cable or multi-pair cable comprising at least one single wire pair transmitting data and pulse power. For simplification, only a small number of nodes are shown. The embodiments operate in the context of a data communications network including multiple network devices. The network may include any number or arrangement of network devices in communication via any number of nodes (e.g., routers, switches, gateways, controllers, access points, or other network devices) operable to route (switch, forward) data communications and facilitate passage of data within the network. The network devices may communicate over or be in communication with one or more networks (e.g., local area network (LAN), metropolitan area network (MAN), wide area network (WAN), virtual private network (VPN) (e.g., Ethernet virtual private network (EVPN), layer 2 virtual private network (L2VPN)), virtual local area network (VLAN), wireless network, enterprise network, corporate network, data center, Internet of Things (IoT) network, Internet, intranet, or any other network).

Signals may be exchanged among communications equipment and power transmitted from the power sourcing equipment 10 to powered devices 12. Data communications between the PSE 10 and PD 12 may be bidirectional (i.e., data transmitted from PSE to PD and from PD to PSE). The network is configured to pass electrical power along with data to provide both data connectivity and electrical power to network devices 12, which may include switches, routers, access points, IoT devices, or other electronic components and devices. The power may be transmitted from the PSE 10 to end points (PDs) 12, which may be located at distances up to 1000 m, for example, and at power levels greater than 50 W (e.g., 100 W, 250 W, 500 W, 1000 W, 2000 W or any other power level).

The PSE 10 is operable to receive external power and transmit power (e.g., pulse power, high voltage pulse power) over SPE cables 14 in the communications network. The PSE (power and data source) 10 may comprise a power supply unit (PSU) for receiving and distributing power and a network interface for receiving data (e.g., one or more fabric cards or line cards). The PSE 10 is operable to provide high capacity power from an internal power system (e.g., PSU capable of delivering power over and including 100 W (e.g., 1 kW or higher)) and driving the plurality of devices 12 each in the 50 W-2000 W range, or any other suitable power range. The PSE 10 may comprise, for example, a router, switch, convergence system, or any other suitable line card system or network device operable to transmit power and data.

One or more of the network devices 12 may also deliver power to equipment using PoE or PoDL. For example, one or more of the powered devices 12 may deliver power to electronic components such as IP (Internet Protocol) cameras, VoIP (Voice over IP) phones, video cameras, point-of-sale devices, security access control devices, residential devices, building automation devices, industrial automation devices, factory equipment, lights (building lights, streetlights), traffic signals, fog nodes, IoT devices, sensors, or other electrical components and devices. In one or more embodiments, a redundant PSE (not shown) may provide backup or additional power or bandwidth, as needed in the network. In one or more embodiments, there is no need for additional electrical wiring for the communications network and all of the network communications devices 12 operate using the power provided by the PSE 10 (or multiple PSEs).

The cable 14 is configured for single pair Ethernet and comprises two conductors (copper wires). SPE cables 14 extend from the PSE 10 to the PDs 12 and may be formed from any material suitable to carry both electrical power and data. The cables 14 may be connected to the network devices 10, 12 with a connector (connection, coupling, connector assembly) formed from a plug (also referred to as a male connector) and a receptacle (also referred to as a port, jack, receiver, or female connector) coupled together. The connection may be used for connecting communications equipment through cables 14 configured to carry both data and power. The connector may comprise, for example, a modified RJ-45 type connector or any other suitable connector. The SPE connector may be configured with a small form factor that allows for an increased number of ports as compared to conventional four-pair connectors.

The cable 14 may be configured according to a standard cable gauge and rated for one or more power or current levels, a maximum power level, a maximum temperature, or identified according to one or more categories indicating acceptable power level usage, for example. In one example, the cable 14 may correspond to a standardized wire gauge system such as AWG (American Wire Gauge). The cable 14 may comprise, for example, 18AWG or other suitable size cable. For different gauge wire, AWG provides data including diameter, area, resistance per length, ampacity (maximum amount of current a conductor can carry before sustaining immediate or progressive deterioration), and fusing current (how much current it takes to melt a wire in free air). Various other standards (e.g., NEC (National Electrical Code), UL (Underwriters Laboratories)) may be used to provide various requirements for the cables and connectors and provide temperature or power ratings or limits, or other information.

The network may also include appropriate safety features as needed for higher power PoDL (e.g., insulation, process for power/cable compatibility confirmation, control circuit check for open/short, or thermal sensor). In one or more embodiments, the connector and cable 14 are configured to meet standard safety requirements for line-to-ground protection and line-to-line protection at relevant high voltage by means including clearance and creepage distances, and touch-safe techniques. The connector may comprise safety features, including, for example, short-pin for hot-plug and hot-unplug without current surge or interruption for connector arcing protection. The connector may further include additional insulation material for hot-plug and hot-unplug with current surge or interruption with arc-flash protection and reliability life with arcing. The insulated cable power connector terminals are preferably configured to meet touch voltage or current accessibility requirements.

In one or more embodiments, the network may incorporate safety features as described in U.S. patent application Ser. No. 15/971,729, referenced above. For example, the system may operate in a communications network with fault detection and safety protection (e.g., touch-safe fault protection). In one embodiment, fault sensing may be performed through a low voltage safety check combined with a digital interlock that uses the data system to provide feedback on the power system status and set a power operation mode. The fault sensing may be performed, for example, during a low voltage startup or between high power pulses in the pulse power system. The pulse power may comprise low voltage fault detection between high voltage power pulses, for example. Fault sensing may include, for example, line-to-line fault detection with low voltage sensing of the cable or powered device and line-to-ground fault detection with midpoint grounding. Touch-safe fault protection may also be provided through cable and connector designs that are touch-safe even with high voltage applied. The power safety features provide for safe system operation and installation and removal (disconnect) of components.

As described below, pulse power uses short pulses of high voltage power. In one or more embodiments, the signature of the pulse may be analyzed for each cycle. This analysis may be a rising edge, falling edge, or both. If the signature is corrupt by an unexpected load, the pulses may be stopped until it is determined that the load is safe to power. The signature may be corrupted, for example, by a human, short, or open.

It is to be understood that the safety features described above are only examples of safety or fault protection features that may be included for high voltage pulse power. Any combination of these or other safety features may be used with the embodiments described herein.

In one or more embodiments, the system may employ a dual-power mode that detects and negotiates between the power source 10 and powered device 12. This negotiation may, for example, distinguish between and accommodate different power-delivery schemes, such as standard PoDL, high power, pulse power, or other power modes. Standard PoDL distribution may be used for remote network devices rated less than about 50 W, for example. For higher power remote powered devices, pulse power may be used to create an efficient energy distribution network.

In one or more embodiments, 100 Mbps to 1000 Mbps data may be delivered over a distance of approximately 40 meters, 10 Gbps data may be delivered over a distance of approximately 15 meters, or 10 Mbps data may be delivered over a distance of approximately 1 km. For example, data may be transmitted at a rate of 1 Gbps at a distance up to 40 m in accordance with IEEE 802.3 bp or IEEE 802.3bw, data may be transmitted at 10 Mbps for a distance up to 1000 m in accordance with IEEE 8002.3cg, or data may be transmitted at 2.5 Gbps-10 Gbps over a distance up to 10 m or 15 m in accordance with IEEE 802.3ch. It is to be understood that these power levels and distances are provided only as examples and other power levels in combination with other distances may be used in accordance with the above referenced standards or any other applicable standard or future standard, without departing from the scope of the embodiments.

Furthermore, it is to be understood that the network devices and topology shown in FIG. 1 and described above is only an example and the embodiments described herein may be implemented in networks comprising different network topologies or network devices, without departing from the scope of the embodiments. For example, the network may comprise any number or type of network communications devices that facilitate passage of data over the network (e.g., routers, switches, gateways, controllers, access points), network elements that operate as endpoints or hosts (e.g., servers, virtual machines, clients, IoT devices), and any number of network sites or domains in communication with any number of networks. Thus, network nodes may be used in any suitable network topology, which may include any number of servers, virtual machines, switches, routers, or other nodes interconnected to form a large and complex network, which may include cloud or fog computing. Nodes may be coupled to other nodes or networks through one or more interfaces employing any suitable connection, which provides a viable pathway for electronic communications along with power.

FIG. 2 illustrates an example of a network device 20 (e.g., PSE 10, PD 12 in FIG. 1) that may be used to implement the embodiments described herein. In one embodiment, the network device 20 is a programmable machine that may be implemented in hardware, software, or any combination thereof. The network device 20 includes one or more processor 22, memory 24, interface 26, and data/pulse power controller 28.

Memory 24 may be a volatile memory or non-volatile storage, which stores various applications, operating systems, modules, and data for execution and use by the processor 22. For example, components of the controller 28 (e.g., code, logic, or firmware, etc.) may be stored in the memory 24. The network device 20 may include any number of memory components.

The network device 20 may include any number of processors 22 (e.g., single or multi-processor computing device or system), which may communicate with a forwarding engine or packet forwarder operable to process a packet or packet header. The processor 22 may receive instructions from a software application or module, which causes the processor to perform functions of one or more embodiments described herein. The processor 22 may also operate one or more components of the controller 28.

The data/pulse power controller 28 may comprise components (modules, gate, buffer, FEC block, packet marking/dropping block, encoder, decoder, error correcting code, software, logic) located at the PSE 10 or the PD 12, and interconnected through the combined power and data SPE cable 14 (FIGS. 1 and 2). As described below, the controller 28 may control data transmission or data processing (e.g., marking, dropping, decoding) based on power transitions at the pulse power. The controller 28 may also modulate pulses of the pulse power to transmit control plane data from the PSE to the PD.

Logic may be encoded in one or more tangible media for execution by the processor 22. For example, the processor 22 may execute codes stored in a computer-readable medium such as memory 24. The computer-readable medium may be, for example, electronic (e.g., RAM (random access memory), ROM (read-only memory), EPROM (erasable programmable read-only memory)), magnetic, optical (e.g., CD, DVD), electromagnetic, semiconductor technology, or any other suitable medium. In one example, the computer-readable medium comprises a non-transitory computer-readable medium. Logic may be used to perform one or more functions described below with respect to the flowcharts of FIGS. 11A, 11B, 11C, and 11D. The network device 20 may include any number of processors 22.

The interface 26 may comprise any number of network interfaces (line cards, ports, inline connectors (e.g., receptacle)) for transmitting or receiving power and transmitting and receiving data. The network interface may be configured to transmit or receive data using a variety of different communications protocols and may include mechanical, electrical, and signaling circuitry for communicating data over physical links coupled to the network interfaces. For example, line cards may include port processors and port processor controllers. One or more of the interfaces 26 may be configured for PoDL on SPE or PoE on multi-pair cable.

It is to be understood that the network device 20 shown in FIG. 2 and described above is only an example and that different configurations of network devices may be used. For example, the network device 20 may further include any suitable combination of hardware, software, algorithms, processors, devices, components, or elements operable to facilitate the capabilities described herein.

FIG. 3 illustrates an example of a pulse power on/off cycle with data transmittal (e.g., 10 Mbps data (or any other data rate)). In this example, a pulse power cycle comprises 4 ms power on and 1 ms power off. It is to be understood that the power duty cycle shown in FIG. 3 is only an example and that different power on or power off timing may be used without departing from the scope of the embodiments. Also, it should be noted that power transitions (from power on to power off or from power off to power on) may occur over a period of time (i.e., rising or falling slope or curve). As previously described, edges of pulse power signal 30 during pulse power transitions 34 (time period covering a transition from power on to power off or from power off to power on) may impact data signal 32. In one example, data transfer may be suspended during the pulse power transitions 34. In the example shown in FIG. 3, the power pulse transition 34 covers a 0.5 ms time period. Holding off (suspending) data transmission during this transition period provides a clear distinction between power and data, thereby providing the pulse circuitry a reliable method to determine faults, while eliminating application of significant coding and signaling to the data stream. As shown in the example of FIG. 3, data is transmitted for 3.5 ms, suspended (stopped, held) for 0.5 ms, resumed for 0.5 ms, and suspended for 0.5 ms. This cycle is repeated to avoid data transmission during the pulse power transition times. Examples of circuits that may be used to avoid data transmission during the pulse power transitions are shown in FIGS. 4 and 5, and described below.

FIG. 4 illustrates an example of a system, generally indicated at 40, that may be used to hold off data transmissions during periods of potential corruption (e.g., pulse power transition time periods 34 shown in FIG. 3), in accordance with one embodiment. Pulse power and data are provided at lines 41, 43 to transmitter (multiplexer) 45 and transmitted over a single wire pair 46 (e.g., SPE cable, multi-pair cable) to receiver (demultiplexer) 47 connected to pulse power line 48 and data line 49. The pulse power and data input lines 41, 43 and transmitter 45 are located at the PSE 10 in FIG. 1, and the receiver 47 and pulse power and data output lines 48, 49 are located at the PD 12. Transmission line 46 represents the cable 14 in FIG. 1 (e.g., SPE cable, multi-pair cable). The block 45 is referred to as a multiplexer/transmitter at a transmitting end (e.g., PSE 10 in FIG. 1) and the block 47 is referred to as a demultiplexer/receiver at a receiving end (e.g., PD 12 in FIG. 1). It is to be understood that data on line 49 may also be transmitted from the PD 12 to the PSE 10 on the cable 14 (FIGS. 1 and 4).

In this example, pulse power edges are used to control a buffer for the data through control block 42 providing input to gate 44. Since the PSE generates the data and the pulse power, the data transmitter has direct access to the power signal timing. The controller 42 holds off transmission of data at data input 43 during pulse power transition times. For example, referring to the power and data duty cycle shown in FIG. 3, as the pulse power transitions to off, the controller 42 instructs the gate 44 to buffer data for 0.5 ms. Data is then transmitted for 0.5 ms while the power is off and is then held back (suspended) for another 0.5 ms while the power cycles to on. As previously noted, the data timing cycle shown in FIG. 3 is only an example and different timing may be used, without departing from the scope of the embodiments. For example, power may be cycled on or off for a different time period and the length of time for which the data is buffered during the pulse power transition time may be different than 0.5 ms.

FIG. 5 illustrates a system, generally indicated at 50, for controlling data transmission for use with pulse power, in accordance with one embodiment. Pulse power line 51 provides input to control block 52, which controls MAC (Media Access Control)/PHY (Physical layer entity) block 54 to hold off data transmission during pulse power transition edges. The PHY block 54 contains functions that transmit, receive, and manage encoded signals that are impressed on and recovered from the physical medium. Pulse power at line 51 and data at line 53 are input at block (multiplexer) 55 and transmitted over transmission line 56 to block (demultiplexer) 57 connected to pulse power line 58 and data line 59. Components 51, 52, 53, 54, and 55 are located at the PSE 10 and components 57, 58, and 59 are located at the PD 12 in FIG. 1. Referring again to the power and data duty cycle shown in FIG. 3, as the pulse power transitions to off, the controller 52 instructs the MAC/PHY block 54 to buffer data for 0.5 ms. Data is then transmitted for 0.5 ms while the power is off and once again suspended for another 0.5 ms while the power cycles to on. As previously noted, different power duty cycles may be used without departing from the scope of the embodiments.

FIGS. 6 and 7 show examples of systems 60, 70, respectively, in which pulse power transitions are used to control data at the receiving end (e.g., PD 12 in FIG. 1). As described in detail below, pulse power transition edges may be used to mark packets, which may be dropped or retried (retransmission request).

FIG. 6 illustrates a system, generally indicated at 60, operable to use pulse power transition edges at pulse power line 68 at receiver (demultiplexer) 67 to mark data for errors at data line 69, in accordance with one embodiment. Pulse power is received at line 61 and data is received at line 63 at transmitter (multiplexer) 65 and transmitted over single wire pair 66 to the receiver 67 (e.g., PD 12). A controller 62 uses the pulse power transition edges to mark packets for possible error at block 64. Packets marked for error may be dropped, depending on the number of bit errors or requested to be retried based on packet type, for example.

FIG. 7 illustrates a system, generally indicated at 70, operable to use pulse power transition edges to mark data for discard at data line 79, in accordance with one embodiment. Pulse power is received at line 71 and data is received at line 73 at transmitter 75 (e.g., PSE 10 in FIG. 1) and transmitted over single wire pair 76 to the receiver 77 (e.g., PD 12 in FIG. 1). Controller 72 marks packets to drop at block 74 on the data line 79 at the receiver based on the pulse power transition times. In this example, all packets are dropped at discard block 74 during the pulse power transitions. Client recovery may be needed on each side of the line to prevent data quality issues.

FIGS. 8, 9, and 10 illustrate systems 80, 90, and 100, respectively, which use locations of the pulse power transitions to indicate the location of possible errors in the data. FEC (Forward Error Correction) may be used to correct errors in the data identified as being received during pulse power transitions (FIG. 8) or for use on data that is not held off during pulse power transitions when used in combination with suspending data during pulse power transitions at the PSE (FIGS. 9 and 10). The FEC may utilize any suitable error correcting code to control errors in the data transmission (e.g., Reed-Solomon or any other suitable code). The error correcting code provides redundancy, which allows the receiver to detect errors and correct errors without retransmission. In one or more embodiments, the data may be encoded with an erasure correcting code at the PSE 10 using burst FEC and encoded at the PD 12, as described below with respect to FIG. 8.

FIG. 8 illustrates a system, generally indicated at 80, for use in marking the location of symbols likely to be in error for an erasure-correcting decoder 84 at the PD, in accordance with one embodiment. Pulse power is received at line 81 and data at line 83 at multiplexer 85. FEC (e.g., burst FEC erasure-correcting code) is applied at block 82. The data and power are transmitted on SPE transmission line 86 to receiver (demultiplexer) 87. Locations of the pulse power transitions on power line 88 are used to mark the location of symbols likely to be in error at block 92. The erasure-correcting decoder 84 decodes the marked data at data line 89. This may increase the number of errors that can be corrected by a factor of two, for example, and may significantly reduce the number of packet drops or retries.

FIG. 9 illustrates a system, generally indicated at 90, in which data transmission is gated based on pulse power transitions (as described above with respect to FIG. 4) and FEC is used to protect the remaining data. The pulse power at line 91 is used to indicate pulse power transitions at controller 114, which provides input at gate 94 to hold the data during the pulse power transitions. FEC block 115 at the PSE is used along with decoder 104 at the PD to protect the remaining data transmitted at multiplexer 95 on single wire pair 96 and received at demultiplexer 97. The order of the gate 94 and FEC block 115 may be interchanged at the transmitter. At the receiver, pulse power line 98 provides input at a gate receiver clock 102, which provides input to FEC decode and buffer 104 on data line 99. In contrast to the system 80 shown in FIG. 8, the receiver in the system 90 is only gating the received signal to reassemble the sequence (hence the buffer). It is not declaring erasure locations to aid the decoder.

FIG. 10 illustrates a system, generally indicated at 100, that combines the control of data at the transmitter as described above with respect to FIG. 5 with the FEC of FIG. 9, in accordance with one embodiment. Data transmission on data line 103 is controlled at MAC/PHY 111 based on pulse power transitions (as described above with respect to FIG. 5) and FEC 110 is used to protect the remaining data (as described above with respect to FIG. 9). The pulse power at line 101 is used to indicate pulse power transitions at controller 116, which provides input at MAC/PHY 111 to hold the data based on the pulse power transitions. FEC block 110 protects the remaining data transmitted at multiplexer 105. The data and power are transmitted on single wire pair 106 and received at demultiplexer 107. At the receiver, pulse power line 108 provides input at a gate receiver clock 112, which provides input to FEC decode and buffer block 113 on data line 109. As previously noted, the receiver is only gating the received signal to reassemble the sequence and is not declaring erasure locations to aid the decoder.

In one or more embodiments, an error rate on the FEC block receiver 104, 113 (FIGS. 9 and 10) may be used to indicate that there may be a fault in the wire. For example, an increase in FEC errors may indicate an issue with the wire in which case pulse power should be shut down (or the power changed to a lower setting). The PD 12 may provide information on FEC errors to the PSE 10 (FIG. 1) over bidirectional communications cable 14.

It is to be understood that the systems 40, 50, 60, 70, 80, 90, and 100 shown in FIGS. 4-10 are only examples and components may be added, removed, modified, or combined without departing from the scope of the embodiments. Also, it is to be understood that the term “controller” as used herein may refer to one or more components used to mitigate data errors during pulse power transitions at the PSE 10, PD 12, or both ends of the single wire pair. For example, a controller at the PSE may include control block 42 and gate 44 (FIG. 4) or control block 116 and FEC block 110 (FIG. 10). A controller at the PD may include, for example, the control block 62, 72 and mark or discard block 64, 74 (FIGS. 6 and 7) or the gate receiver clock 112 and FEC decoder/buffer 113 (FIG. 10) or any subset or combination of these components.

Also, as previously noted, pulse power and data may be transmitted over any number of wire pairs. Each wire pair transmitting pulse power and data may be associated with a circuit such as shown in FIGS. 4-10 to mitigate data corruption during pulse power transitions. One or more circuit components may be shared between wire pairs if pulse power is transmitted in a phantom power scheme (e.g., using a center tap such as in PoE).

FIGS. 11A-11D are flowcharts illustrating an overview of processes for transmitting and receiving pulse power and data over SPE, in accordance with one or more embodiments.

Referring first to the flowchart of FIG. 11A, data transmission is controlled based on pulse power transmission timing at the PSE. At step 120, data transmission is suspended during power transitions on pulse power at the PSE. For example, a controller (e.g., control block 42 and gate 44 in FIG. 4, control block 52 and MAC/PHY 54 in FIG. 5) may suspend transmission of data at the power sourcing equipment during identified power transitions (e.g., 0.5 ms period 34 shown in FIG. 3). Data and pulse power are transmitted on the cable 14 to the powered device 12 (step 122) (FIGS. 1 and 11A).

FIG. 11B illustrates a process for using FEC to mitigate corruption of Ethernet packets (data transmission) during pulse power transitions, in accordance with one embodiment. FEC is applied to data at the PSE 10 (step 124) (FIGS. 1 and 11B). The data and pulse power are transmitted over the cable 14 to the powered device 12 (step 126). The power transitions are identified in the pulse power at the powered device 12 and data is decoded at the powered device based on the identified power transitions (step 128). For example, data transmitted during the pulse power transitions may be decoded to identify possible error as described above with respect to FIG. 8. FEC may also be used to protect data that is not suspended during pulse power transitions at the PSE (remaining data), as described above with respect to FIGS. 9 and 10.

FIG. 11C illustrates a process at the powered device for mitigating corruption of data during power transitions, in accordance with one embodiment. At step 130, data and pulse power are received on the cable 14 at the powered device 12 (FIGS. 1 and 11C). Pulse power transitions are used to mark packets for possible error (step 132). A portion of the marked packets may be dropped or retransmitted or all of the marked packets may be dropped, as described above with respect to FIGS. 6 and 7 (step 134).

In one or more embodiments, modulation of the high voltage pulse power may be used in parallel with the SPE transmission for control plane data. For example, encode modulation may be added at the transmitter end with decoding at the receiver used to transmit control plane data. This would include the addition of decode components at the receiver end for the control plane data. FIG. 11D is a flowchart illustrating an overview of a process for transmitting control plane data, in accordance with one embodiment. At step 136, power pulses are modulated at the PSE to provide control plane data. The data and pulse power are transmitted on the cable with the control plane data superimposed on the power signal (step 138). The modulated power pulses are decoded at the powered device to provide the control plane data to the powered device (step 140). Any type of suitable modulation may be used (e.g., PWM (Pulse Width Modulation), NRZ (Non-Return to Zero), or other modulation).

It is to be understood that the processes shown in FIGS. 11A-11D and described above are only examples and steps may be added, removed, modified, or combined without departing from the scope of the embodiments. For example, one or more of the steps of the processes shown in FIGS. 11A, 11B, 11C, and 11D may be combined with one or more steps from another of the processes shown in a different flowchart. Also, as noted above, the cable may comprise a multi-pair cable and the process may be performed on one or more wire pairs. As previously described, FEC shown in steps 124-128 of FIG. 11B may be added to the process shown in FIG. 11A.

Although the method and apparatus have been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations made to the embodiments without departing from the scope of the invention. Accordingly, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

1. A method comprising: applying Forward Error Correction (FEC) to data at power sourcing equipment;transmitting the data and pulse power over a wire pair to a powered device, the pulse power comprising a pulse power on time and a pulse power off time;identifying power transitions between the pulse power on time and the pulse power off time in the pulse power at the powered device;marking data transmitted during the power transitions to identify errors for decoding; andapplying FEC decoding to at least a portion of the data that is transmitted during the power transitions.

2. The method of claim 1 further comprising suspending transmission of the data during power transitions at the power sourcing equipment, buffering the data transmitted during said power transitions at the powered device, and decoding the FEC for remaining data.

3. The method of claim 1 further comprising modulating pulses of the pulse power at the power sourcing equipment for use in transmitting control plane data to the powered device.

4. The method of claim 1 wherein the pulse power on time comprises a high voltage state and the pulse power off time comprises a low voltage state.

5. The method of claim 4 wherein the data is transmitted only during the pulse power on time.

6. The method of claim 1 wherein the FEC mitigates corruption of Ethernet packets during said power transitions.

7. The method of claim 1 wherein said power transitions each comprise an approximately 0.5 millisecond time window and wherein the pulse power on time is greater than the pulse power off time.

8. The method of claim 1 wherein identifying said power transitions comprises identifying said power transitions at a controller at the powered device, wherein the controller is coupled to a wire pair receiving the data and the pulse power.

9. The method of claim 1 further comprising performing fault sensing during a low voltage startup before transmitting the pulse power and between high power pulses in the pulse power.

10. The method of claim 1 further comprising monitoring an FEC error rate; identifying a fault on a wire based on an increase in the FEC error rate; and shutting down the pulse power.

11. A powered device comprising: an interface configured to receive pulse power and data from power sourcing equipment over a wire pair, the pulse power comprising a pulse power on time and a pulse power off time; anda controller coupled to the wire pair and configured to perform operations including: identifying power transitions between a pulse power on time and a pulse power off time in the pulse power;marking data transmitted during the power transitions to identify errors for decoding; andapplying Forward Error Correction (FEC) decoding to at least a portion of the data that is transmitted during the power transitions to mitigate corruption of the data during said power transitions.

12. The powered device of claim 11 wherein the data is suspended during power transitions at the power sourcing equipment and the controller is buffers the data transmitted during said power transitions at the powered device and performs FEC decoding for remaining data.

13. The powered device of claim 11 wherein locations of said power transitions are used to mark a location of symbols in the data that are potentially in error and wherein the controller comprises an erasure-correcting decoder to decode the symbols in the data whose locations have been marked.

14. The powered device of claim 11 wherein the data is transmitted only during said pulse power on time.

15. The powered device of claim 11 wherein fault sensing is performed during a low voltage startup before the pulse power is transmitted to the powered device and between high power pulses in the pulse power.

16. The powered device of claim 11, wherein the power transitions each comprise an approximately 0.5 millisecond time window and wherein the pulse power on time is greater than the pulse power off time.

17. A system comprising: power sourcing equipment operable to transmit data and pulse power and apply Forward Error Correction (FEC) to the data, the pulse power comprising a pulse power on time and a pulse power off time;a powered device that receives the data and the pulse power from the power sourcing equipment over a wire pair; anda controller at the powered device, the controller configured to perform operations including: identifying power transitions between the pulse power on time and the pulse power off time in the pulse power;marking data transmitted during the power transitions to identify errors for decoding; andapplying FEC decoding to at least a portion of the data that is transmitted during the power transitions to mitigate corruption of the data during said power transitions.

18. The system of claim 17 wherein the power sourcing equipment performs fault sensing during a low voltage startup before the pulse power is transmitted to the powered device and between high power pulses in the pulse power.

19. The system of claim 17 wherein locations of said power transitions are used to mark a location of symbols in the data that are potentially in error and wherein the controller comprises an erasure-correcting decoder to decode symbols in the data whose locations have been marked.

20. The system of claim 17, wherein the controller is configured to further perform operations including: monitoring an FEC error rate; andidentifying a fault on the wire pair based on an increase in the FEC error rate.