Patent Application
20240146359
This application relates to the field of communications technologies, and in particular, to a transmission processing method and apparatus, a communication device, and a readable storage medium.
With the development of communications technologies, the orthogonal time frequency space (OTFS) modulation technique is applied in the communications technologies. This technique logically maps information in a data packet of M×N into one M×N grid point on a two-dimensional delay-Doppler domain plane, that is, pulses within each grid point modulate one symbol of the data packet. The analysis of sparse channel matrices in the delay-Doppler domain using the OTFS modulation technique allows for tighter and more flexible encapsulation of reference signals. Because current discussion on the delay-Doppler domain is only for single antenna, how to apply multi-input multi-output (MIMO) in the delay-Doppler domain has become an urgent problem.
According to a first aspect, a transmission processing method is provided, including:
splitting, by a transmit end, a delay-Doppler domain resource block corresponding to each antenna in L antennas into L sub-blocks of equal size, L being an integer greater than 1; and
performing, by the transmit end, delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
According to a second aspect, a transmission processing apparatus is provided, including:
a splitting module, configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of a transmit end into L sub-blocks of equal size, L being an integer greater than 1; and
an encoding module, configured to perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
According to a third aspect, a terminal is provided, where the terminal includes a processor, a memory, and a program or instructions stored in the memory and capable of running on the processor, and when the program or instructions are executed by the processor, the steps of the method according to the first aspect are implemented.
According to a fourth aspect, a terminal is provided, including a processor and a communication interface, where
the processor is configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of the terminal into L sub-blocks of equal size, L being an integer greater than 1; and perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
According to a fifth aspect, a network-side device is provided, where the network-side device includes a processor, a memory, and a program or instructions stored in the memory and capable of running on the processor, and when the program or instructions are executed by the processor, the steps of the method according to the first aspect are implemented.
According to a sixth aspect, a network-side device is provided, including a processor and a communication interface, where
the processor is configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of the network-side device into L sub-blocks of equal size, L being an integer greater than 1; and perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
According to a seventh aspect, a readable storage medium is provided, where a program or instructions are stored in the readable storage medium, and when the program or instructions are executed by a processor, the steps of the method according to the first aspect are implemented.
According to an eighth aspect, an embodiment of this application provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or instructions to implement the steps of the method according to the first aspect.
According to a ninth aspect, a computer program product is provided, where the computer program product is stored in a non-transitory storage medium, and the computer program product is executed by at least one processor to implement the method according to the first aspect.
The following clearly describes the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are only some rather than all of the embodiments of this application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of this application shall fall within the protection scope of this application.
In the specification and claims of this application, the terms such as “first” and “second” are intended to distinguish between similar objects but do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way is interchangeable in appropriate circumstances so that the embodiments of this application can be implemented in other orders than the order illustrated or described herein, and “first” and “second” are usually for distinguishing same-type objects but not limiting the number of objects, for example, a first object may be one or multiple. In addition, in the specification and claims, “and/or” represents presence of at least one of connected objects, and the symbol “/” in this specification usually indicates an “or” relationship between associated objects.
It should be noted that techniques described in the embodiments of this application are not limited to a long term evolution (LTE) or LTE-advanced (LTE-A) system, and may also be applied to various wireless communication systems, for example, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiple access (OFDMA), single-carrier frequency-division multiple access (SC-FDMA), and other systems. The terms “system” and “network” in the embodiments of this application are usually used interchangeably. Techniques described herein may be used in the aforementioned systems and radio technologies, and may also be used in other systems and radio technologies. In the following descriptions, a new radio (NR) system is described for an illustration purpose, and NR terms are used in most of the following descriptions, although these technologies may also be applied to other applications than an NR system application, for example, the 6th generation (6G) communication system.
For ease of understanding, the following describes some content included in the embodiments of this application:
Characteristics of delay and Doppler of channels are essentially determined by multipath channels. Signals arriving at a receiver through different paths have different propagation distances, resulting in different arrival times. For example, if two echoes S1 and S2 have traveled distances d1 and d2 respectively to arrive at the receiver, a time difference between their arrivals is
where c is the speed of light. Due to the time difference between the echoes S1 and S2, their coherent superposition at the receiver side causes amplitude fluctuations in an observed signal. Similarly, Doppler spread for the multipath channel is also caused by a multipath effect. As known, the Doppler effect is caused by existence of relative velocity at the transmit end and the receive end, and signals arriving at the receiver via different paths have different angles of incidence with respect to the antenna normal, which results in differences in relative velocities and further leads to different Doppler shifts of signals from different paths. Assuming that the original frequency of the signal is f0, the relative velocity at the transmit end and the receive end is Δν, and the angle of incidence of the signal with respect to the antenna normal at the receive end is θ,
Apparently, when two echoes S1 and S2 arrive at the receiver-end antenna via different paths with different angles of incidence θ1 and θ2, respectively, the resulting Doppler shifts are also different. In summary, the signal observed at the receiver end is a superposition of component signals with different delays and Doppler shifts from different paths. Delay-Doppler analysis for the channel helps gather delay-Doppler information for each path, thus reflecting delay-Doppler response of the channel.
The OTFS modulation technique logically maps information in a data packet with a size of M×N into one M×N grid point on a two-dimensional delay-Doppler domain plane, that is, pulses within each grid point modulate one symbol of the data packet. Further, one set of orthogonal two-dimensional basis functions is designed to transform a data set from the delay-Doppler domain plane of M×N to the time-frequency domain plane of N×M. Such transform is mathematically known as inverse sympletic finite Fourier transform (ISFFT). Correspondingly, transform from the time-frequency domain to the delay-Doppler domain is known as sympletic finite Fourier transform (SFFT). The physical meaning behind this lies in that the signal delay-Doppler effect is actually a linear superposition effect of a series of echoes with different time and frequency offsets of a signal passing through a multipath channel. In this sense, delay-Doppler analysis and time-frequency domain analysis can be obtained through mutual transform between the inverse sympletic finite Fourier transform and the sympletic finite Fourier transform.
By doing so, the OTFS technique transforms the time-varying multipath channel into a time-invariant (within a specific duration) two-dimensional delay-Doppler domain channel, directly reflecting the delay-Doppler response characteristics of the channel resulting from geometric characteristics of relative positions of reflectors between the transmitter and receiver in radio links. This eliminates difficulties in tracking time-varying fading characteristics in conventional time-frequency domain analysis; instead, all diversity characteristics of the channel in the time-frequency domain are extracted through delay-Doppler domain analysis. In practical systems, because the number of delay paths and Doppler shifts of the channel is much smaller than the number of time- and frequency-domain responses of the channel, the channel impulse response matrix represented by the delay-Doppler domain features sparsity. The analysis of sparse channel matrices in the delay-Doppler domain using the OTFS technique allows for tighter and more flexible encapsulation of reference signals.
OTFS modulation defines quadrature amplitude modulation (QAM) symbols on the delay-Doppler plane and transforms them to the time-frequency domain for transmission. At the receive end, it is returned back to the delay-Doppler domain for processing. Therefore, a radio channel response analysis method in the delay-Doppler domain can be introduced. When a signal passes through a linear time-varying radio channel, the relationship between its channel responses expressed on different planes is shown in
In
h(τ,84 )=∫∫H(t,f)e−j2π(νt−fτ)dτdν (1)
Correspondingly, the ISFFT transform formula is:
H(t,f)=∫∫h(τ,ν)ej2π(νt−fτ)dτdν (2)
When a signal passes through a linear time-varying channel, a time-domain received signal is r(t), a corresponding frequency-domain received signal is R(f), and r(t)=−1{R(f)}, where r(t) may be expressed as follows:
r(t)=s(t)*h(t)=∫g(t,τ)s(t−τ)dτ (3)
Based on the relationship in
g(t,τ)=∫h(ν,τ)ej2πνtdv (4)
(4) is substituted into (3) to obtain the following:
r(t)=∫∫h(ν,96 )s(t−τ)ej2πνtdτdν (5)
Based on the relationship shown in
where ν represents a delay variable, τ represents a Doppler variable, f represents a frequency variable, and t represents a time variable.
Equation (6) implies that delay-Doppler domain analysis in the OTFS system can rely on the existing communication framework established in the time-frequency domain, with additional signal processing steps performed at the transmit end and the receive end. Moreover, the additional signal processing includes only Fourier transform, which can be implemented entirely using existing hardware, without the need for additional modules. Such high compatibility with the existing hardware system greatly facilitates the application of the OTFS system. In practical systems, the OTFS technique can be conveniently implemented as pre- and post-processing modules for one filtered OFDM system, making it highly compatible with existing multi-carrier systems under the NR technology architecture.
When OTFS is combined with the a multi-carrier system, the implementation at the transmit end is as follows: QAM symbols containing information to be sent are carried using waveforms on the delay-Doppler plane, undergo two-dimensional ISFFT to transform into waveforms on the time-frequency domain plane of the conventional multi-carrier system, and then undergo symbol-level one-dimensional inverse fast Fourier transform (IFFT) and serial-parallel conversion, and then become time-domain samples for transmission.
The receive end in the OTFS system roughly performs the inverse process of the transmit end: time-domain samples received by the receiver are processed through parallel-serial conversion and symbol-level one-dimensional fast Fourier transform (FFT), transformed into waveforms on the time-frequency domain plane, and then undergo SFFT to transform into waveforms on the delay-Doppler domain plane. QAM symbols carried using the delay-Doppler domain waveforms are processed by the receiver, including channel estimation and equalization, demodulation, decoding, and the like.
The advantages of OTFS modulation are mainly reflected in the following aspects:
OTFS modulation transforms a time-varying fading channel between the transmitter and the receiver in the time-frequency domain into a deterministic non-fading channel in the delay-Doppler domain. In the delay-Doppler domain, each symbol in a set of information symbols transmitted at once experiences the same static channel response and signal-to-noise ratio (SNR).
The OTFS system analyzes a delay-Doppler image to identify reflectors in the physical channel and uses receiver equalizers to coherently combine the energy from different reflected paths, actually providing a non-fading static channel response. Utilizing this static channel characteristic, the OTFS system does not require closed-loop channel adaptation like an OFDM system to deal with rapidly changing channels, thereby improving system robustness and reducing system design complexity.
Due to the significantly smaller number of delay-Doppler states in the delay-Doppler domain compared to the time-frequency domain, the channel in the OTFS system can be expressed in a very compact form. Channel estimation in the OTFS system incurs fewer overheads and achieves higher accuracy.
Another advantage of OTFS is its performance in extreme Doppler channels. Through analysis of the delay-Doppler image under appropriate signal processing parameters, the Doppler characteristics of the channel can be fully presented, which facilitates signal analysis and processing in Doppler-sensitive scenarios (such as high-speed mobility and millimeter-wave).
In summary, channel estimation in the OTFS system is performed as follows: the transmitter maps pilot pulses onto the delay-Doppler domain, and the receiver estimates the channel response h(ν,τ) of the delay-Doppler domain by analyzing the delay-Doppler image of the pilots, so as to obtain expression of channel response in the time-frequency domain according to the relationship in
In
l
τ≥τmaxMΔf,kv≥vmaxNΔT (7)
τmax and vmax are respectively the maximum delay and maximum Doppler shift of all paths in the channel, and multiple protection symbols 302 surround the single-point pilot 301 to form the protection band, with the multiple protection symbols 302 corresponding to blank resource elements.
The following describes in detail a transmission processing method provided in the embodiments of this application by using some embodiments and application scenarios thereof with reference to the accompanying drawings.
Referring to
Step 401: A transmit end splits a delay-Doppler domain resource block corresponding to each antenna in L antennas into L sub-blocks of equal size, L being an integer greater than 1.
In this embodiment of this application, the transmit end may be understood as a terminal or a network-side device, and the L antennas are all or part of antennas of the transmit end. The transmit end may use the L antennas to implement multi-input multi-output to improve transmission performance.
Optionally, in some embodiments, the L sub-blocks obtained by splitting the delay-Doppler domain resource blocks corresponding to different antennas have a same position in the delay-Doppler domain. For example, the delay-Doppler domain resource blocks corresponding to the antennas are split in the same manner, and the L sub-blocks obtained by splitting the delay-Doppler domain resource blocks corresponding to each antenna are of a same size and position.
Step 402: The transmit end performs delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
In this embodiment of this application, after delay-Doppler domain block encoding is performed at the granularity of sub-block, the delay-Doppler domain information carried on each delay-Doppler domain resource block can be obtained and then transmitted. The specific process of transmission may include: first converting the delayed Doppler information to the time-frequency domain, and then mapping it to a corresponding resource for transmission.
In this embodiment of this application, the transmit end splits a delay-Doppler domain resource block corresponding to each antenna in the L antennas into L sub-blocks of equal size; and the transmit end performs delay-Doppler domain block encoding at the granularity of sub-block to obtain delay-Doppler domain information carried on the delay-Doppler domain resource block. This enables the application of MIMO in the delay-Doppler domain, thereby improving transmission performance.
Optionally, delay-Doppler domain coordinates within each sub-block are continuous or cyclically continuous.
In this embodiment of this application, the delay-Doppler domain coordinates within the sub-block being continuous or cyclically continuous may be understood as the delay domain coordinates and Doppler domain coordinates of grid points within the sub-block being continuous or cyclically continuous. Cyclically continuous may include the delay domain coordinates being cyclically continuous or the Doppler domain coordinates being cyclically continuous. The delay domain coordinates being cyclically continuous may be understood as that one sub-block has two portions in the delay direction, the delay domain coordinates of grid points within each portion are continuous, coordinates of the delay domain grid points within one portion include the maximum delay domain coordinates and coordinates of the grid points in the other portion include the minimum delay domain coordinates. The Doppler domain coordinates being cyclically continuous may be understood as that one sub-block has two portions in the Doppler direction, Doppler domain coordinates of grid points within each portion are continuous, coordinates of grid points within one portion include the maximum Doppler domain coordinates, and Doppler coordinates of grid points in the other portion include the minimum delay domain coordinates.
Optionally, in some embodiments, a direction of splitting the delay-Doppler domain resource block includes at least one of the following: a delay direction and a Doppler direction.
In this embodiment of this application, splitting along one direction is illustrated as an example. For example, when L is equal to 2, a splitting manner is shown in
When L is equal to 4, a splitting manner is shown in
It should be noted that although the order of the sub-blocks shown in the figures is arranged from left to right or from bottom to top, it may actually be other ordering manners, for example, from right to left or from top to bottom, or even lack of order. Therefore, the j-th sub-block in this embodiment of this application is not the j-th sub-block under the sorting modes given in the figures, but may alternatively be the j-th sub-block under any one of specified sorting modes. In other words, the j-th sub-block described above may be understood as the j-th sub-block under a specific logical sorting rule.
Optionally, in some embodiments, that the transmit end performs delay-Doppler domain block encoding at the granularity of sub-block to obtain delay-Doppler domain information carried on the delay-Doppler domain resource block includes:
determining first delay-Doppler domain information carried on part of sub-blocks of L*L sub-blocks; and
performing mapping on the first delay-Doppler domain information based on a mapping relationship of delay-Doppler domain block encoding to obtain second delay-Doppler domain information carried on remaining sub-blocks of the L*L sub-blocks; where
the L*L sub-blocks are all sub-blocks obtained through splitting delay-Doppler domain resource blocks corresponding to the L antennas.
In this embodiment of this application, the antenna may be understood as a physical antenna or an antenna port (for example, two or three physical antennas form one antenna port).
Optionally, in a case that L=2, the part of sub-blocks include a first sub-block and a second sub-block, and the remaining sub-blocks include a third sub-block and a fourth sub-block; where
the first sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna, and the third sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna; and
the second sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna, and the fourth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna.
In this embodiment of this application, the second delay-Doppler domain information S3 carried on the third sub-block meets: S3=S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block; and
the second delay-Doppler domain information S4 carried on the fourth sub-block meets: S4=−S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block.
For example, in some embodiments, delay-Doppler domain information S12 carried on the 2nd sub-block of the 1st antenna and delay-Doppler domain information S11 carried on the 1st sub-block of the 1st antenna may be configured first, and then delay-Doppler domain information S21 carried on the 1st sub-block of the 2nd antenna and delay-Doppler domain information S22 carried on the 2nd sub-block of the 2nd antenna are determined based on a mapping relationship for delay-Doppler domain block encoding. The mapping relationship may meet:
S21=−S12*, where S12*, denotes a conjugate of each element of S12; and S22=S11*, where S11* denotes a conjugate of each element of S11; or
S21=−Ŝ12*, where Ŝ12* denotes a conjugate of each element of Ŝ12, and Ŝ12, is obtained by reordering based on S12; and S22=Ŝ11*, where Ŝ11* denotes a conjugate of each element of Ŝ11*, and Ŝ11* is obtained through reordering based on S11.
Certainly, in other embodiments, a value of the sub-block on the left of the mapping relationship equal sign may alternatively be first determined and then a value of the sub-block on the right of the equal sign is determined based on the mapping relationship.
Optionally, in a case that L=4, the part of sub-blocks include a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block, and the remaining sub-blocks include a fifth sub-block, a sixth sub-block, a seventh sub-block, and an eighth sub-block; where
the first sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna, and the fifth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna;
the second sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna, and the sixth sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna;
the third sub-block is one of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna, and the seventh sub-block is the other of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna; and
the fourth sub-block is one of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna, and the eighth sub-block is the other of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna.
In this embodiment of this application, the second delay-Doppler domain information S5 carried on the fifth sub-block meets: S5=−S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block;
the second delay-Doppler domain information S6 carried on the sixth sub-block meets: S6=S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block;
the second delay-Doppler domain information S7 carried on the seventh sub-block meets: S7=−S3*, where S3* denotes a conjugate of each element of S3, and S3 denotes the first delay-Doppler domain information carried on the third sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the third sub-block; and
the second delay-Doppler domain information S8 carried on the eighth sub-block meets: S8=−S4*, where S4* denotes a conjugate of each element of S4, and S4 denotes the first delay-Doppler domain information carried on the fourth sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the fourth sub-block.
For example, in some embodiments, delay-Doppler domain information S11 carried on the 1st sub-block of the 1st antenna, delay-Doppler domain information S12 carried on the 2nd sub-block of the 1st antenna, delay-Doppler domain information S23 carried on the 3rd sub-block of the 2nd antenna, and delay-Doppler domain information S24 carried on the 4th sub-block of the 2nd antenna may be configured first. Then delay-Doppler domain information S31 carried on the 1st sub-block of the 3rd antenna, delay-Doppler domain information S32 carried on the 2nd sub-block of the 3rd antenna, delay-Doppler domain information S43 carried on the 3rd sub-block of the 4th antenna, and delay-Doppler domain information S44 carried on the 4th sub-block of the 4th antenna are determined based on a mapping relationship for delay-Doppler domain block encoding. The mapping relationship may meet:
S31=−S12*, where S12* is obtained by taking a conjugate based on each element in S12; S32=−S11*, where S11* is obtained by taking a conjugate based on each element in S11; S43=−S24*, where S24* is obtained by taking a conjugate based on each element in S24; S44=−S23*, where Ŝ23* is obtained by taking a conjugate based on each element in S23; or
S31=−S12*, where Ŝ12* is obtained by taking a conjugate based on each element in Ŝ12, and Ŝ12 is obtained by reordering based on S12; S32=−Ŝ11*, where Ŝ11*; is obtained by taking a conjugate based on each element in Ŝ11, and Ŝ11 is obtained by reordering based on S11; S43=−Ŝ24*, where Ŝ24* is obtained by taking a conjugate based on each element in Ŝ24, and Ŝ24 is obtained by reordering based on S24; S44=−Ŝ23*, where Ŝ23* is obtained by taking a conjugate based on each element in Ŝ23, and Ŝ23 is obtained by reordering based on S23.
Certainly, in other embodiments, a value of the sub-block on the left of the mapping relationship equal sign may alternatively be first determined and then a value of the sub-block on the right of the equal sign is determined based on the mapping relationship.
Optionally, in some embodiments, in a case that L=4, second delay-Doppler domain information carried on a ninth sub-block is set to be 0, the ninth sub-block being any one sub-block in the part of sub-blocks other than the first sub-block, the second sub-block, the third sub-block, and the fourth sub-block.
Optionally, in some embodiments, a preset position of at least one of the sub-blocks is set to be a first guard period, the preset position including at least one of the following: a preset delay position and a preset Doppler position.
It should be noted that the i-th antenna can be understood as the i-th antenna defined based on a logical order. Assuming that the antenna in this embodiment of this application is a physical antenna, the 1st antenna can be understood as the 1st antenna in an actual order or can be understood as the m-th antenna in an actual order, m being an integer greater than 1 and a value of m being determined based on a logical order.
In this embodiment of this application, the first guard period meets any one of the following:
the first guard periods are all set to be 0 s;
the first guard period is set to be a cyclic prefix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic suffix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic prefix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located; and
the first guard period is set to be a cyclic suffix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located.
Optionally, a position of providing the first guard period can be set according to actual needs, for example, in some embodiments, the first guard period includes at least one of the following:
a first guard sub-period on at least one boundary of the sub-block in a delay direction; and
a second guard sub-period on at least one boundary of the sub-block in a Doppler direction.
Referring to
Optionally, in some embodiments, a width of the first guard sub-period is greater than or equal to a maximum delay of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, in some embodiments, a width of the second guard sub-period is greater than or equal to twice a maximum Doppler of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, in some embodiments, a pilot is configured in the first guard period.
In this embodiment of this application, the pilot may be a pulse pilot or a sequence pilot. In a case of using pulse pilots, the pilots of all antennas are staggered using delay-Doppler domain resources, as shown in
Optionally, in some embodiments, after the step of performing, by the transmit end, delay-Doppler domain block encoding on the L antennas at the granularity of sub-block, the method further includes:
transforming, by the transmit end, delay-Doppler domain information obtained through delay-Doppler domain block encoding into time-frequency domain information; and
sending, by the transmit end, the time-frequency domain information.
Optionally, before the sending, by the transmit end, the time-frequency domain information, the method further includes:
configuring, by the transmit end, a second guard period for the time-frequency domain information based on a preset time-domain interval.
In this embodiment of this application, the configuring a second guard period for the time-frequency domain information based on a preset time-domain interval may be understood as setting one or more time domain guard periods at intervals of one time domain interval. It can be understood that the second guard period may be that the second guard period is set to be 0, or is set to be a cyclic prefix, or is set to be a cyclic suffix.
Optionally, in some embodiments, target information is determined by the transmit end or specified by a protocol; and the target information includes at least one of the following:
position information of the L sub-blocks;
rules corresponding to the delay-Doppler domain block encoding;
configuration information for a guard period;
pilot position; and
pilot information.
Optionally, in a case that the target information is determined by the transmit end, the method further includes:
sending, by the transmit end, indication information to a receive end, where the indication information is used to indicate the target information.
Optionally, the indication information is carried in at least one of: radio resource control signaling, layer 1 signaling in physical downlink control channel, information in physical downlink shared channel, signaling in a media access control control element, system information block, layer 1 signaling in physical uplink control channel, information 1 in physical random access channel, information 3 in physical random access channel, information A in physical random access channel, information in physical uplink shared channel, Xn interface signaling, PC5 interface signaling, and sidelink interface signaling.
It should be noted that in this embodiment of this application, the indication information may include a plurality of pieces of sub-indication information, and each sub-indication information is used to indicate at least one of the position information of the L sub-blocks, the rule corresponding to delay-Doppler domain block encoding, the configuration information for the guard period, pilot position, and pilot information. The indication information is carried in at least two of the above, each of which may include the same sub-indication information or different sub-indication information.
It should be noted that, for the transmission processing method provided by the embodiments of this application, the execution body may be a transmission processing apparatus, or a control module for executing the transmission processing method in the transmission processing apparatus. In the embodiments of this application, the transmission processing method being performed by the transmission processing apparatus is used as an example to describe the transmission processing apparatus provided in the embodiments of this application.
To better understand this application, a procedure framework of this application is described below with reference to
1. Split the delay-Doppler domain resource block of each antenna into sub-blocks in a same splitting manner.
2. Add the first guard period in the delay-Doppler domain.
3. Add a pilot.
4. Perform delay-Doppler domain block encoding at the granularity of sub-block.
5. Perform OTFS modulation.
6. Add the second guard period in the time-frequency domain.
It should be understood that for specific implementation of each of the above processes, reference may be made to the above embodiments of the transmission processing method, and details will not be repeated herein.
Referring to
a splitting module 2101, configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of a transmit end into L sub-blocks of equal size, L being an integer greater than 1; and
an encoding module 2102, configured to perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
Optionally, delay-Doppler domain coordinates within each sub-block are continuous or cyclically continuous.
Optionally, a direction of splitting the delay-Doppler domain resource block includes at least one of the following: a delay direction and a Doppler direction.
Optionally, the encoding module 2102 includes:
a determining unit, configured to determine first delay-Doppler domain information carried on part of sub-blocks of L*L sub-blocks; and
a mapping unit, configured to perform mapping on the first delay-Doppler domain information based on a mapping relationship of delay-Doppler domain block encoding to obtain second delay-Doppler domain information carried on remaining sub-blocks of the L*L sub-blocks; where
the L*L sub-blocks are all sub-blocks obtained through splitting delay-Doppler domain resource blocks corresponding to the L antennas.
Optionally, in a case that L=2, the part of sub-blocks include a first sub-block and a second sub-block, and the remaining sub-blocks include a third sub-block and a fourth sub-block; where
the first sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna, and the third sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna; and
the second sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna, and the fourth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna.
Optionally, the second delay-Doppler domain information S3 carried on the third sub-block meets: S3=S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block; and
the second delay-Doppler domain information S4 carried on the fourth sub-block meets: S4=−S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block.
Optionally, in a case that L=4, the part of sub-blocks include a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block, and the remaining sub-blocks include a fifth sub-block, a sixth sub-block, a seventh sub-block, and an eighth sub-block; where
the first sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna, and the fifth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna;
the second sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna, and the sixth sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna;
the third sub-block is one of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna, and the seventh sub-block is the other of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna; and
the fourth sub-block is one of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna, and the eighth sub-block is the other of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna.
Optionally, the second delay-Doppler domain information S5 carried on the fifth sub-block meets: S5=−S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block;
the second delay-Doppler domain information S6 carried on the sixth sub-block meets: S6=S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block;
the second delay-Doppler domain information S7 carried on the seventh sub-block meets: S7=−S3*, where S3* denotes a conjugate of each element of S3, and S3 denotes the first delay-Doppler domain information carried on the third sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the third sub-block; and
the second delay-Doppler domain information S8 carried on the eighth sub-block meets: S8=S4*, where S4* denotes a conjugate of each element of S4, and S4 denotes the first delay-Doppler domain information carried on the fourth sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the fourth sub-block.
Optionally, second delay-Doppler domain information carried on a ninth sub-block is set to be 0, the ninth sub-block being any one sub-block in the part of sub-blocks other than the first sub-block, the second sub-block, the third sub-block, and the fourth sub-block.
Optionally, a preset position of at least one of the sub-blocks is set to be a first guard period, the preset position including at least one of the following: a preset delay position and a preset Doppler position.
Optionally, the first guard period meets any one of the following:
the first guard periods are all set to be 0 s;
the first guard period is set to be a cyclic prefix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic suffix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic prefix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located; and
the first guard period is set to be a cyclic suffix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located.
Optionally, the first guard period includes at least one of the following:
a first guard sub-period on at least one boundary of the sub-block in a delay direction; and
a second guard sub-period on at least one boundary of the sub-block in a Doppler direction.
Optionally, a width of the first guard sub-period is greater than or equal to a maximum delay of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, a width of the second guard sub-period is greater than or equal to twice a maximum Doppler of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, a pilot is configured in the first guard period.
Optionally, the transmission processing apparatus 2100 further includes:
a transform module, configured to transform delay-Doppler domain information obtained through delay-Doppler domain block encoding into time-frequency domain information; and
a sending module, configured to send the time-frequency domain information.
Optionally, the transmission processing apparatus 2100 further includes:
a setting module, configured to configure a second guard period for the time-frequency domain information based on a preset time-domain interval.
Optionally, the second guard period is set to be 0, or is set to be a cyclic prefix, or is set to be a cyclic suffix.
Optionally, target information is determined by the transmit end or specified by a protocol; and the target information includes at least one of the following:
position information of the L sub-blocks;
rules corresponding to the delay-Doppler domain block encoding;
configuration information for a guard period;
pilot position; and
pilot information.
Optionally, in a case that the target information is determined by the transmit end, the transmission processing device 2100 further includes: a sending module, configured to send indication information to a receive end, where the indication information is used to indicate the target information.
Optionally, the indication information is carried in at least one of: radio resource control signaling, layer 1 signaling in physical downlink control channel, information in physical downlink shared channel, signaling in a media access control control element, system information block, layer 1 signaling in physical uplink control channel, information 1 in physical random access channel, information 3 in physical random access channel, information A in physical random access channel, information in physical uplink shared channel, Xn interface signaling, PC5 interface signaling, and sidelink interface signaling.
The transmission processing apparatus provided in this embodiment of this application is capable of implementing the processes that are implemented by the method embodiments in
The transmission processing apparatus in this embodiment of this application may be an apparatus, or an apparatus or electric device having an operating system, or may be a component, an integrated circuit, or a chip in the terminal. The apparatus may be a mobile terminal or a non-mobile terminal. For example, the mobile terminal may include but is not limited to the types of the terminal 11 listed above, and the non-mobile terminal may be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, a self-service machine, or the like, which is not specifically limited in this embodiment of this application.
Optionally, as shown in
An embodiment of this application further provides a terminal, including a processor and a communication interface, where the processor is configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of the terminal into L sub-blocks of equal size, L being an integer greater than 1; and perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block. The terminal embodiments correspond to the foregoing terminal-side method embodiments, and the implementation processes and implementations of the foregoing method embodiments can be applied to the terminal embodiments, with the same technical effects achieved. Specifically,
The terminal 2300 includes but is not limited to at least part of components such as a radio frequency unit 2301, a network module 2302, an audio output unit 2303, an input unit 2304, a sensor 2305, a display unit 2306, a user input unit 2307, an interface unit 2308, a memory 2309, and a processor 2310.
Persons skilled in the art can understand that the terminal 2300 may further include a power supply (for example, a battery) supplying power to the components, and the power supply may be logically connected to the processor 2310 through a power management system. In this way, functions such as charge management, discharge management, and power consumption management are implemented by using the power management system. The structure of the terminal shown in
It can be understood that in this embodiment of this application, the input unit 2304 may include a graphics processing unit (GPU) and a microphone. The graphics processing unit processes image data of a still picture or video obtained by an image capture apparatus (such as a camera) in a video capture mode or an image capture mode. The display unit may include a display panel, and the display panel may be configured in a form of a liquid crystal display, an organic light-emitting diode, and the like. The user input unit may include a touch panel and other input devices. The touch panel is also referred to as a touchscreen. The touch panel may include two parts: a touch detection apparatus and a touch controller. The other input devices may include but are not limited to a physical keyboard, a function key (such as a volume control key or a power on/off key), a trackball, a mouse, a joystick, and the like. Details are not described herein.
In this embodiment of this application, the radio frequency unit 2301 receives downlink data from a network-side device, and then sends the downlink data to the processor 2310 for processing; and also sends uplink data to the network-side device. Generally, the radio frequency unit 2301 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
The memory 2309 may be configured to store software programs or instructions and various data. The memory 2309 may include a program or instruction storage area and a data storage area. The program or instruction storage area may store an operating system, an application program or instruction required by at least one function (for example, a sound playback function or an image playback function), and the like. In addition, the memory 2309 may include a high-speed random access memory, and may further include a non-transitory memory. The non-transitory memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), or a flash memory, for example, at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices.
The processor 2310 may include one or more processing units. Optionally, an application processor and a modem processor may be integrated in the processor 2310. The application processor primarily processes an operating system, user interfaces, application programs or instructions, and the like. The modem processor primarily processes radio communication, for example, being a baseband processor. It can be understood that the modem processor may alternatively be not integrated in the processor 2310.
The processor 2310 is configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of the terminal into L sub-blocks of equal size, L being an integer greater than 1; and perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block.
In this embodiment of this application, the delay-Doppler domain resource block corresponding to each antenna in the L antennas of the terminal into L sub-blocks of equal size; and delay-Doppler domain block encoding is performed on the L antennas at the granularity of sub-block. This enables the application of MIMO in the delay-Doppler domain, thereby improving transmission performance.
Optionally, delay-Doppler domain coordinates within each sub-block are continuous or cyclically continuous.
Optionally, a direction of splitting the delay-Doppler domain resource block includes at least one of the following: a delay direction and a Doppler direction.
Optionally, the processor 2310 is specifically configured to determine first delay-Doppler domain information carried on part of sub-blocks of L*L sub-blocks; and perform mapping on the first delay-Doppler domain information based on a mapping relationship of delay-Doppler domain block encoding to obtain second delay-Doppler domain information carried on remaining sub-blocks of the L*L sub-blocks; where
the L*L sub-blocks are all sub-blocks obtained through splitting delay-Doppler domain resource blocks corresponding to the L antennas.
Optionally, in a case that L=2, the part of sub-blocks include a first sub-block and a second sub-block, and the remaining sub-blocks include a third sub-block and a fourth sub-block; where
the first sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna, and the third sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 2nd antenna; and
the second sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna, and the fourth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 2nd antenna.
Optionally, the second delay-Doppler domain information S3 carried on the third sub-block meets: S3=S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block; and
the second delay-Doppler domain information S4 carried on the fourth sub-block meets: S4=−S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block.
Optionally, in a case that L=4, the part of sub-blocks include a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block, and the remaining sub-blocks include a fifth sub-block, a sixth sub-block, a seventh sub-block, and an eighth sub-block; where
the first sub-block is one of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna, and the fifth sub-block is the other of the 2nd sub-block corresponding to the 1st antenna and the 1st sub-block corresponding to the 3rd antenna;
the second sub-block is one of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna, and the sixth sub-block is the other of the 1st sub-block corresponding to the 1st antenna and the 2nd sub-block corresponding to the 3rd antenna;
the third sub-block is one of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna, and the seventh sub-block is the other of the 4th sub-block corresponding to the 2nd antenna and the 3rd sub-block corresponding to the 4th antenna; and
the fourth sub-block is one of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna, and the eighth sub-block is the other of the 3rd sub-block corresponding to the 2nd antenna and the 4th sub-block corresponding to the 4th antenna.
Optionally, the second delay-Doppler domain information S5 carried on the fifth sub-block meets: S5=−S1*, where S1* denotes a conjugate of each element of S1, and S1 denotes the first delay-Doppler domain information carried on the first sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the first sub-block;
the second delay-Doppler domain information S6 carried on the sixth sub-block meets: S6=S2*, where S2* denotes a conjugate of each element of S2, and S2 denotes the first delay-Doppler domain information carried on the second sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the second sub-block;
the second delay-Doppler domain information S7 carried on the seventh sub-block meets: S7=−S3*, where S3* denotes a conjugate of each element of S3, and S3 denotes the first delay-Doppler domain information carried on the third sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the third sub-block; and
the second delay-Doppler domain information S8 carried on the eighth sub-block meets: S8=S4*, where S4* denotes a conjugate of each element of S4, and S4 denotes the first delay-Doppler domain information carried on the fourth sub-block or denotes information obtained by reordering the first delay-Doppler domain information carried on the fourth sub-block.
Optionally, second delay-Doppler domain information carried on a ninth sub-block is set to be 0, the ninth sub-block being any one sub-block in the part of sub-blocks other than the first sub-block, the second sub-block, the third sub-block, and the fourth sub-block.
Optionally, a preset position of at least one of the sub-blocks is set to be a first guard period, the preset position including at least one of the following: a preset delay position and a preset Doppler position.
Optionally, the first guard period meets any one of the following:
the first guard periods are all set to be 0 s;
the first guard period is set to be a cyclic prefix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic suffix in a delay direction for a transmit signal of a sub-block in which the first guard period is located;
the first guard period is set to be a cyclic prefix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located; and
the first guard period is set to be a cyclic suffix in a Doppler direction for a transmit signal of a sub-block in which the first guard period is located.
Optionally, the first guard period includes at least one of the following:
a first guard sub-period on at least one boundary of the sub-block in a delay direction; and
a second guard sub-period on at least one boundary of the sub-block in a Doppler direction.
Optionally, a width of the first guard sub-period is greater than or equal to a maximum delay of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, a width of the second guard sub-period is greater than or equal to twice a maximum Doppler of a target channel, the target channel being a channel for transmitting the delay-Doppler domain information.
Optionally, a pilot is configured in the first guard period.
Optionally, the processor 2310 is further configured to transform delay-Doppler domain information obtained through delay-Doppler domain block encoding into time-frequency domain information; and
the radio frequency unit 2301 is configured to send the time-frequency domain information.
Optionally, the processor 2310 is further configured to configure a second guard period for the time-frequency domain information by the transmit end based on a preset time-domain interval.
Optionally, the second guard period is set to be 0, or is set to be a cyclic prefix, or is set to be a cyclic suffix.
Optionally, target information is determined by the terminal or specified by a protocol; and the target information includes at least one of the following:
position information of the L sub-blocks;
rules corresponding to the delay-Doppler domain block encoding;
configuration information for a guard period;
pilot position; and
pilot information.
Optionally, in a case that the target information is determined by the terminal, the radio frequency unit 2301 is further configured to send indication information to a receive end, where the indication information is used to indicate the target information.
Optionally, the indication information is carried in at least one of: radio resource control signaling, layer 1 signaling in physical downlink control channel, information in physical downlink shared channel, signaling in a media access control control element, system information block, layer 1 signaling in physical uplink control channel, information 1 in physical random access channel, information 3 in physical random access channel, information A in physical random access channel, information in physical uplink shared channel, Xn interface signaling, PC5 interface signaling, and sidelink interface signaling.
An embodiment of this application further provides a network-side device, including a processor and a communication interface, where the processor is configured to split a delay-Doppler domain resource block corresponding to each antenna in L antennas of the network-side device into L sub-blocks of equal size, L being an integer greater than 1; and perform delay-Doppler domain block encoding on the L antennas at the granularity of sub-block. The network-side device embodiments correspond to the foregoing network-side device method embodiments, and the implementation processes and implementations of the foregoing method embodiments can be applied to the network-side device embodiments, with the same technical effects achieved.
Specifically, an embodiment of this application further provides a network-side device. As shown in
The frequency band processing apparatus may be located in the baseband apparatus 2403. The method performed by the network-side device in the foregoing embodiments may be implemented in the baseband apparatus 2403, and the baseband apparatus 2403 includes a processor 2404 and a memory 2405.
The baseband apparatus 2403 may include, for example, at least one baseband board, where a plurality of chips are disposed on the baseband board. As shown in
The baseband apparatus 2403 may further include a network interface 2406, configured to exchange information with the radio frequency apparatus 2402, where the interface is, for example, a common public radio interface (CPRI).
Specifically, the network-side device in this embodiment of this application further includes: instructions or a program stored in the memory 2405 and capable of running on the processor 2404. The processor 2404 invokes the instructions or program in the memory 2405 to execute the method executed by the modules shown in
An embodiment of this application further provides a readable storage medium, where a program or an instruction is stored in the readable storage medium. When the program or instruction is executed by a processor, the processes of the foregoing transmission processing method embodiment can be implemented, with same technical effects achieved. To avoid repetition, details are not described herein again.
The processor is the processor in the electronic device in the foregoing embodiments. The readable storage medium includes a computer-readable storage medium, for example, a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.
An embodiment of this application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or instructions to implement the processes of the foregoing transmission processing method embodiments, with the same technical effects achieved. To avoid repetition, details are not repeated herein.
It should be understood that the chip in the embodiments of this application may also be referred to as a system-level chip, a system chip, a chip system, a system on chip, or the like.
An embodiment of this application further provides a computer program product, where the computer program product is stored in a non-transitory storage medium, and when being executed by at least one processor, the computer program product is configured to implement the processes of the foregoing transmission processing method embodiments, with the same technical effects achieved. To avoid repetition, details are not repeated herein.
It should be noted that in this specification, the term “include”, “comprise”, or any of their variants are intended to cover a non-exclusive inclusion, so that a process, a method, an article, or an apparatus that includes a list of elements not only includes those elements but also includes other elements that are not expressly listed, or further includes elements inherent to such process, method, article, or apparatus. In absence of more constraints, an element preceded by “includes a . . . ” does not preclude existence of other identical elements in the process, method, article, or apparatus that includes the element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in a reverse order depending on the functions involved. For example, the described method may be performed in an order different from the order described, and steps may be added, omitted, or combined. In addition, features described with reference to some examples may be combined in other examples.
According to the description of the foregoing implementations, persons skilled in the art can clearly understand that the method in the foregoing embodiments may be implemented by software in combination with a necessary general hardware platform. Certainly, the method in the foregoing embodiments may alternatively be implemented by hardware. However, in many cases, the former is a preferred implementation. Based on such an understanding, the technical solutions of this application essentially or the part contributing to the prior art may be implemented in a form of a computer software product. The computer software product is stored in a storage medium (such as a ROM/RAM, a magnetic disk, or an optical disc), and includes several instructions for instructing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, a base station, or the like) to perform the methods described in the embodiments of this application.
The foregoing describes the embodiments of this application with reference to the accompanying drawings. However, this application is not limited to the foregoing specific implementations. These specific implementations are merely illustrative rather than restrictive. Inspired by this application, persons of ordinary skill in the art may develop many other forms without departing from the essence of this application and the protection scope of the claims, and all such forms shall fall within the protection scope of this application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110739227.8 | Jun 2021 | CN | national |
This application is a continuation of PCT Application No. PCT/CN2022/101453 filed on Jun. 27, 2022, which claims priority to Chinese Patent Application No. 202110739227.8, filed in China on Jun. 30, 2021, which are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2022/101453 | Jun 2022 | US |
| Child | 18398946 | US |
