Patent Application
20120300680
I. Field
The present disclosure relates generally to communication, and more specifically to techniques for wireless communication.
II. Background
Wireless communication networks are widely deployed to provide various communication services such as voice, video, packet data, messaging, broadcast, etc. These wireless networks may be capable of supporting communication for multiple users by sharing the available network resources. Examples of such wireless networks include wireless wide area networks (WWANs) providing communication coverage for large geographic areas, wireless metropolitan area networks (WMANs) providing communication coverage for medium geographic areas, and wireless local area networks (WLANs) providing communication coverage for small geographic areas.
It may be desirable to improve the coverage of a wireless network. This may be achieved by using radio frequency (RF) repeaters. An RF repeater may receive an RF signal, amplify the received RF signal, and transmit the amplified RF signal. By amplifying the received RF signal, however, interference elements may be amplified as well. Furthermore, noise from circuitry within the RF repeater may be injected in the amplified RF signal and may degrade the desired signal. RF repeaters may thus improve link budget but may cause a loss in network capacity.
Techniques for processing and forwarding transmissions by a relay are disclosed herein. In one aspect, an orthogonal distributed space-time frequency code (DSTFC) scheme may be used to support full-duplex operation and to mitigate self-interference at the relay. In the orthogonal DSTFC scheme, a source node (e.g., a base station) may transmit the same modulation symbol on two subcarriers in one symbol period. The relay may obtain two received symbols from the two subcarriers in the symbol period and may generate two output symbols based on the two received symbols such that the output symbols and the modulation symbol are orthogonal at both the relay and a destination node (e.g., a user equipment).
In another aspect, a distributed Alamouti scheme across frequency may be used to support half-duplex and/or full-duplex operation by the relay. In the distributed Alamouti scheme, the source node may transmit two modulation symbols on two subcarriers in each of two consecutive symbol periods. The relay may obtain two received symbols from the two subcarriers in the first symbol period and may generate two output symbols based on the two received symbols and in accordance with an Alamouti code. The relay may transmit the two output symbols on the two subcarriers in the next symbol period.
In one aspect, the relay may obtain received symbols from a plurality of subcarriers in a first symbol period. The relay may generate output symbols based on the received symbols, without demodulating or decoding the received symbols. The relay may generate the output symbols based on the orthogonal DSTFC scheme or the distributed Alamouti scheme, as described herein. The relay may transmit the output symbols on the plurality of subcarriers in a second symbol period.
In one aspect, the destination node may obtain first received symbols from the plurality of subcarriers in the first symbol period. The destination node may also obtain second received symbols from the plurality of subcarriers in the second symbol period. The first and second received symbols may comprise (i) modulation symbols transmitted on the plurality of subcarriers by the source node and (ii) output symbols transmitted on the plurality of subcarriers by the relay. The destination node may process the first and second received symbols to recover data sent in the modulation symbols by the source node.
Various additional aspects and features of the disclosure are described in further detail below.
The techniques described herein may be used for various wireless communication networks such as WWANs, WMANs, WLANs, etc. The terms “network” and “system” are often used interchangeably. A WWAN may be a Code Division Multiple Access (CDMA) network, a Time Division Multiple Access (TDMA) network, a Frequency Division Multiple Access (FDMA) network, an Orthogonal FDMA (OFDMA) network, a Single-Carrier FDMA (SC-FDMA) network, etc. A CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc. UTRA includes Wideband CDMA (WCDMA), Time Division Synchronous CDMA (TD-SCDMA), and other variants of CDMA. cdma2000 covers IS-2000, IS-95 and IS-856 standards. A TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA network may implement a radio technology such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.20, Flash-OFDM®, etc. UTRA and E-UTRA are part of Universal Mobile Telecommunication System (UMTS). 3GPP Long Term Evolution (LTE) and LTE-Advanced (LTE-A), in both frequency division duplexing (FDD) and time division duplexing (TDD), are recent releases of UMTS that use E-UTRA, which employs OFDMA on the downlink and SC-FDMA on the uplink. UTRA, E-UTRA, UMTS, LTE, LTE-A and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). cdma2000 and UMB are described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). A WLAN may implement one or more standards in the IEEE 802.11 family of standards (which is also referred to as Wi-Fi and Wi-Fi Direct), Hiperlan, etc. A WMAN may implement one or more standards in the IEEE 802.16 family of standards (which is also referred to as WiMAX). The techniques described herein may be used for the wireless networks and radio technologies mentioned above as well as other wireless networks and radio technologies.
Source node 110 may be a base station that communicates with user equipments (UEs), a broadcast station that broadcasts information, or some other transmitter station. A base station may also be referred to as a Node B, an evolved Node B (eNB), an access point, a node, etc.
Relay 120 may be a station that receives transmissions from a source node (e.g., source node 110) and forwards transmissions to a destination node (e.g., destination node 130). Relay 120 may be deployed for a specific purpose to receive and forward transmissions for other nodes. Relay 120 may also be a UE that can receive and forward transmissions for other nodes (e.g., other UEs).
Destination node 130 may be a UE, a broadcast receiver, or some other receiver station. A UE may also be referred to as a mobile station, a terminal, an access terminal, a subscriber unit, a station, a node, etc. A UE may be a cellular phone, a smartphone, a tablet, a wireless communication device, a personal digital assistant (PDA), a wireless modem, a handheld device, a laptop computer, a cordless phone, a wireless local loop (WLL) station, a netbook, a smartbook, etc. Destination node 130 may receive transmissions from source node 110 and may also send transmissions to source node 110. Destination node 130 may receive transmissions from relay 120 (with or without knowledge of destination node 130) and may also send transmissions to relay 120.
As shown in
Wireless network 100 may utilize orthogonal frequency division multiplexing (OFDM) and/or single-carrier frequency division multiplexing (SC-FDM) for transmission. For example, wireless network 100 may be an LTE network that utilizes OFDM for the downlink and SC-FDMA for the uplink. OFDM and SC-PDM partition a frequency range into multiple (NFET) orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers (NFET) may be dependent on the system bandwidth. For example, the subcarrier spacing may be 15 kilohertz (KHz), and NFFT may be equal to 128, 256, 512, 1024 or 2048 for system bandwidth of 1.4, 3, 5, 10 or 20 megahertz (MHz), respectively.
In general, each node in
Relay 120 may operate in a half-duplex (HD) mode and/or a full-duplex (FD) mode. In the half-duplex mode, relay 120 may either transmit or receive (but not both) at any given time. In the full-duplex mode, relay 120 may concurrently receive a transmission from source node 110 and send a transmission to destination node 130. The full-duplex mode may make better use of the available resources and hence may be more desirable than the half-duplex mode. More particularly, the half-duplex mode may use only the backhaul link or the relay link at any given time whereas the full-duplex mode may use both the backhaul link and the relay link simultaneously, thus potentially increasing efficiency by a factor of two. In full-duplex mode, relay 120 typically receives a superposition of a transmission from source node 110 and its own transmission to destination node 130. The disturbance observed by relay 120 due to its own transmission is typically referred to as self-interference. The self-interference may degrade performance.
In one aspect of the disclosure, an orthogonal DSTFC scheme may be used to support the full-duplex mode and to mitigate self-interference at relay 120. In the orthogonal DSTFC scheme, source node 110 may transmit the same modulation symbol on two subcarriers in one symbol period. Relay 120 may obtain two received symbols from the two subcarriers in the symbol period and may generate two output symbols based on the two received symbols such that the output symbols and the modulation symbol are orthogonal at both relay 120 and destination node 130. This orthogonality may reduce interference between the modulation symbol from source node 110 and the output symbols from relay 120. It may also enable relay 120 (and also destination node 130) to recover the modulation symbol from source node 110 as well as the output symbols from relay 120 with a relatively simple receiver, as described below.
As shown in
s
1,i+1
=r
1,i
+r
2,i, and Eq (1)
s
2,i+1
=−r
1,i
−r
2,i
=−s
1,i+1. Eq (2)
As shown in equations (1) and (2), one output symbol s1,i+1 may be equal to the sum of the two received symbols, and the other output symbol s2,i+1 may be equal to the opposite of the sum of the two received symbols, i.e., the negative of s1,i±1. Output symbols s1,i+1 and s2,i+1 may be scaled versions of modulation symbol xi transmitted by source node 110, with the scaling being dependent on the channel gain of the backhaul link from source node 110 to relay 120. Relay 120 may transmit the two output symbols s1,i+1 and s2,i+1 on the two subcarriers in the next symbol period i+1 to destination node 130. Relay 120 may obtain two received symbols r1,i+1 and r2,i+1 on the two subcarriers 1 and 2 in symbol period i+1. These received symbols include self-interference from the two output symbols s1,i+1 and s2,i+1 transmitted by relay 120 on the two subcarriers in symbol period i+1. However, as shown, the self-interference on the two subcarriers differs by sign such that it may be canceled when relay 120 adds up the two received symbols r1,i+1 and r2,i+1 from the two subcarriers in symbol period i+1 to generate output symbols s1,i+2 and s2,i+2, assuming that the channel gain is the same for both subcarriers. In this way, the self-interference terms may be canceled by the processing at relay 120, without the need to know the channel response and/or the self-interfering signal at the relay and also without the need for any active/self interference canceller at relay 120.
The orthogonal DSTFC scheme in
where nr,1 and nr,2 denote the noise at relay 120 on subcarriers 1 and 2, respectively.
In equations (3) and (4), the term h1·xi denotes a desired signal component from source node 110 at relay 120. The terms hr·s1,i and hr·s2,i denote self-interference at relay 120 on subcarriers 1 and 2, respectively.
Relay 120 may recover modulation symbol xi from source node 110 by summing the two received symbols (or r1,i+r2,i), which would result in the output symbols s1,i and s2,i canceling out. Relay 120 may also recover the output symbol s1,i from relay 120 by subtracting the two received symbols (or r1,i−r2,i), which would result in modulation symbol xi transmitted on the two subcarriers canceling out. The orthogonality between the modulation symbols transmitted by source node 110 and the output symbols transmitted by relay 120 can mitigate self-interference at relay 120 and reduce the amount of self-interference forwarded by relay 120 to destination node 130.
The orthogonal DSTFC scheme in
where nd,1 and nd,2 denote the noise at destination node 130 on subcarriers 1 and 2, respectively.
In equations (5) and (6), the term h0·xi denotes a desired signal component from source node 110 at destination node 130. The terms h2·s1,i and h2·s2,i denote desired signal components from relay 120 at destination node 130 on subcarriers 1 and 2, respectively.
Destination node 130 may recover modulation symbol xi from source node 110 by summing the two received symbols (or y1,i+y2,i), which would result in the output symbols s1,i and s2,i canceling out. Destination node 130 may also recover the output symbol s1,i from relay 120 by subtracting the two received symbols (or y1,i−y2,i), which would result in modulation symbol xi transmitted on the two subcarriers canceling out. The orthogonality between the modulation symbols transmitted by source node 110 and the output symbols transmitted by relay 120 enables destination node 130 to extract and combine the desired signal components from source node 110 and relay 120.
Destination node 130 may obtain two received symbols y1,i and y2,i from two subcarriers 1 and 2 in each symbol period. Destination node 130 may determine an estimate of modulation symbol xi transmitted by source node 110 on both subcarriers 1 and 2 in symbol period i based on (i) received symbols y1,i and y2,i from subcarriers 1 and 2 in symbol period i and (ii) received symbols y1,i+1 and y2,i+1 from subcarriers 1 and 2 in the next symbol period i+1, as follows:
where “*” denotes a complex conjugate. Channel gains h0, h1 and h2 are for both subcarriers 1 and 2 for the direct link, the backhaul link, and the relay link, respectively.
In equation (7), the term y1,i+y2,i provides a first estimate of modulation symbol xi based on the desired signal components from source node 110 at destination node 130. The term y1,i+1−y2,i+1 provides an estimate of r1,i+r2,i, which corresponds to a second estimate of modulation symbol xi based on the desired signal components from relay 120 at destination node 130. The two estimates of modulation symbol xi are multiplied by appropriate channel gains, coherently combined, and scaled to obtain a final estimate of modulation symbol xi.
The received symbols at relay 120 may be expressed as:
r=H
1
x+H
r
s+n
r, Eq (8)
where
Equation (8) shows a linear block transmission model in which transmissions are sent in blocks, with each block covering two subcarriers in L symbol periods. L may be equal to 1, 2, 4, or some other value. In general, a transmission may be sent in blocks or in a continuous manner. For a blocked transmission, vector x includes L pairs of modulation symbols transmitted in L symbol periods, with each pair including two identical modulation symbols transmitted on two subcarriers in one symbol period. Vector s includes L pairs of output symbols transmitted in L symbol periods, with each pair including two output symbols transmitted on two subcarriers in one symbol period. Vector r includes L pairs of received symbols in L symbol periods, with each pair including two received symbols from two subcarriers in one symbol period.
Channel matrix Hm, for mε{0, 1, 2, r}, may be expressed as:
is a channel matrix for two subcarriers in one symbol period, and 0 is a matrix of all zeros. Channel matrices Hm and hm are diagonal matrices with possible non-zero elements along the diagonal and zeros elsewhere.
Equation (9) assumes a static channel in a block fading model, with the channel being constant for an entire block of L symbol periods. In this case, each diagonal element of matrix Hm may include matrix hm, and each diagonal element of matrix hm may include channel gain hm. The channel matrices for the direct link, the backhaul link, the relay link, and the transmit-to-receive path at relay 120 may then be expressed as H0=h0I, H1=h1I, H2=h2I, and Hr=hrI, where I is an identity matrix of dimension 2L×2L. For a time-varying channel, the diagonal elements of matrix Hm may include matrices hm,i through hm,i+L−1, and each diagonal element of matrix hm,i may include a channel gain hm,i for one subcarrier in one symbol period i.
The processing at relay 120 may be expressed as:
s=U
r
r, Eq (10)
where Ur is a 2L×2L processing matrix for relay 120 for two subcarriers in L symbol periods.
Processing matrix Ur for the case of L=4 may be expressed as:
where ur is a 2×2 processing matrix for two subcarriers in two symbol periods. Processing matrix Ur includes matrix ur below the main diagonal due to a processing delay of one symbol period.
The output symbols in equation (10) may be expressed as:
Equation (12) shows the output symbols from relay 120 with self-interference. The self-interference at relay 120 may be modeled as (I−Ur Hr)−1. Relay 120 would observe no self-interference if Hr=0, which would result in (I−Ur Hr)−1Ur=Ur. If there is no self-interference at relay 120, then the output symbols may be expressed as:
s=U
r(H1x+nr). Eq (13)
With processing matrix Ur defined as shown in equation (11), self-interference would cancel out if Ur Hr Ur=0. If relay 120 has one transmit antenna and hr is a scalar, then self-interference would cancel out if ur ur=0. This condition may be satisfied by defining matrix ur as follows:
U
r
=v
0
v
1
H, Eq (14)
where
If relay 120 has multiple transmit antennas and hr is non-scalar, then matrix ur may be defined as follows:
u
r=(v0v1H){circle around (x)}Pr, Eq (15)
where
Matrix ur may be defined based on various unitary matrices so that self-interference can be canceled out. In a first design, matrices ur and V may be defined as follows:
The first design corresponds to the orthogonal DSTFC scheme shown in
In the first design, processing matrix Ur at relay 120 for the case of L=4 may be expressed as:
In a second design, matrices ur and V may be defined as follows:
The second design corresponds to a transmission scheme in which source node 110 transmits a modulation symbol on one subcarrier (e.g., subcarrier 2). Relay 120 generates an output symbol based on a received symbol from this one subcarrier and transmits the output symbol on another subcarrier (e.g., subcarrier 1). Matrices ur and V may also be defined based on other designs such that self-interference cancels out at relay 120. Since self-interference is not forwarded by relay 120, advantageously, there may be no need for complicated gain control of a transmission from relay 120.
Source node 110 may generate vector x as follows:
x=U
s
z, Eq (23)
where
If source node 110 includes one transmit antenna, then processing matrix Us may be expressed as:
U
s
=I{circle around (x)}v
1. Eq (24)
For example, if vector v1 is defined as shown in equation (16) and L=4, then processing matrix Us may be expressed as:
Processing matrix Us in equation (25) corresponds to the orthogonal DSTFC scheme shown in
If source node 110 includes multiple transmit antennas, then processing matrix Us may be expressed as:
U
s
=I{circle around (x)}v
1
{circle around (x)}P
s, Eq (26)
where Ps is a spatial processing matrix (i.e., a precoding matrix) for source node 110.
The above equations indicate that vector v1 is used by both source node 110 to generate modulation symbols and by relay 120 to generate output symbols. However, relay 120 further uses vector v0 to obtain orthogonality. Processing matrix Ur for relay 120 may be dependent on vector v1 used by source node 110 and vector v0 used by relay 120 to obtain orthogonality.
The received symbols at destination node 130 may be expressed as:
where
H
eff=(H2(I−UrHr)−1UrH1+H0)Us. Eq (28)
The effective channel matrix includes the direct link, the backhaul link, and the relay link. Vector y includes L pairs of received symbols in L symbol periods, with each pair including two received symbols from two subcarriers in one symbol period.
An estimated channel matrix Hest may be expressed as:
H
est=(H2UrH1+H0)Us. Eq (29)
Destination node 130 may determine the estimated channel matrix based on an estimate of H0, an estimate of H2 Ur H1, and known Ur and Us. Destination node 130 may estimate H0 based on a reference signal or pilot sent by source node 110. Destination node 130 may estimate H2 Ur H1 based on the reference signal sent by source node 110 and forwarded by relay 120, without requiring any special processing by relay 120. The estimated channel matrix may be equal to the effective channel matrix if there is no self-interference and Hr=0. For simplicity, equation (29) assumes no channel estimation errors.
The product of the estimated channel matrix and the effective channel matrix, with no self-interference, may be expressed as:
and gr and gs are scalars.
If source node 110 includes a single transmit antenna, then scalars gr and gs may be expressed as:
g
r
=|h
0|2+|h1|2·|h2|2, and Eq (31)
g
s
=|h
0|2. Eq (32)
If source node 110 and relay 120 include multiple transmit antennas, then scalars gr and gs in matrices R and S may be replaced with matrices Gr and Gs, which may be expressed as:
G
r
=P
s
H(h0Hh0+h2HPrHh1Hh1Prh2)Ps, and Eq (33)
G
s
=P
s
H(h0Hh0)Ps, Eq (34)
where h0, h1 and h2 are channel vectors or matrices for the direct link, the backhaul link, and the relay link, respectively.
As shown in equation (30), the product HestH Heff is a diagonal matrix that includes L−1 matrices R and one matrix S along the diagonal when there is no self-interference. HestH Heff indicates that destination node 130 may receive the last modulation symbol from only source node 110 (due to a block transmission model) and may receive other modulation symbols from both source node 110 and relay 120.
The received symbols at destination node 130 may be processed in various manners to obtain estimates of the modulation symbols transmitted by source node 110. In one design, a matched filter Mmf may be defined based on the estimated channel matrix, as follows:
M
mf
=H
est
H. Eq (35)
Matched filtering may be performed on the received symbols at destination node 130, as follows:
{circumflex over (x)}
mf
=M
mf
y, Eq (36)
where {circumflex over (x)}mf is a L×1 vector of detected symbols in L symbol periods. The detected symbols are estimates of the modulation symbols transmitted in L symbol periods.
Since HestH Heff is a diagonal matrix, matched filtering may ensure that there is no crosstalk between different modulation symbols and a symbol-wise detector returns a maximum likelihood (ML) decision. A low complexity ML detector may thus be implemented with a matched filter followed by a symbol-wise detector.
In another design, a minimum mean square error (MMSE) filter Mmmse may be defined based on the estimated channel matrix, as follows:
M
mmse=(HestHHest+E{neffneffH})−1HestH, Eq (37)
where E{ } denotes an expectation.
The effective noise neff may be expressed as:
n
eff
=H
2(I−UrHr)−1Urnr+nd. Eq (38)
Destination node 130 may be informed of the noise nr at relay 120 and may compute the effective noise neff based on its noise nd and the relay noise nr. If the relay noise is not available, then destination node 130 may compute E{nd ndH} based on its noise nd and may use E{nd ndH} to compute the MMSE filter.
MMSE filtering may be performed on the received symbols at destination node 130, as follows:
{circumflex over (x)}
mmse
=M
mmse
Y, Eq (39)
where is {circumflex over (x)}mmse a L×1 vector of detected symbols in L symbol periods.
In another aspect of the disclosure, a distributed Alamouti scheme across frequency may be used to support the half-duplex mode. In this transmission scheme, source node 110 may transmit two modulation symbols on two subcarriers in each of two consecutive symbol periods. Relay 120 may obtain two received symbols from the two subcarriers in the first of the two symbol periods and may generate two output symbols based on the received symbols and in accordance with an Alamouti code. Relay 120 may then transmit the two output symbols on the two subcarriers in the second of the two symbol periods. The output symbols may also be referred to as Alamouti-encoded symbols.
In the distributed Alamouti scheme, relay 120 may operate in the half-duplex mode, may receive modulation symbols from source node 110 during odd-numbered symbol periods, and may transmit output symbols to destination node 130 during even-numbered symbol periods. The processing by relay 120 may ensure that destination node 130 can receive Alamouti-encoded symbols from the two subcarriers in the two symbol periods. This can provide orthogonality between the modulation symbols transmitted by source node 110 and the output symbols transmitted by relay 120 at destination node 130. Destination node 130 may be able to obtain estimates of the modulation symbols independently based on a transmission from source node 110 and a transmission from relay 120.
As the example of
s
i
=−r
i±1*, and Eq (40)
s
i+1
=r
i*. Eq (41)
Relay 120 may transmit the two output symbols si and si+1 on the two subcarriers in the next symbol period i+1. Relay 120 may receive modulation symbols from source node 110 during odd-numbered symbol periods and may transmit output symbols to destination node 130 during even-numbered symbol periods. The output symbols transmitted in each symbol period are processed versions of the received symbols in the preceding symbol period.
Destination node 130 may obtain two received symbols y1,i and y2,i from two subcarriers 1 and 2 in symbol period i and may obtain two received symbols y1,i+1 and y2,i+1 from the two subcarriers 1 and 2 in symbol period i+1. Destination node 130 may determine estimates of modulation symbols xi and xi+1 transmitted by source node 110 based on the four received symbols y1,i, y2,i, y1,i+1 and y2,i+1, as follows:
In equation (42), the term y1,i+y1,i+1 provides a first estimate of modulation symbol xi based on desired signal components from source node 110 at destination node 130. The term y2,i+1 provides a second estimate of modulation symbol xi based on desired signal components from relay 120 at destination node 130. The two estimates of modulation symbol xi are multiplied by appropriate channel gains, coherently combined, and scaled to obtain a final estimate of modulation symbol xi. An estimate of modulation symbol xi+1 may be obtained in similar manner, as shown in equation (43).
In the distributed Alamouti scheme, the processing at relay 120 may ensure that destination node 130 observes Alamouti-encoded symbols across the two subcarriers. Destination node 130 may be able to determine estimates of modulation symbols xi and xi+1 independently due to the orthogonality provided by the Alamouti code.
In yet another aspect of the disclosure, a distributed Alamouti scheme across frequency may be used to support the full-duplex mode. In this transmission scheme, source node 110 may transmit two modulation symbols on two subcarriers in each of two consecutive symbol periods. The channel may be assumed to be static over the two symbol periods. Relay 120 may obtain two received symbols from the two subcarriers in one symbol period and may generate two output symbols based on the two received symbols. Relay 120 may then transmit the two output symbols on the two subcarriers in the next symbol period.
As shown in
s
2i−1
=−r
2i*, and Eq (44)
s
2i
=r
2i−1*. Eq (45)
Relay 120 may transmit the two output symbols s2i−1 and s2i on the two subcarriers in the next symbol period i+1.
Destination node 130 may obtain two received symbols y1,i and y2,i from two subcarriers 1 and 2 in symbol period i. Neglecting self-interference at relay 120, orthogonality may be preserved in even-numbered symbol periods. However, there may be crosstalk between certain symbols in odd-numbered symbol periods. The received symbols may be processed based on an MMSE receiver, a trellis-based receiver, or some other type of receiver to obtain estimates of the modulation symbols transmitted by source node 110.
A plot 510 shows the performance of the distributed Alamouti scheme for the half-duplex mode in
A plot 530 shows the performance of the orthogonal DSTFC scheme for the full-duplex mode in
The orthogonal DSTFC scheme may provide the following advantages:
It will be recognized that the transmission schemes described herein differ in several respects from conventional DSTC and DSTFC schemes. For example, with the transmission schemes described herein, the source node and the relay transmit their symbols on the same set of subcarriers whereas, in conventional DSTC and DSTFC schemes, the source node and the relay transmits their symbols on different overlapping sets of subcarriers. Furthermore, the DSTC and DSTFC schemes are limited to the half-duplex mode whereas the transmission schemes in
In one design, the relay may operate in a full-duplex mode and may concurrently receive and transmit on the plurality of subcarriers in each of a plurality of symbol periods including the first and second symbol periods, e.g., as shown in
In another design, the relay may operate in a half-duplex mode and may either receive or transmit on the plurality of subcarriers in each of the plurality of symbol periods, e.g., as shown in
In one design, the orthogonal DSTFC scheme in
In the orthogonal DSTFC scheme, the relay may generate two output symbols s1,2 and s2,2 based on two received symbols r1,1 and r2,1 from two subcarriers in the first symbol period, e.g., as shown in equations (1) and (2). The relay may generate each output symbol based on a sum of the two received symbols from the two subcarriers in the first symbol period. One of the two output symbols may be a negative of the other one of the two output symbols. For example, the relay may obtain a first received symbol r1,1 from a first subcarrier in the first symbol period and may obtain a second received symbol r2,1 from a second subcarrier in the first symbol period. The relay may generate a first output symbol s1,2 based on a sum of the first and second received symbols, as shown in equation (1), and may generate a second output symbol s2,2 based on a negative of the sum of the first and second received symbols, as shown in equation (2). The relay may transmit the first output symbol on the first subcarrier in the second symbol period and may transmit the second output symbol on the second subcarrier in the second symbol period.
In general, for the orthogonal DSTFC scheme, the relay may generate output symbols based on a unitary matrix V selected to reduce/mitigate self-interference at the relay. A processing matrix ur may be defined based on the unitary matrix V, e.g., as shown in equation (14) or (15). The relay may generate the output symbols based on the received symbols and the processing matrix ur, e.g., as shown in equations (10) and (11). The relay may generate the output symbols to be orthogonal to the modulation symbols transmitted by the source node at the relay and also at a destination node receiving transmissions from the source node and the relay.
In another design, the distributed Alamouti scheme for the half-duplex mode in
In the distributed Alamouti scheme for the half-duplex mode in
For the distributed Alamouti scheme for the full-duplex mode in
Advantageously, in each of the transmission schemes described herein, the relay may generate the output symbols without using a channel estimate. The relay may generate output symbols for a single transmit antenna at the relay, as described above. Alternatively, the relay may precode the output symbols based on a precoding matrix to send each output symbol from a plurality of antennas at the relay.
In one design, the orthogonal DSTFC scheme in
In one design of block 716 for the orthogonal DSTFC scheme, the destination node may determine an estimate of the modulation symbol x1 based on a sum of two first received symbols (e.g., received symbols y1,1 and y2,1 in
In another design of block 716 for the orthogonal DSTFC scheme, the destination node may determine a filter matrix based on a channel matrix, e.g., as shown in equation (35). The destination node may also determine the filter matrix based further on a noise estimate and in accordance with a MMSE criterion, e.g., as shown in equation (37). The destination node may determine estimates of modulation symbols transmitted by the source node based on the filter matrix and the first and second received symbols, e.g., as shown in equation (36) or (39).
In another design, the distributed Alamouti scheme in
In one design of block 716 for the distributed Alamouti scheme, the destination node may determine estimates of two modulation symbols (e.g., modulation symbols x1 and x2) based on two first received symbols (e.g., received symbols y1,1 and y2,1) obtained from the two subcarriers in the first symbol period and two second received symbols (e.g., received symbols y1,2 and y2,2) obtained from the two subcarriers in the second symbol period, e.g., as shown in equations (42) and (43). In another design of block 716 for the distributed Alamouti scheme, the destination node may determine estimates of modulation symbols based on the received symbols using an ML receiver, an MMSE receiver, a trellis-based receiver, or some other type of receiver.
Within relay 120x, a receiver 820 may receive the source signal transmitted by source node 110x and a relay signal transmitted by relay 120x and may provide one or more received signals. A module 822 may determine received symbols based on the received signal(s) from receiver 820. A module 824 may generate output symbols based on the received symbols, as described above. A module 826 may generate a transmission comprising the output symbols, reference symbols, etc. A transmitter 828 may generate the relay signal comprising the transmission being sent by relay 120x. A controller/processor 830 may direct the operation of various modules within relay 120x. A memory 832 may store data and program codes for relay 120x.
Within destination node 130x, a receiver 840 may receive the source signal transmitted by source node 110x and the relay signal transmitted by relay 120x and may provide one or more received signals. A module 842 may determine received symbols based on the received signal(s) from receiver 840. A module 844 may determine estimates of the modulation symbols transmitted by source node 110x, as described above. A module 846 may process (e.g., decode) the estimates of the modulation symbol to recover data sent by source node 110x to destination node 130x. A controller/processor 848 may direct the operation of various modules within destination node 130x. A memory 850 may store data and program codes for destination node 130x.
At source node 110y, a transmit processor 910 may receive data to transmit and may process (e.g., encode and modulate) the data in accordance with a selected modulation and coding scheme (MCS) to obtain modulation symbols. Processor 910 may also process control information to obtain control symbols. Processor 910 may multiplex the modulation symbols, the control symbols, and reference symbols (e.g., on different subcarriers and/or in different symbol periods). Processor 910 may further process the multiplexed symbols (e.g., for OFDM, SC-FDMA, etc.) to generate output samples. A transmitter (TMTR) 912 may condition (e.g., convert to analog, amplify, filter, and upconvert) the output samples to generate a source signal, which may be transmitted to relay 120y and destination node 130y.
At relay 120y, a receiver (RCVR) 936 may receive the source signal from source node 110y. Receiver 936 may condition (e.g., filter, amplify, downconvert, and digitize) the received signal and provide received samples. A receive processor 938 may process the received samples to obtain received symbols from different subcarriers. A transmit processor 930 may generate output symbols based on the received symbols and in accordance with any of the transmission schemes described above. A transmitter 932 may condition the output symbols from processor 930 and generate a relay signal, which may be transmitted to destination node 130y.
At destination node 130y, the source signal from source node 110y and the relay signal from relay 120y may be received and conditioned by a receiver 952 and further processed by a receive processor 954 to obtain estimates of the modulation symbols transmitted by source node 110y. Processor 954 may derive channel estimates, derive a filter matrix, and perform filtering of the received symbols with the filter matrix. Processor 954 may further process (e.g., demodulate and decode) the estimates of the modulation symbols to recover the data and control information sent by source node 110y.
Controllers/processors 920, 940 and 960 may direct operation at source node 110y, relay 120y, and destination node 130y, respectively. Controller/processor 940 at relay 120y may perform or direct process 600 in
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, or digital subscriber line (DSL), then the coaxial cable, fiber optic cable, twisted pair, or DSL are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present application claims priority to provisional U.S. Application Ser. No. 61/491,108, entitled “SIGNAL PROCESSING FOR FULL-DUPLEX RELAY,” filed May 27, 2011, and incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61491108 | May 2011 | US |
