Patent Application
20190058497
The field of this invention relates to a transmitter, a communication unit and a method for pre-distortion calibration, and in particular to methods for controlling or reducing harmonic distortion during a calibration training mode of operation.
A primary focus and application of the present invention is the field of transmitters and radio frequency (RF) power amplifiers capable of use in wireless telecommunication applications. Continuing pressure on the limited spectrum available for radio communication systems is forcing the development of spectrally-efficient linear modulation schemes. Since the envelopes of a number of these linear modulation schemes fluctuate, these result in the average power delivered to the antenna being significantly lower than the maximum possible power, leading to poor efficiency of the power amplifier. Specifically, in this field, there has been a significant amount of research effort in developing high-power efficient topologies capable of providing useful performance in the ‘back-off’ (linear) region of the power amplifier.
Linear modulation schemes require linear amplification of the modulated signal in order to minimise undesired out-of-band emissions from spectral re-growth. However, the active devices used within a typical RF power amplifier are inherently non-linear by nature. Only when a small portion of the consumed direct current (DC) power is transformed into RF power, can the transfer function of the amplifying device be approximated by a straight line, i.e. as in an ideal linear amplifier. This mode of operation provides a low efficiency of DC to RF power conversion.
Additionally, the emphasis in portable (subscriber) equipment is to increase battery life. To achieve both linearity and efficiency, so called linearization techniques are used to improve the linearity of the more efficient amplifier classes, for example class ‘AB’, ‘B’ or ‘C’ amplifiers. A number and variety of linearizing techniques exist, such as Cartesian Feedback, Feed-forward, and Adaptive Digital Pre-distortion (DPD), which are often used when designing linear transmitters.
In order to increase the bit rate used in transmit uplink communication channels, larger constellation modulation schemes, with an amplitude modulation (AM) component are being investigated and, indeed, becoming required. These modulation schemes, such as sixteen-bit quadrature amplitude modulation (16-QAM), require linear PAs and are associated with high ‘crest’ factors (i.e. a degree of fluctuation) of the modulation envelope waveform. This is in contrast to the previously often-used constant envelope modulation schemes and can result in significant reduction in power efficiency and linearity.
To help overcome such efficiency and linearity issues, for various communications standards, a number of techniques have been proposed.
Referring to
In this manner, a linear transmitter signal is output from the power amplifier, with the inherent non-linearity effects that would have been created cancelled out by the DPD applied by the DPD compensation circuit 215.
As illustrated, the block diagram 200 of the known transmitter architecture includes a frequency generation circuit that, typically, includes a phase locked loop 260 that generates the RF frequency that is used for up-conversion of the pre-distorted digital training signal (Xref) 210 to a radio frequency in RF modulator 220 and the same RF frequency that is used for down-conversion of the fed-back RF representation of the pre-distorted digital training signal (Xref) 210 to a baseband signal in RF demodulator 235. As the RF signal output from the PLL 260 inevitably has some harmonic content, this signal includes (at least) a fundamental carrier signal (fRF) and a 3rd harmonic of (3fRF). Typically, the DPD digital training signal (Xref) 210 is a baseband ramp signal with, say, a frequency=fBB. Hence, when this PLL (local oscillator (LO) signal) of: fRF+3fRF+5fRF+ . . . is mixed with the digital training signal (Xref) 210, the output from the RF modulator 220 is of a form of:
xLO (where the frequency is fRF+fBB)+x3LO (where the frequency is 3fRF+fBB)+x5LO (where the frequency is 5fRF+fBB)+ . . . [1]
After the generated RF signal of the pre-distorted digital training signal (Xref) 210 is amplified by the power amplifier, the output power amplified signal is of a form of:
[The fundamental frequency components of] (fRF+fBB)+a third harmonic distortion component (HD3) of 3fRF+3fBB, (as x3LO is attenutated by the PA gain/frequency response)+HD5 (where the frequency is 5fRF+5fBB)+ . . . [2]
The calibration circuit (engine) 250 determines PA nonlinearity by measuring nfBB (n:odd integer), where the PA's 3rd order distortion at a frequency of 3fRF+3fBB can mix with the PLL's 3fRF frequency and down convert to a baseband frequency of: 3fBB. The inventors of the present invention have recognized and appreciated that this may have the disadvantage that the PA's 3rd order distortion at a frequency of 3fRF+3fBB has a negative impact on, and, thus, interferes with the desired signal and affects the stored DPD compensation values.
In order to meet the transmitter requirements, such as output power spectrum requirement limits and error vector magnitude, such as those illustrated in
U.S. Pat. No. 8,498,591 describes a technique to implement DPD compensation that uses a low bit modulation (quadrature phase shift keyed (QPSK), 16-level quadrature amplitude modulation (16QAM) modulation schemes. With these less-complex modulation schemes, the interference from harmonics is insufficient to cause problems in meeting the required linearity performance.
However, a number of recently proposed communication systems utilize highly complex modulation schemes, such as 1024QAM or 256QAM. The inventors have recognized and appreciated that for these higher and more complex modulation schemes, the linearity requirements are much more severe and therefore impact of the harmonic distortion content of the PLL is likely to cause a problem.
Thus, there exists a need for a more efficient and cost effective solution to control spectral re-growth and reduce harmonic distortion in RF transmitters, particularly for RF transmitters that employ linearization techniques such as DPD.
Accordingly, the invention seeks to mitigate, alleviate or eliminate one or more of the above mentioned disadvantages singly or in any combination.
According to aspects of the invention, there is described a communication unit having a transmitter and a method of harmonic distortion reduction. The transmitter is configured to operate in a training mode of operation and a normal transmission mode of operation. The transmitter includes a signal generator arranged to generate a digital baseband signal that is representative of a signal for transmission; a digital predistortion (DPD) circuit configured to predistort the digital baseband signal; a first frequency shift circuit operably coupled to the DPD circuit and configured to frequency shift the signal for transmission in a first frequency direction; where the frequency-shifted signal is then transmitted to a power amplifier. A feedback path is coupleable to an output of the power amplifier and configured to route a portion of the power amplified predistorted signal to a second frequency shift circuit that is configured to frequency shift the fed back portion of a power amplified predistorted signal in a second frequency direction that is substantially equal to and opposite to the first frequency direction. A calibration engine, located in the feedback path and coupled to the signal generator, is arranged to receive and compare the digital baseband signal representative of a signal for transmission with the fed back portion of the power amplified predistorted signal shifted in the second frequency direction, wherein the calibration engine is configured to determine at least one DPD compensation value to apply to the DPD circuit during a training mode of operation and wherein the first frequency shift circuit and second frequency shift circuit apply the frequency shift in a first direction and a second frequency direction opposite to the first frequency direction only in the training mode of operation.
In this manner, a transmitter architecture that uses a DPD circuit is described whereby the effect of harmonic distortion from one or more of various components in the transmitter line-up can be determined by applying a frequency shift to a transmit signal in a training mode of operation, which is removed from a feedback portion of the signal to be transmitted by a reverse frequency shift in a feedback path.
In an optional example embodiment, the first frequency shift circuit and second frequency shift circuit comprise single sideband mixers configured to receive a frequency shift signal and the signal for transmission and generate a frequency shifted signal for transmission on a single sideband of the signal for transmission. In this optional example embodiment, the use of SSB mixers removes a possibility of image signals being generated that may interfere with the desired signal.
In an optional example embodiment, the first frequency shift circuit is located before the DPD circuit in a transmitter path. In this optional example embodiment, the location of the first frequency shift circuit, for example using a first SSB mixer, before the DPD circuit in a transmitter path. Alternatively, in an optional example embodiment, the first frequency shift circuit is located after the DPD circuit in a transmitter path. In this optional example embodiment, the location of the first frequency shift circuit, for example using a first SSB mixer, after the DPD circuit in a transmitter path enables, in some examples, for the DPD clock frequency to be lower if the frequency shift of the SSB is large.
In an optional example embodiment, the feedback path further comprises a filter located between the second frequency shift circuit and the calibration engine. In this optional example embodiment, the location of the filter between the second frequency shift circuit and the calibration engine may remove the signal related to the transmitter third harmonic distortion component HD3.
In an optional example embodiment, the frequency shift circuits are bypassed in the normal transmission mode of operation. In this optional example embodiment, the ability to bypass the frequency shift circuits in the normal transmission mode of operation may avoid an increase in the DAC clock frequency.
In an optional example embodiment, the transmitter further includes a radio frequency modulator comprising at least one low pass filter, LPF, coupled to at least one mixer in a forward path and a radio frequency demodulator located in the feedback path. In this optional example embodiment, when the frequency shift of SSB mixer is large, the training (calibration) signal may be attenuated significantly by the LPF. A use of a bypass circuit to bypass the LPF in a training mode of operation or an extension of the LPF cutoff frequency may be used to keep the signal level high.
In an optional example embodiment, the transmitter forward path may include a pre-emphasis filter located before the RF demodulator, wherein the pre-emphasis filter is configured to compensate for a frequency response applied to the transmit signal by the RF demodulator. In this optional example embodiment, the ability to compensate for a frequency response applied to the transmit signal by the RF demodulator using a pre-emphasis filter may also attenuate the signal. Again, a use of a bypass circuit to bypass the LPF in a training mode of operation or an extension of the LPF cutoff frequency may be used to keep the signal level high.
These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter.
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the FIGs are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Examples of the invention will be described in terms of various circuits configured to determine DPD compensation values during a calibration training mode of operation to reduce harmonic distortion, for examples as used in a wireless communication unit, such as an user equipment (UE) in Long Term Evolved (LTE™) that employs a digital predistortion circuit. However, it is envisaged that the harmonic distortion reduction concepts herein described may be applicable in any situation or system or communication unit where harmonic control is desired.
In examples of the invention, DPD calibration is performed and in some examples it may be initiated either in a factory set-up, or following power-on of a communication unit, or in response to an operational or environmental change, such as a temperature change, whereby a DPD training signal is used to determine the appropriate transmitter linearization values (i.e. DPD compensation values) to use. In a DPD normal transmission mode of operation, sometimes referred to as a compensation phase, the transmitter outputs the modulation signal that can be compensated by the DPD circuit using the DPD compensation values to reduce the effect of distortion of the transmit signal, i.e. once the transmitter has been calibrated and any associated transmitter performance parameters or circuits adjusted accordingly as obtained during a training mode of operation. The approach to reducing the impact to DPD calibration accuracy by addressing harmonic distortion, and in particular a third harmonic distortion content of a generated signal has not previously been considered in a complex linear transmitter architecture, such as a transmitter employing a DPD circuit, as the modulation schemes previously employed in linearized transmitter systems were less complex, typically with fewer levels, and therefore less affected by harmonic distortion content of a generated signal.
Examples of the invention provide a first frequency shift in a transmitter forward path and a corresponding reverse frequency shift in a feedback path to enable harmonic distortion by the power amplifier to be identified and reduced. This architecture shifts the desired signal and the related third harmonic distortion signal to a different frequency. In some examples, a low pass filter (LPF) in the feedback path may be used to reduce or remove the third order harmonic distortion signal at the calibration engine input to improve the calibration engine accuracy. Some examples of the invention propose, in a calibration training mode of operation, to use a single sideband (SSB) mixer in both the transmitter forward path and the feedback path and which are used to impart a frequency shift of a transmit signal as applied to a power amplifier (and a feedback signal to impart a reverse frequency shift) in order to determine and compensate harmonic distortion content introduced by the PLL and exacerbated by the power amplifier. Thereafter, in some examples and in a normal transmission mode of operation, examples of the invention propose to bypass the SSB mixers when transmitting real signals.
Furthermore, because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated below, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Referring now to
A controller 314 maintains overall operational control of the wireless communication unit 300. The controller 314 is coupled to the receiver front-end circuitry 306 and the signal processing module 308. In some examples, the controller 314 is also coupled to a buffer module 317 and at least one memory device 316 that selectively stores data relating to operating functions, such as information relating to DPD gains, look-up-table information (say for a DPD), harmonic distortion levels, frequency shift values and programmable filter parameters to impart an associated filter response, and the like. A timer 318 is operably coupled to the controller 314 to control the timing of operations (e.g. transmission or reception of time-dependent signals) within the wireless communication unit 300.
The transmit chain includes transmitter/modulation circuitry 322 and a power amplifier 324 coupled to the antenna arrangement 302, which may comprise for example an antenna array, or plurality of antennas. The transmitter/modulation circuitry 322 and the power amplifier 324 are operationally responsive to the controller 314. In some examples, the signal processing module 308 and/or controller 314 may receive inputs from one or more input device or sensor modules 320. Frequency generation circuit 328 includes at least one local oscillator, LO, 327 and is operably coupled to the receiver front-end circuitry 306 and the transmitter/modulation circuitry 322 and arranged to provide local oscillator signals 329 thereto.
In example embodiments, the transmit chain includes a first frequency shift circuit 321, which may be located in transmitter/modulation circuitry 322 or within the signal processor 308, or any other suitable circuit, as shown. In some examples herein described, the first frequency shift circuit 321 may encompass or be operably coupled to DPD functionality with a DPD look-up-table (LUT), as described in later figures. In example embodiments, signal processor 308 generates a digital signal, such as a DPD digital training signal that is routed through the transmitter/modulation circuitry 322, frequency shifted by first frequency shift circuit 321 and converted to analog form in a digital-to analog converter (DAC), typically located in transmitter/modulation circuitry 322 and routed through a power amplifier 324, such that the output signal 325 is an amplified analog representation of the DPD digital training signal. In some examples, the first frequency shift circuit 321 may be located within the transmitter/modulation circuitry 322 and in some examples the first frequency shift circuit 321 may be located elsewhere, e.g. in, or coupled to, the signal processor 308, with the specific location dependent upon the desired architecture.
A portion 326 of the output signal 325 is routed back to a second frequency shift circuit 331 configured to apply a reverse frequency shift to the frequency shift imparted on the DPD digital training signal in the forward path and converted back to digital form in down-converter and analog-to-digital converter (ADC) 350. The first frequency shift circuit 321 is configured to apply frequency shifting of a training signal to determine harmonic distortion introduced in to the transmitter, in particular a 3rd order harmonic distortion content introduced for example by a phase locked loop (PLL) frequency generation circuit, in accordance with any one or more of the examples herein described with reference to
In some examples, the second frequency shift circuit 331 may be located within the down-converter and ADC 350, which may be referred to as an RF demodulator, and in some examples the second frequency shift circuit 331 may be located elsewhere, e.g. in, or coupled to, the signal processor 308, with the specific location dependent upon the desired architecture.
Clearly, a number of the various components within the wireless communication unit 300 can be realized in discrete or integrated component form, with an ultimate structure therefore being application-specific or design-based.
In this example, a signal generator 405 generates a DPD digital training signal (Xref) 410 that is routed through the transmitter circuit. In this example, an intermediate frequency, fIF, is introduced into the DPD digital training signal (Xref) 410 via a first single sideband (SSB) mixer 412, which outputs a transmit frequency-shifted training signal of fBB+fIF.
In some examples a SSB mixer is proposed as this circuit component may avoid generating interference by the PA 324 due to 3rd harmonics, and only generates a frequency shift and does not generate an additional tone. It is envisaged in other examples that a SSB mixer may be replaced by other frequency conversion components, such as a double sideband mixer, although in this case the circuit would need to be designed to attenuate any other mixed signals that were generated.
The transmit training signal of fBB+fIF is input to the digital predistorter 415, where the digital components (amplitude and phase) of the training signal are (pre-)distorted. In this example transmitter architecture, the output pre-distorted training signal is input to an optional pre-emphasis circuit 417, which is employed in transmitters to equalize the modulating signal frequency response changed by the following transmitter blocks.
The output of the optional pre-emphasis circuit 417 is input to a radio frequency (RF) modulator 420, which includes a digital-to-analog converter (DAC) (not shown) and converts an analog version of the digitally pre-distorted training signal to a radio frequency.
The RF modulator 420 receives a PLL signal from PLL 460 that is of a form of:
The fundamental frequency (LO)+the 3rd harmonic (where the 3LO is: fRF−fOFF+3fRF−3fOFF)+the 5th order harmonic (where the 5LO is: 5fRF−5fOFF)+ . . . [3]
where the offset frequency (fOFF) is the frequency difference of the PLL between the DPD calibration mode and the normal transmission mode. Typically, the offset frequency is chosen as the same as the intermediate frequency (fOFF=fIF)
Hence, when this PLL signal is applied to the digitally pre-distorted training signal, the resultant RF output signal from the RF modulator 420 is of a form of:
xLO (which is: fRF−fOFF+fBB+fIF)+x3LO (which is: 3fRF−3fOFF+fBB+fIF)+x5LO (which is: 5fRF−5fOFF+fBB+fIF)+ . . . [4]
The output from the RF modulator 420 is routed 422 through a power amplifier 324, such that the output signal 326 is an amplified analog representation of the DPD digital training signal (Xref) 410. At this point, the desired RF signal is only xLO in equ. [4], whereas a third harmonic distortion (HD3) component of x3LO is attenuated by the power amplifier 324.
A portion of the output signal 326 is routed back to the DPD circuit 415 via radio frequency (RF) demodulator 435. In this example, the RF demodulator 435 includes a down-mixer and an analog-to-digital converter (ADC). The output of the RF demodulator 435 is a digital representation of: nfBB+fIF together with third harmonic distortion (HD3) content thereof −3fBB−3fIF. In accordance with this example architecture, the down-converted baseband portion of the output signal 326 is input to a second SSB mixer 442. The second SSB mixer 442 subtracts the intermediate frequency, fIF, that was previously introduced, and thereby outputs a feedback transmit training signal of nfBB, together with a further frequency shifted third harmonic distortion content thereof of −3fBB−4fIF 444. The feedback transmit training signal is input to filter 446, which is effectively used to remove the harmonic content of −3fBB−4fIF. The filtered output 448 of nfBB is then input to a calibration circuit (e.g. calibration processing engine) 450, which compares the filtered signal of nfBB to the DPD digital training signal (Xref) 410. An output of the calibration circuit 450 is used to control the pre-distortion coefficients in digital predistorter 415. In some examples, a look-up table 452 may be used to store the determined pre-distortion coefficients.
In this example, the first frequency shift implemented by the first SSB mixer in the transmit path, and the second SSB mixer reversing the frequency shift in the feedback path, is fIF.
In this example architecture, the RF modulator 420 and RF demodulator 435, which are configured to effect up-conversion of a baseband or intermediate frequency signal transmit signal to an RF frequency and down-conversion of the RF fed back signal to a baseband or intermediate frequency signal to be compared to the original transmit signal 410 signal to control the pre-distortion coefficients in digital predistorter 415, are each supplied with the same local oscillator (LO) signal 465. The LO signal is generated by a phase locked loop PLL frequency generation circuit 460, which inevitably includes fRF−fOFF (an offset frequency that sets a desired output frequency from the PA 324) together with third harmonic distortion content thereof: 3fRF−3fOFF.
In operation, the calibration circuit 450 determines how the transmitter circuitry, and particularly the power amplifier 324, has affected the DPD digital training signal (Xref) 410, by analyzing the output from a comparison circuit within the calibration circuit 450 and determining PA nonlinearity (amplitude modulated to amplitude modulated (AM-to-AM) and amplitude modulated to phase modulated (AM-to-PM)) effects. Notably, in accordance with examples of the invention, the application of the respective frequency shifts also enables the 3rd harmonic distortion content of the LO signal to be easily removed by a LPF.
The calibration circuit 450 then adapts phase and gain components in the digital predistorter 415 that, effectively, pre-distorts the input signal, e.g. DPD digital training signal (Xref) 410, to compensate for the subsequent non-linearity and distortion effects that will be caused to the input signal by the transmitter circuit and shape the envelope at same time.
In this manner, the frequency shift by fIF of the transmit signal in the transmitter path via the SSB mixer 412, followed by the reverse frequency shift by fIF of the transmit signal in the feedback path enables the frequency shifted 3rd harmonic distortion content to be removed by LPF filter 446, where the cut-off frequency may be configured to be larger than the IF frequency, or the transmit LPF may be bypassed, or a transmit pre-emphasis filter used to compensate the transmit LPF frequency response or an IF frequency selected that is too small to attenuate the training signal significantly.
Although in this example the introduction (and subsequent removal) of an intermediate frequency shift has been implemented in the digital domain via SSB mixers 412, 442, it is envisaged that the architecture could be adapted such that the intermediate frequency shift may be introduced by analog SSB mixers in the analog domain (i.e. post DAC in the transmitter path and pre-ADC in the receiver path).
Referring now to
The example illustrated in
In this example, the frequency shift implemented by the first SSB mixer in the transmit path, and the second SSB mixer reversing the frequency shift in the feedback path, is fIF.
In this example transmitter architecture, the output pre-distorted training signal is input to an optional pre-emphasis circuit 517. The output of the optional pre-emphasis circuit 517 is input to a RF modulator 520, which includes a DAC (not shown) and converts an analog version of the digitally pre-distorted training signal to a radio frequency.
The RF modulator 520 receives a PLL signal from PLL 560 that is of a form of equation [3]. Hence, when this PLL signal is applied to the digitally pre-distorted training signal, the resultant RF output signal from the RF modulator 520 is of a form of equation [4].
The output from the RF modulator 520 is routed 522 through a power amplifier 324, such that the output signal 326 is an amplified analog representation of the DPD digital training signal (Xref) 510. At this point, the desired RF signal is of a form of xLO in equ. [4], whereas it contains a third harmonic distortion (HD3) of the PA input signal (xLO), and x3LO at the PA input is attenuated by the PA gain frequency response. A portion of the output signal 326 is routed back to the DPD circuit 515 via RF demodulator 535.
In this example, the RF demodulator 535 includes a down-mixer and an ADC. The output of the RF demodulator 535 is a digital representation of: nfBB+fIF together with third harmonic distortion content thereof −3fBB−3fIF. In accordance with this example architecture, the down-converted baseband portion of the output signal 326 is input to a second SSB mixer 542. The second SSB mixer 542 subtracts the intermediate frequency, fIF, that was previously introduced, and thereby outputs a feedback transmit training signal of fBB, together with a further frequency shifted third harmonic distortion content thereof of −3fBB−5fIF 544. The feedback transmit training signal is input to filter 546, which is effectively used to remove the harmonic content. The filter output 548 of nfBB is then input to a calibration circuit (e.g. calibration processing engine) 550, which compares the filtered signal of nfBB to the DPD digital training signal (Xref) 510 in a comparison circuit 530. An output of the calibration circuit 550 is used to control the pre-distortion coefficients in digital predistorter 515. In some examples, a look-up table 552 may be used to store the determined pre-distortion coefficients.
In this example architecture, the RF modulator 520 and RF demodulator 535, which are configured to effect up-conversion of a baseband or intermediate frequency signal transmit signal to an RF frequency and down-conversion of the RF fed back signal to a baseband or intermediate frequency signal to be compared to the original transmit signal 510 signal to control the pre-distortion co-efficients in digital predistorter 515, are each supplied with the same LO signal 565. The LO signal is generated by a phase locked loop frequency generation circuit 560, which inevitably includes fRF−fOFF (an offset frequency that sets a desired output frequency from the PA 324) together with third harmonic distortion content thereof: −3fRF−3fOFF.
In operation, the calibration circuit 550 determines how the transmitter circuitry, and particularly the power amplifier 324, has affected the DPD digital training signal (Xref) 510, by analyzing the output from the comparison circuit within the calibration circuit 550 and determining PA nonlinearity (amplitude modulated to amplitude modulated (AM-to-AM) and amplitude modulated to phase modulated (AM-to-PM)) effects. The calibration circuit 550 then adapts phase and gain components in the digital predistorter 515 that, effectively, pre-distorts the input signal, e.g. DPD digital training signal (Xref) 510, to compensate for the subsequent non-linearity and distortion effects that will be caused to the input signal by the transmitter circuit and shape the envelope at same time.
In this manner, the frequency shift by fIF of the transmit signal in the transmitter path by the first SSB mixer 512, followed by the reverse frequency shift by fIF 541 of the transmit signal in the feedback path via the second SSB mixer 542, enables the frequency shifted 3rd harmonic distortion content to be removed by filter 546.
Although in this example the introduction (and subsequent removal) of an intermediate frequency shift has been implemented in the digital domain via SSB mixers 512, 542, it is envisaged that the architecture could be adapted such that the intermediate frequency shift may be introduced by analog SSB mixers in the analog domain (i.e. post DAC in the transmitter path and pre-ADC in the receiver path).
In some examples, assuming digital SSB mixers are used, there is no benefit in locating the DPD before the SSB mixer in the forward path as in
Referring now to
In this example, a signal generator 605 generates a DPD digital training signal (Xref) 610 that is routed through the transmitter circuit. The DPD digital training signal Xref 610 is input to the digital predistorter 615, where the digital components of the training signal are (pre-) distorted. In this example, an intermediate frequency, FIF, is introduced into an output predistorted DPD digital training signal via a first SSB mixer 612, which outputs a transmit training signal of FBB+FIF. In this example transmitter architecture, the output pre-distorted training signal is input to an optional pre-emphasis circuit 617, which is employed in frequency modulation or phase modulation transmitters to equalize the modulating signal drive power in terms of deviation ratio. The receiver demodulation process includes a reciprocal network, called a de-emphasis network, to restore the original signal power distribution. The output of the optional pre-emphasis circuit 617 is input to a radio frequency modulator 620, which includes a digital-to-analog converter (DAC) (not shown) and converts an analog version of the digitally pre-distorted training signal to a radio frequency (RF) that is routed 622 through a power amplifier 324, such that the output signal 326 is an amplified analog representation of the DPD digital training signal (Xref) 610.
A portion of the output signal 326 is routed back to the DPD circuit 615 via radio frequency (RF) demodulator 635. In this example, the RF demodulator 635, includes a down-mixer and an ADC. The output of the RF demodulator 635 is a digital representation of: nfBB+fIF together with third harmonic distortion content thereof −3fBB−fFIF. In accordance with this example architecture, the down-converted baseband portion of the output signal 326 is input to a second SSB mixer 642. The second SSB mixer 642 subtracts the intermediate frequency, fIF, that was previously introduced, and thereby outputs a feedback transmit training signal of fBB, together with a further frequency shifted third harmonic distortion content thereof of −3fBB−6fIF 644. The feedback transmit training signal is input to averaging circuit 647, which removes the harmonic content. The averaging circuit output 648 of nfBB is then input to a calibration circuit (e.g. calibration processing engine) 650, which compares the filtered signal of nfBB to the DPD digital training signal (Xref) 610 in a comparison circuit 630. An output of the calibration circuit 650 is used to control the pre-distortion coefficients in digital predistorter 615.
In some examples, a use of an averaging circuit 647 does not require a specific filter. In some examples, it is envisaged that the averaging circuit 647 may include a multiplexer 680 that outputs signals to multiple accumulators 684 that may be controlled based on the reference signal (e.g. the DPD digital training signal) level 682. Also, in some examples, the averaging circuit 647 may include a frequency response with a frequency having a large attenuation that is aligned with the frequency that relates to the transmitter's HD3.
In some examples, by choosing an IF that is too close to the notch, it is possible to obtain a benefit that the circuit does not require an additional filter. In this regard, the averaging circuit 647 (or filter in other examples) removes or reduces the third harmonic distortion (HD3) component using −3fRF−4fIF.
In this example architecture, the RF modulator 620 and RF demodulator 635, which are configured to effect up-conversion of a baseband or intermediate frequency signal transmit signal to an RF frequency and down-conversion of the RF fed back signal to a baseband or intermediate frequency signal to be compared to the original transmit signal 610 signal to control the pre-distortion coefficients in digital predistorter 615, are each supplied with the same LO signal 665. The LO signal is generated by a phase locked loop frequency generation circuit 660, which inevitably includes fRF−fOFF (an offset frequency that sets a desired output frequency from the PA 324) together with third harmonic distortion content thereof: −3fRF−3fOFF.
In operation, the calibration circuit 650 determines how the transmitter circuitry, and particularly the power amplifier 324, has affected the DPD digital training signal (Xref) 610, by analyzing the output from the comparison circuit within the calibration circuit 650 and determining PA nonlinearity (amplitude modulated to amplitude modulated (AM-to-AM) and amplitude modulated to phase modulated (AM-to-PM)) effects. The calibration circuit 650 then adapts phase and gain components in the digital predistorter 615 that, effectively, pre-distorts the input signal, e.g. DPD digital training signal (Xref) 610, to compensate for the subsequent non-linearity and distortion effects that will be caused to the input signal by the transmitter circuit and shape the envelope at same time. In some examples, a look-up table 652 may be used to store the determined pre-distortion co-efficients.
In this manner, the frequency shift by fIF of the transmit signal in the transmitter path via the SSB mixer 612, followed by the reverse frequency shift by fIF of the transmit signal in the feedback path enables the frequency shifted 3rd harmonic distortion content to be removed by averaging circuit 647.
Although in this example the introduction (and subsequent removal) of an intermediate frequency shift has been implemented in the digital domain via SSB mixers 612, 642, it is envisaged that the architecture could be adapted such that the intermediate frequency shift may be introduced by analog SSB mixers in the analog domain (i.e. post DAC in the transmitter path and pre-ADC in the receiver path).
Referring now to
In the second, subsequent normal transmission mode of operation 820, the SSB mixers are then disabled or bypassed in both the forward and feedback paths, at 822. At 824, in this example, the phase locked loop frequency of fRF is set in the transmitter path. At 826, a transmit orthogonal frequency division multiplex (OFDM) signal, in this example, is sent, with the DPD coefficients (and/or) filter parameters being set to reduce any harmonic distortion content of the transmitter signal, particularly reduce third order harmonic distortion. In this manner, a cleaner and more linear transmitter signal is output from the power amplifier.
In some example embodiments, the examples herein described may increase transmitter output power for low order modulation signals, due to the lower spectral regrowth, so long as the output power meets the spectrum mask specification.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims.
Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
Any arrangement of components to achieve the same functionality is effectively ‘associated’ such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as ‘associated with’ each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being ‘operably connected’, or ‘operably coupled’, to each other to achieve the desired functionality.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
For example, in some example embodiments, it is envisaged that a single processor may be configured to perform multiple functions and operations of circuits hereinbefore described. Furthermore, in some example embodiments, although the LUTs have been described individually, thereby suggesting that they may comprise separate memory elements, it is envisaged that a number or each may form a portion of a single LUT or memory element.
Also for example, the various components/modules, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type. However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms ‘a’ or ‘an’, as used herein, are defined as one, or more than one. Also, the use of introductory phrases such as ‘at least one’ and ‘one or more’ in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles ‘a’ or ‘an’ limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases ‘one or more’ or ‘at least one’ and indefinite articles such as ‘a’ or ‘an’. The same holds true for the use of definite articles. Unless stated otherwise, terms such as ‘first’ and ‘second’ are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
The connections as discussed herein may be any type of connections suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediary components. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections or bidirectional connections. However, different illustrated examples may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.
It will be appreciated that, for clarity purposes, the above description has described embodiments of the invention with reference to different functional units and processors. However, it will be apparent that any suitable distribution of functionality between different functional units or processors, for example one or more shaping circuits, etc., may be used without detracting from the invention. Hence, references to specific functional units are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.
Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term ‘comprising’ does not exclude the presence of other elements or steps.
Furthermore, although individually listed, a plurality of means, elements or method steps may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. Also, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather indicates that the feature is equally applicable to other claim categories, as appropriate.
Furthermore, the order of features in the claims does not imply any specific order in which the features must be performed and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order. In addition, singular references do not exclude a plurality. Thus, references to ‘a’, ‘an’, ‘first’, ‘second’, etc. do not preclude a plurality.
Thus, lower spectral regrowth solutions have been described, wherein the aforementioned disadvantages with prior art arrangements have been substantially alleviated.
| Number | Date | Country | |
|---|---|---|---|
| 62545591 | Aug 2017 | US |
