Patent Application
20170187399
Embodiments of the subject matter described herein relate generally to on-chip differential output drivers in point-to-point communication systems, and methods of their operation.
Devices known as serializers/deserializers (or “SerDes”) are commonly used in high-speed, point-to-point communications systems to exchange data between transmitters and receivers. In the transmitter, a transmitter-side SerDes receives parallel data signals from a parallel data bus, and converts the signals into a serialized bit stream. The serialized bit stream is fed into a differential line driver (or “differential signal buffer” or “differential output driver”), which drives the serialized bit stream out onto a single-ended or differential channel. In the receiver, and assuming a differential channel, a receiver-side SerDes receives the serialized bit stream from the channel, and feeds it into a differential signal input buffer. The input buffer performs clock recovery, and converts the incoming bits into a serial bit stream. The serial bit stream is then de-serialized (i.e., converted back into parallel data signals).
In the transmitter-side SerDes, a conventional differential line driver may be implemented as a current mode driver or a voltage mode driver. The performance of both of these types of drivers may be quantified by bandwidth, jitter, amplitude, power consumption, common mode noise, and return loss, among other things. When compared with each other, conventional current mode drivers and voltage mode drivers have various performance advantages and disadvantages. As data rates continue to climb, developers of differential line drivers continually strive to design drivers with improved performance.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
Embodiments of the inventive subject matter include push-pull current mode output driver circuits, which are suitable for use in high data rate transmitters. For example, as will be described in detail below, the output driver circuit embodiments may be used in a serializer/deserializer (SerDes) type of system, in which a serializer within the transmitter provides a serialized bit stream to an embodiment of an on-chip output driver circuit, and the output driver circuit drives signals representing the bit stream onto a differential a channel. In some embodiments, the channel may be an on-chip channel, and in other embodiments, the channel may be an off-chip channel. As used herein, the term “on-chip” means integrated within or directly coupled to an integrated circuit (IC) (e.g., a semiconductor chip), such as a transmitter IC, a receiver IC, or a transceiver IC. Conversely, as used herein, the term “off-chip” means coupled to a substrate other than an IC, such as a printed circuit board (PCB) or some other type of module substrate (e.g., a multi-chip module substrate).
Although implementation of the various embodiments in a SerDes type of system is illustrated in the figures and described in detail below, it should be understood that the below-described output driver circuit embodiments also may be implemented in a variety of other transmitter types. Essentially, the output driver circuit embodiments may be implemented in any type of on-chip transmitter that drives complementary data onto a differential channel (e.g., an on-chip or off-chip channel), and which includes a serial link termination. As will be described in detail later, an on-chip I/O (input/output) circuit in the transmitter includes push-pull output drivers (or push-pull complementary data switch pairs) with positively coupled T-coil circuits that are configured to filter on-die output capacitance and provide bandwidth enhancement. This may result in improved return loss and increased bandwidth, when compared with conventional I/O circuits. As is known, relatively low return loss and wider bandwidth near a center operational frequency of interest are desirable performance goals, which may enable a system to better meet high-speed performance requirements.
The transmitter I/O circuit 160 includes a serializer 132, an embodiment of a differential output driver 134, and a phase locked loop (PLL) circuit 136. The serializer 132 is configured to receive parallel transmit data signals 110 from a parallel data bus (not shown) of the transmitter, and to convert the parallel transmit data signals 110 into a serialized bit stream 112. Sampling of the parallel transmit data signals 110 and outputting of the serialized bit stream 112 by the serializer 132 is controlled by a high-speed clock signal 142 provided by the PLL 136.
The PLL 136 is driven by a high-quality reference clock signal 140, which may have a clock frequency substantially equal to the rate at which the serializer 132 clocks in the parallel transmit data signals 110 (referred to herein as the “parallel data clock rate”). Using the reference clock signal 140, the PLL 136 produces the high-speed clock signal 142 at a clock frequency that is substantially equal to the parallel data clock rate multiplied by N, where N is the number of parallel transmit data signals 110. For example, in a system in which the parallel data bus provides ten parallel transmit data signals 110, and in which the clock frequency of the reference clock signal 140 is 1.4 gigahertz (GHz), the high-speed clock signal 142 may have a clock frequency of 14 GHz. In such an embodiment, the data rate of the serialized bit stream 112 (referred to herein as the “serial data rate”) would be twice the clock frequency, or 28 gigabits per second (Gbps).
The serialized bit stream 112 produced by the serializer 132 is provided to the differential output driver 134, which is configured to drive the serialized bit stream 112 out onto the differential channel 150 as a differential transmit data signal 114. As will be described in more detail in conjunction with
The differential channel 150 may include, for example, conductive wires (e.g., a twisted pair) or conductive traces coupled to a printed circuit board. Because the channel 150 may impart distortion, attenuation, and other signal effects to the differential transmit data signal 114, the corresponding data signal received by the receiver I/O circuit 160 is differentiated from the differential transmit data signal 114 by referring to it as a differential receive data signal 116.
The on-chip receiver I/O circuit 160 includes a differential signal input buffer 162, a de-serializer 164, and a timing recovery circuit 166. Using a high-speed clock signal 170 from the timing recovery circuit 166, the differential signal input buffer 162 samples the differential receive data signal 116, and produces a serialized bit stream 118. Essentially, the timing recovery circuit 166 produces the high-speed clock signal 170 at a clock frequency that is substantially the same as the clock frequency of the high-speed clock signal 142 produced by the PLL 136 on the transmitter side. Using the high-speed clock signal 170 from the timing recovery circuit 166, the de-serializer 164 converts the serialized bit stream 118 into parallel receive data signals 120, which are provided to a parallel data bus (not shown) of the receiver.
The data switch pairs, referred to below as a D+ data switch pair and a D− data switch pair, are coupled in parallel with each other between a high-side current source and a low-side current source. Essentially, the D+ data switch pair transmits a non-inverted version of an input serial bit stream, D+ (e.g., a non-inverted version of serialized bit stream 112,
In the illustrated embodiment, the transistors 220, 222, 225, 227 of each data switch pair include complementary (i.e., of opposite conductivity types) metal oxide semiconductor (CMOS) field effect transistors (FETs), where each transistor includes a control terminal (e.g., a gate terminal) and first and second current conducting terminals (e.g., a source terminal and a drain terminal, or vice versa). As is known, a variable signal applied to the control terminal affects the electrical conductivity of a channel between the first and second current carrying terminals, and thus the current flow through the channel.
According to an embodiment, a first pair of CMOS transistors composing the D+ data switch pair includes a P-channel transistor 220 and an N-channel transistor 222. The source of the P-channel transistor 220 is coupled to the high-side current source, and the source of the N-channel transistor 222 is coupled to the low-side current source. The drains of the transistors 220, 222 are coupled together at output node 224, which in turn is coupled to the first differential output terminal 250. The gates 221, 223 of transistors 220, 222 are coupled together to receive the non-inverted version of the input serial bit stream, D+.
A second pair of complementary transistors composing the D− data switch pair also includes a P-channel transistor 225 and an N-channel transistor 227. The source of the P-channel transistor 225 is coupled to the high-side current source (and to the source of P-channel transistor 220), and the source of the N-channel transistor 227 is coupled to the low-side current source (and to the source of N-channel transistor 222). The drains of the transistors 225, 227 are coupled together at output node 229, which in turn is coupled to the second differential output terminal 252. The gates 226, 228 of transistors 225, 227 are coupled together to receive the inverted version of the input serial bit stream, D−.
According to an embodiment, the high-side current source includes a P-channel transistor 210 with its source coupled to a voltage supply (e.g., Vdd), and its drain coupled to the sources of P-channel transistors 220, 225. The gate of transistor 210 is coupled to the output of a bias circuit 260, which provides a relatively constant bias voltage 262 (e.g., Vbp) to transistor 210. During operation, the high-side current source is biased to provide a relatively constant current to the push-pull output driver (e.g., 10 milliamps (mA) or some other current level).
According to an embodiment, the low-side current source includes an N-channel transistor 212 with its source coupled to the sources of N-channel transistors 222, 227, and its drain coupled to a ground reference voltage (e.g., Vss). The gate of transistor 212 is coupled to the output of a bias circuit 264, which provides a bias voltage 268 (e.g., Vocm) that is dependent on the difference between a reference voltage 267 and the voltage at a common mode node 230, as will be discussed in more detail below. During normal operations, the current through the high-side and low-side current sources is substantially equal.
According to an embodiment, the output nodes 224, 229 of the D+ and D− data switch pairs are coupled to a differential termination circuit, which includes termination resistors 234 and 238. More specifically, a first termination resistor 234 is coupled between the first output node 224 and a common mode node 230, and a second termination resistor 238 is coupled between the second output node 229 and the common mode node 230. The termination resistors 234, 238 are configured to match the impedance of the on-chip circuitry with the channel (e.g., channel 150,
According to an embodiment, the common mode node 230 is coupled to a ground reference voltage through a common mode capacitor 240. Desirably, the common mode capacitor 240 has a relatively large value to provide a very low AC impedance to ground. For example, capacitor 240 may have a value of about 10 picofarads, although larger or smaller capacitance values may be used, as well.
According to an embodiment, the center tap of a positively coupled T-coil also is coupled to each output node 224, 229. More specifically, a first T-coil includes a primary inductance 232 (or primary coil) coupled between the first output node 224 and the first termination resistor 234, and a secondary inductance 233 (or secondary coil) coupled between the first output node 224 and the first differential output terminal 250. Similarly, a second T-coil includes a primary inductance 236 (or primary coil) coupled between the second output node 229 and the second termination resistor 238, and a secondary inductance 237 (or secondary coil) coupled between the second output node 229 and the second differential output terminal 252. On the transmitter IC, each T-coil may be implemented as a pair of positively coupled, integrated inductors, such as aligned spiral inductors that are fabricated using different metal layers of the IC. The mutual coupling (e.g., the positive mutual coupling) of the primary and secondary inductances 232, 233, 236, 237 of the first and second T-coils is indicated by arrows 270, 272.
According to an embodiment, the T-coil inductances 232, 233, 236, 237 are configured so that their mutual inductances (e.g., their positive mutual inductances) will substantially filter out (or compensate for) the on-chip output capacitance of each push-pull complementary data switch pair, which tends to be highest at the output nodes 224, 229. This may provide a matching effect for return loss at the desired frequency of interest. Further, the primary coil of each T-coil (e.g., inductances 232, 236) may provide a shunt-peaking effect for bandwidth extension. The T-coil inductances 232, 233, 236, 237 should be designed to have inductance values that are appropriate for the serial data rate and the magnitude of the on-chip output capacitances for which the T-coils are intended to compensate. For example, in a transmitter configured to support a 28 Gbps serial data rate, each inductance 232, 233, 236, 237 may have an inductance value of about 400 picohenries (pH), although larger or smaller inductance values may be used, as well.
Although the various transistors 210, 212, 220, 222, 226, 228 are illustrated to have particular conductivity types (e.g., P-type or N-type), those of skill in the art would understand, based on the description herein, that the conductivity types of the various transistors 210, 212, 220, 222, 226, 228 could be opposite those illustrated in
The method may begin, in block 302, by converting (e.g., by serializer 132,
As mentioned above, embodiments of the on-chip differential output driver circuits discussed above may result in improved return loss, when compared with conventional output driver circuits. For example,
In addition, embodiments of the on-chip differential output driver circuits discussed above may produce an inductive peaking effect that extends the bandwidth. For example,
In addition, embodiments of the on-chip differential output driver circuits discussed above may result in reduced signal distortion, when compared with a conventional output driver circuit. This is indicated, for example, by comparing the transient eye diagrams in
An embodiment of an output driver circuit includes an output terminal configured to produce an output signal, a complementary data switch pair, and a T-coil. The complementary data switch pair is coupled between a voltage source and a ground reference node. The complementary data switch pair includes a first transistor and a second transistor, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the first and second transistors are coupled together at an output node, and the control terminals of the first and second transistors are configured to receive an input signal. The T-coil is coupled to the output node. The T-coil includes a first coil coupled between the output node and the output terminal, and a second coil coupled between the output node and a termination. A mutual inductance (e.g., a positive mutual inductance) is present between the first coil and the second coil during operation of the output driver circuit. An embodiment of a differential output driver circuit includes a first output terminal configured to produce a first output signal, a second output terminal configured to produce a second output signal, first and second complementary data switch pairs, and first and second T-coils.
The first and second output signals are complementary signals of a differential output signal. The first complementary data switch pair is coupled between a voltage source and a ground reference node. The first complementary data switch pair includes a pair of first complementary transistors, where each of the first complementary transistors includes a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the first complementary transistors are coupled together at a first output node, and the control terminals of the first complementary transistors are configured to receive a first input signal. The second complementary data switch pair is coupled in parallel with the first complementary data switch pair between the voltage source and the ground reference node. The second complementary data switch pair includes a pair of second complementary transistors, where each of the second complementary transistors includes a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the second complementary transistors are coupled together at a second output node, and the control terminals of the second complementary transistors are configured to receive a second input signal that is complementary to the first input signal. The first T-coil is coupled to the first output node, and the first T-coil includes a first coil coupled between the first output node and the first output terminal, and a second coil coupled between the first output node and a first termination. A mutual inductance (e.g., a positive mutual inductance) is present between the first coil and the second coil during operation of the output driver circuit. The second T-coil coupled to the second output node, and the second T-coil includes a third coil coupled between the second output node and the second output terminal, and a fourth coil coupled between the second output node and a second termination. A mutual inductance (e.g., a positive mutual inductance) is present between the third coil and the fourth coil during operation of the output driver circuit.
An embodiment of a transmitter IC includes a serializer and an output driver circuit. The serializer is configured to convert a parallel transmit signal into a serialized bit stream. The output driver circuit is coupled to the serializer, and is configured to receive the serialized bit stream, to modify the serialized bit stream, and to drive the modified serialized bit stream onto a channel. The output driver circuit includes an output terminal configured to produce an output signal, a complementary data switch pair, and a T-coil. The complementary data switch pair is coupled between a voltage source and a ground reference node. The complementary data switch pair includes first and second transistors, each with a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the first and second transistors are coupled together at an output node, and the control terminals of the first and second transistors are configured to receive the serialized bit stream. The T-coil is coupled to the output node. The T-coil includes a first coil coupled between the output node and the output terminal, and a second coil coupled between the output node and a termination. A mutual inductance (e.g., a positive mutual inductance) is present between the first coil and the second coil during operation of the output driver circuit.
An embodiment of a method of operating an output driver circuit includes modifying a first data signal using a first complementary data switch pair coupled between a voltage source and a ground reference node. The first complementary data switch pair includes a pair of first complementary transistors, where each of the first complementary transistors includes a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the first complementary transistors are coupled together at a first output node, and the control terminals of the first complementary transistors are configured to receive a first input signal. The method further includes compensating for output capacitance of the first complementary data switch pair using an inductive filter comprised of a first T-coil coupled to the first output node. The first T-coil includes a first coil coupled between the first output node and a first output terminal, and a second coil coupled between the first output node and a first termination. A mutual inductance is present between the first coil and the second coil during operation of the output driver circuit.
In a further embodiment the output driver circuit is a differential output driver circuit, and the method further includes modifying a second data signal using a second complementary data switch pair coupled in parallel with the first complementary data switch pair between the voltage source and the ground reference node. The second complementary data switch pair includes a pair of second complementary transistors, where each of the second complementary transistors includes a control terminal, a first current conducting terminal, and a second current conducting terminal. The first current conducting terminals of the second complementary transistors are coupled together at a second output node, and the control terminals of the second complementary transistors are configured to receive a second input signal that is complementary to the first input terminal. The further embodiment also includes compensating for output capacitance of the second complementary data switch pair using an inductive filter comprised of a second T-coil coupled to the second output node. The second T-coil includes a third coil coupled between the second output node and a second output terminal, and a fourth coil coupled between the second output node and a second termination. A mutual inductance is present between the third coil and the fourth coil during operation of the output driver circuit.
The foregoing detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the words “exemplary” and “example” mean “serving as an example, instance, or illustration.” Any implementation described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the foregoing technical field, background, or detailed description.
For the sake of brevity, conventional semiconductor fabrication techniques may not be described in detail herein. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
The foregoing description refers to elements or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
