Patent Application
20080279289
The entire disclosure of Japanese Patent Application No. 2007-123353, filed May 8, 2007 is expressly incorporated by reference herein.
1. Technical Field
An aspect of the present invention relates to an asynchronous data transfer. More specifically, in two-way to four-way handshaking communication, the invention relates to signaling for a fixed length serial burst data transfer at high speed.
2. Related Art
Data transfer between asynchronous systems themselves has been achieved by the two-way to four-way handshaking. As such a technique, a technique shown in Case study of “Asynchronous processor”, Fundamental treatment for noise & electric power consumption in digital LSI, Nobuo Karaki, Design Wave Magazine, pp. 64-91, July (2005) has been known.
However, in the two-way to four-way handshaking shown in Case study of “Asynchronous processor”, in a case of transferring a serial data block having a certain length, the handshaking by bit is overhead, causing an issue that the transfer time is elongated.
Therefore, a high-speed serial data transfer has not been achieved by the asynchronous data transfer using the two-way to four-way handshaking.
An advantage of the invention is to provide a communication system achieving a high-speed serial data transfer by an asynchronous data transfer using two-way to four-way handshaking.
A transmitter included in a fixed length serial burst data transfer system in which the transmitter and a receiver are coupled to each other through at least two data transmission lines according to a first aspect of the invention includes a two wire encoder encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and transmitting the encoded transmit data to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission.
This can prevent overhead due to handshaking in asynchronous communication between the transmitter and the receiver when the communication starts according to a request for starting the communication from the transmitter. Further, as an advantage of the asynchronous communication, high-speed communication with low power consumption while not easily receiving impact of environmental variation is achieved.
A transmitter included in a fixed length serial burst data transfer system in which the transmitter and a receiver are coupled to each other through at least two data transmission lines according to a second aspect of the invention includes: a burst request receiver receiving a burst transmission request signal from the receiver through a request signal line; and a two wire encoder encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and transmitting the encoded transmit data to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission, corresponding to that the burst request receiver receives the burst transmission request signal.
This can prevent overhead due to handshaking in asynchronous communication between the transmitter and the receiver when the communication starts according to a request for starting the communication from the receiver. Further, as an advantage of the asynchronous communication, high-speed communication with low power consumption while not easily receiving impact of environmental variation is achieved.
The transmitter according to the first aspect of the invention may further include: a transmit data counter counting a number of the transmit data symbols encoded and transmitted; and a last data detector detecting if a number of the transmit data counted by the transmit data counter is a predetermined number of data or not, and outputting a last data signal if the detected number of the transmit data is the predetermined number of data. The two-wire encoder transmits the non-transmission symbol to the receiver through the two data transmission lines corresponding to receiving the last data signal from the last data detector.
This allows the transmitter to detect communication completion and output the non-transmission symbol by using the handshaking in the asynchronous communication.
A receiver included in a fixed length serial burst data transfer system in which a transmitter and the receiver are coupled to each other through at least two data transmission lines according to a third aspect of the invention includes: a memory storing receiving data; a two wire decoder receiving fixed length serial transmit data from the transmitter, decoding encoded transmit data symbols based on an identification symbol included in the received fixed length serial transmit data, and storing the decoded fixed length serial transmit data in the memory as receiving data, the fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, having the identification symbol inserted between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and being output to the receiver through the two data transmission lines during transmission, while a non-transmission symbol indicating a non-transmission state is output to the receiver through the two data transmission lines during non-transmission; a receiving data counter counting a number of pieces of the receiving data stored in the memory by the two wire decoder; a detector detecting if the number of pieces of the receiving data counted by the receiving data counter is a predetermined number of pieces of data or not, and outputting a detection signal if the detected number of the pieces of the receiving data is the predetermined number of pieces of data; and a receiving completion reporter transmitting a receiving completion signal to the transmitter corresponding to receiving the detection signal from the detector.
A receiver included in a fixed length serial burst data transfer system in which a transmitter and the receiver are coupled to each other through at least two data transmission lines according to a fourth aspect of the invention includes: a burst request transmitter transmitting a burst transmission request signal to the transmitter through a request signal line; a memory storing receiving data; a two wire decoder receiving fixed length serial transmit data from the transmitter, decoding encoded transmit data symbols based on an identification symbol included in the received fixed length serial transmit data, and storing the decoded fixed length serial transmit data in the memory as receiving data, the fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, having the identification symbol inserted between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and being output to the receiver through the two data transmission lines during transmission, while a non-transmission symbol indicating a non-transmission state is output to the receiver through the two data transmission lines during non-transmission; a receiving data counter counting a number of pieces of the receiving data stored in the memory by the two wire decoder; a detector detecting if the number of pieces of the receiving data counted by the receiving data counter is a predetermined number of pieces of data or not, and outputting a detection signal if the detected number of the pieces of the receiving data is the predetermined number of pieces of data; and a receiving completion reporter transmitting a receiving completion signal corresponding to receiving the detection signal from the detector.
The receiver according to the third aspect of the invention may further include: a data invalid signal generator outputting a data invalid signal for indicating that the receiving data is not stored from when a non-transmission symbol signal is input until when an identification symbol signal is input to the receiver in a case where the non-transmission symbol signal and the identification symbol signal are input from the two wire decoder; and a strobe signal generator receiving a write signal output from the two wire decoder, outputting the write signal to the memory, and masking the write signal corresponding to that the data invalid signal is input from the data invalid signal generator, wherein the two wire decoder outputs the receiving data to the memory, stores the receiving data in the memory by outputting the write signal to the memory while the receiving data is being output to the memory, outputs the identification symbol signal in a case of decoding the identification symbol included in the received fixed length serial transmit data, and outputs the non-transmission symbol signal in a case of decoding the non-transmission symbol included in the received fixed length serial transmission data.
According to the above, even when the receiving data to be received by the receiver has a hazard, the receiving data can be transmitted without receiving impact of the hazard.
Further, the receiver according to the third aspect of the invention may still further include a serial-to-parallel converter converting the receiving data output from the two wire decoder in a predetermined bit number in parallel form and storing the receiving data converted in parallel form in the memory.
This allows the receiver to store serial data being received as parallel data.
Furthermore, the receiver according to the third aspect of the invention may yet further include a data length setting unit extracting burst transmit data length information from the extracted received fixed length serial transmit data and setting a number of pieces of the transmit data of the burst transmit data length information as the predetermined number of pieces of data, wherein the fixed length serial transmission data of the two wire decoder receiving from the transmitter includes the number of pieces of the burst transmit data that is information of a number of pieces of the transmit data for transmitting at a time by burst transmission.
This enables transmission and reception of variable serial transmit data.
A method for transmitting by a transmitter included in a fixed length serial burst data transfer system in which the transmitter and a receiver are coupled to each other through at least two data transmission lines according to a fifth aspect of the invention includes: encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data; inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another; and transmitting the encoded transmit data to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission.
Further, a method for transmitting by a transmitter included in a fixed length serial burst data transfer system in which the transmitter and a receiver are coupled to each other through at least a request signal line and two data transmission lines according to a sixth aspect of the invention includes: encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data; inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another; and transmitting the encoded transmit data to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission, corresponding to that the transmitter receives a burst transmission request signal from the receiver through the request signal line.
The method according to the fifth aspect of the invention for transmitting by the transmitter may further include: counting a number of the transmit data symbols encoded and transmitted; detecting if a counted number of pieces of the transmit data is a predetermined number of data or not; outputting a last data signal if the counted number is detected as the predetermined number of data; and transmitting the non-transmission symbol to the receiver through the two data transmission lines corresponding to that the last data signal is input.
A method for receiving by a receiver included in a fixed length serial burst data transfer system in which a transmitter and the receiver are coupled to each other through at least two data transmission lines according to a seventh aspect of the invention includes: receiving the fixed length serial transmit data from the transmitter, the fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, having an identification symbol inserted between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and being output to the receiver through the two data transmission lines during transmission, while a non-transmission symbol indicating a non-transmission state is output to the receiver through the two data transmission lines during non-transmission; decoding transmit data symbols having been encoded based on the identification symbol included in the received fixed length serial transmit data so as to store the transmit data as receiving data in the memory; counting a number of pieces of the receiving data stored in the memory; detecting if the counted number of the pieces of the receiving data number is a predetermined number of pieces of data or not; outputting a detection signal if the number of the pieces of the receiving data is detected as the predetermined number of pieces of data; and transmitting a receiving completion signal to the transmitter corresponding to that the detection signal is input.
A method for receiving by a receiver included in a fixed length serial burst data transfer system in which a transmitter and the receiver are coupled to each other through at least two data transmission lines according to an eighth aspect of the invention includes transmitting a burst transmission request signal to the transmitter through a request signal line; receiving the fixed length serial transmit data from the transmitter, the fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, having an identification symbol inserted between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and being output to the receiver through the two data transmission lines during transmission, while a non-transmission symbol indicating a non-transmission state is output to the receiver through the two data transmission lines during non-transmission, decoding transmit data symbols having been encoded based on the identification symbol included in the received fixed length serial transmit data so as to store the transmit data as receiving data in the memory; counting a number of pieces of the receiving data stored in the memory; detecting if the counted number of the pieces of the receiving data number is a predetermined number of pieces of data or not; outputting a detection signal if the number of the pieces of the receiving data is detected as the predetermined number of pieces of data; and transmitting a receiving completion signal corresponding to that the detection signal is input.
The method for receiving by the receiver according to the seventh aspect of the invention may further include: outputting the receiving data to the memory; storing the receiving data in the memory by transmitting a write signal to the memory while the receiving data is being output to the memory; outputting an identification symbol signal in a case of decoding the identification symbol included in the received fixed length serial transmit data; outputting a non-transmission symbol signal in a case of decoding the non-transmission signal included in the received fixed length serial transmission data; outputting a data invalid signal for indicating that the receiving data is not stored from when the non-transmission symbol signal is input until when the identification symbol signal is input to the receiver in a case where the non-transmission symbol signal and the identification symbol signal are input from the two wire decoder, and masking the write signal corresponding to that the data invalid signal is input.
The method for receiving by the receiver according to the seventh aspect of the invention may still further include converting the receiving data in a predetermined bit number in parallel form; and storing the receiving data converted in parallel form in the memory.
The method for receiving by the receiver according to the seventh aspect of the invention may yet further include: extracting burst transmit data length information from the received fixed length serial transmit data; and setting a number of pieces of the transmit data of the extracted burst transmit data length information as the predetermined number of data, wherein the received fixed length serial transmission data includes the number of pieces of the burst transmit data that is information of the number of the pieces of the transmit data for transmitting at a time by burst transmission.
A fixed length serial burst data transfer system according to a ninth aspect of the invention includes a transmitter and a receiver coupled to the transmitter through at least two data transmission lines. The transmitter includes a two wire encoder encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and transmitting the transmit data being encoded to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission. The receiver includes: a memory storing receiving data; a two wire decoder receiving fixed length serial transmit data from the transmitter, decoding encoded transmit data symbols based on an identification symbol included in the received fixed length serial transmit data, and storing the decoded fixed length serial transmit data in the memory as receiving data; a receiving data counter counting a number of pieces of the receiving data stored in the memory by the two wire decoder; a detector detecting if the number of pieces of the receiving data counted by the receiving data counter is a predetermined number of pieces of data or not, and outputting a detection signal if the detected number of the pieces of the receiving data is the predetermined number of pieces of data; and a receiving completion reporter transmitting a receiving completion signal to the transmitter corresponding to receiving the detection signal from the detector.
A fixed length serial burst data transfer system according to a tenth aspect of the invention includes a transmitter, and a receiver being coupled to the transmitter through at least a request signal line and two data transmission lines. The transmitter includes: a burst request receiver receiving a burst transmission request signal from the receiver; and a two wire encoder encoding fixed length serial transmit data having binary digits to transmit data symbols each predetermined to correspond to each piece of the transmit data, inserting an identification symbol between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and transmitting the transmit data being encoded to the receiver through the two data transmission lines during transmission, while transmitting a non-transmission symbol indicating a non-transmission state to the receiver through the two data transmission lines during non-transmission, corresponding to that the burst request receiver receives the burst transmission request signal. The receiver includes: a burst request transmitter transmitting the burst transmission request signal to the transmitter; a memory storing receiving data; a two wire decoder receiving the encoded fixed length serial transmit data from the transmitter, decoding the encoded transmit data symbols based on an identification symbol included in the received fixed length serial transmit data so as to store as the receiving data in the memory; a receiving data counter counting a number of pieces of the receiving data stored in the memory by the two wire decoder; a detector detecting if the number of pieces of the receiving data counted by the receiving data counter is a predetermined number of pieces of data or not, and outputting a detection signal if the detected number of the pieces of the receiving data is the predetermined number of pieces of data; and a receiving completion reporter transmitting a receiving completion signal corresponding to receiving the detection signal from the detector.
In the fixed length serial burst data transfer system according to the ninth aspect of the invention, the data transmission lines may be made of metal.
In the fixed length serial burst data transfer system according to the ninth aspect of the invention, the data transmission lines may be made of an optic fiber and the two wire encoder may include a light emitter outputting at least one of transmit symbols among transmit data symbols, an identification symbol, and a non-transmission symbol through the optic fiber, while the two wire decoder may include a light receiver to receive the transmit symbols through the optic fiber.
This allows a high-speed serial data transfer system to communicate while reducing external influences such as electromagnetic waves.
Further, in the fixed length serial burst data transfer system, the light emitter may perform high-frequency modulation on an optical output corresponding to the transmit symbol, while the light receiver may receive and decode high-frequency light being modulated corresponding to the transmit symbol.
A semiconductor device according to an eleventh aspect of the invention includes the fixed length serial burst data transfer system according to the ninth aspect of the invention formed on a single silicon substrate.
This enables communication of a circuit in a semiconductor device formed on a single silicon substrate with the high-speed serial data transfer system.
A hybrid semiconductor device according to a twelfth aspect of the invention includes the fixed length serial burst data transfer system according to the ninth aspect of the invention formed on a plurality of various silicon substrates.
This enables communication of a circuit in a semiconductor device composed of various silicon substrates with the high-speed serial data transfer system.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Embodiments of the invention will now be described below with reference to the accompanying drawings.
Further, the active sending and passive receiving is a communication system in which a transmitter sends a request for starting communication and a receiver starts receiving by corresponding to the request.
The high-speed serial data transfer system includes a transmitter 10 for a high-speed serial data transfer, and a receiver 20 for a high-speed serial data transfer. The transmitter 10 for a high speed serial data transfer and the receiver 20 for a high speed serial data transfer are coupled to each other via two data transmission lines, d0 and d1. Further, the transmitter 10 and the receiver 20 for transferring high-speed serial data are coupled to each other via a confirmation signal line ‘comp2’. In a description below, the transmitter 10 for a high-speed serial data transfer is referred to as the transmitter 10, and the receiver 20 for a high-speed serial data transfer is referred to as the receiver 20.
The data transmission line d0 and the data transmission line d1 are respectively made of metal, for example. In addition, the confirmation signal line ‘comp2’ is also made of metal.
Further, the transmitter 10 transmits and receives transmit data ‘data1’, a transmit control signal ‘send’, a reception enable signal ‘ena’, a burst communication start signal ‘start’, and a confirmation signal line ‘comp3’ through a transmission side bus 30.
Further, the receiver 20 transmits and receives a read signal ‘read’, data ‘data3’, and a read request signal ‘readreq’ through a reception side bus 40.
Next, explanations on the transmitter 10, and the receiver 20 will be given. Here, between the transmitter 10 and the receiver 20, a case where the number of pieces of burst data that is the number of pieces of data to be transmitted or received in one burst transfer is preliminary defined.
The transmitter 10 transmits a signal for indicating that the transmitter 10 is transmittable (L) or untransmittable (H) with respect to the receiver 20 to the transmission side bus 30 by the reception enable signal ‘ena’.
Further, the transmitter 10 starts a burst transfer by the communication start signal ‘start’ input from the transmission bus 30. Corresponding to the start of the burst transfer, the transmitter 10 makes the reception enable signal ‘ena’ be at an H level, transmitting a signal indicating a untransmittable state to the transmission side bus 30.
Further, after the start of the burst transfer, the transmitter 10 receives the transmit control signal ‘send’ and the transmit data ‘data1’ input from the transmission side bus 30. Then, based on the transmit control signal ‘send’ having been input, the transmit data ‘data1’ is encoded and transmitted to the receiver 20 via the two data transmit lines d0 and d1. The encoding will be described later.
Further, the transmitter 10 counts the number of pieces of the data having been transmitted. When it is detected that the number of pieces of the data transmitted reaches a predetermined number of pieces of burst data, the reception enable signal ‘ena’ is made to be at an L level so as to output a signal indicating that it is transmittable to the transmission side bus 30.
Further, the transmitter 10 receives an acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level through the confirmation signal line ‘comp2’ from the receiver 20, detecting that the receiver 20 has received all the transmit data. Further, corresponding to the reception of the acknowledged signal ‘ack’ through the confirmation signal line ‘comp2’, the transmitter 10 transmits an acknowledged signal ‘ack’ that is the confirmation signal line ‘comp3’ at the H level through the confirmation signal line ‘comp3’ to the transmission side bus 30.
The receiver 20 receives the transmit data that has been encoded from the transmitter 10 through the two data transmission lines d0 and d1, and then decodes and stores the data in a memory inside the receiver 20.
Further, the receiver 20 counts the number of pieces of the data having been received. When it is detected that the number of pieces of the data received reaches the predetermined number of pieces of the burst data, the receiver 20 transmits the acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level to the transmitter 10 through the confirmation signal line ‘comp2’.
Further, corresponding to the input of the read signal ‘read’ from the reception side bus 40, the receiver 20 outputs the transmit data stored in the memory inside as the data ‘data 3’ to the reception side bus 40.
Furthermore, corresponding to an amount of the transmit data stored in the memory inside, the receiver 20 outputs the read request signal ‘readreq’ indicating a request for reading the data stored in the receiver 20 to the reception side bus 40.
As described later, the transmitter 10 and the receiver 20 are communicated by four way handshaking in which the two data transmission lines d0 and d1 serve as request signal lines while the confirmation signal line ‘comp2’ serves as a confirmation signal line.
The transmission side bus 30 is coupled to a central processing unit (CPU) that executes transmission, and a transmit bus master such as a transmission circuit. The transmit bus master controls the transmitter 10 so as to transmit the transmit data to the receiver 20.
The reception side bus 40 is coupled to a CPU that executes reception, and a receiving bus master such as a receiving circuit. The receiving bus master controls the receiver 20 so as to receive the transmit data from the transmitter 10.
[Two Wire Encoding]
Next, encoding at the two data transmission lines d0 and d1 coupling the transmitter 10 and the receiver 20 will be described.
The transmit data is encoded in a combination of a high level and a low level so as to be transmitted to the two data transmission lines d0 and d1. From now, the high level is described as H or 1, while the low level is described as L or 0.
Symbols to be encoded in the two data transmission lines d0 and d1 are preliminarily determined between the transmitter and the receiver as shown in
The symbol “0” and the symbol “1” indicate transmit data having binary digits. The symbol “0” corresponds to the transmit data “0”, while the symbol “1” corresponds to the transmit data “1”. In the description below, the symbol “0” is described as the symbol 0, while the symbol “1” is described as the symbol 1. Further, the symbol 0 and the symbol 1 are described as transmit data symbols.
Further, the symbol “Invalid” is described as a symbol I, while the symbol “Null” is described as a symbol N.
Further, in the description below, the encoding described above is called two-wire encoding.
In the two wire encoding, the transmit data 0 or 1 is correspondingly encoded to the symbol 0 or 1, and then the symbol N is added before the symbol 0 or 1 having been encoded.
Adding the symbol N before the symbol 0 or 1 having been encoded means that the symbol N is inserted between the symbols 0 or 1. Further, the symbol N makes a breakpoint between the symbols 0 or 1 detectable.
[Outline Operation of the Transmitter 10 and the Receiver 20]
Next, referring to
First, at a timing t101 that is before transmission, the transmitter 10 transmits the symbol I. Corresponding to the transmit bus master starting the burst transfer, the transmitter 10 starts transmitting the transmit data, and transmits the symbol N at a timing t103 fast.
Here, in the symbol I, the data transmission lines d0 and d1 are at an H level, while in the symbol N, the data transmission lines d0 and d1 are at an L level. Therefore, when the symbol I is changed to the symbol N, the data transmission lines d0 and d1 are changed from the H level to the L level at the same timing. However, due to difference of wiring lengths between circuits, and variation of delay timing of elements executing transmission, timing in which the data transmission line d0 and d1 are changed from the H level to the L level may vary in some cases. Therefore, when the symbol I is changed to the symbol N, a hazard may occur in some cases.
Here, a case where the data transmission line d1 is changed from the H level to the L level at a timing t102, while the data transmission line d0 is changed from the H level to the L level at a timing t103, and thus the symbol 0 is output in a period between the timing t102 and the timing t103 will be described. The symbol 0 in the period between the timing t102 and the timing t103 is a hazard. In general, during the period between the timing t102 and the timing t103, there is a possibility to output the symbol 0 or the symbol 1, therefore, it is indefinite.
Next, the transmitter 10 transmits the symbol 0 at a timing t104. The receiver 20 receives the symbol 0 as the transmit data symbol, and counts the transmit data symbol, so that the receiver 20 makes the number of pieces of receiving data be 1.
Next, the transmitter 10 transmits the symbol N at a timing t105, and outputs the symbol 1 at a timing t106. The receiver 20 receives the symbol 1 as the transmit data symbol at the timing t106. After counting the received transmit data symbol, the receiver 20 makes the number of pieces of receiving data be 2.
By detecting that the number of pieces of the receiving data is 2, the receiver 20 transmits the acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level to the transmitter 10 thorough the confirmation signal line ‘comp2’.
Corresponding to that the transmitter 10 receives the acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level from the receiver 20, the transmitter 10 transmits the symbol I at a timing t108 to the receiver 20 through the data transmission lines d0 and d1.
Corresponding to reception of the symbol I transmitted from the transmitter 10, the receiver 20 makes the confirmation signal line ‘comp2’ be at the L level at a timing t109 so as to terminate outputting the acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level.
According to the above, the transmitter 10 and the receiver 20 communicate each other by the four-way handshaking in which the data transmission lines d0 and d1 serve as request signal lines while the confirmation signal line ‘comp2’ serves as a confirmation signal line.
The four-way handshaking will be explained by adding a request signal line ‘req’ to
The request signal line ‘req’ is a signal line that is at the L level when a symbol that the data transmission lines d0 and d1 carry is the symbol I, while it is at the H level when the symbol is other than the symbol I, that is, when the symbol is the symbol 1, the symbol 0, or the symbol N.
When only the request signal line ‘req’ and the confirmation signal line ‘comp2’ are focused, the transmitter 10 and the receiver 20 communicate each other as below.
Before the communication, the transmitter 10 has the request signal line ‘req’ at the L level while the receiver 20 has the confirmation signal line ‘comp2’ at the L level.
Next, the transmitter 10 makes the request signal line ‘req’ be at the H level at the timing t102. Then, corresponding to that the request signal line ‘req’ is at the H level, the receiver 20 makes the confirmation signal line ‘comp2’ be at the H level at the timing t107.
Next, corresponding to that the confirmation signal line ‘comp2’ is at the H level, the transmitter 10 makes the request signal line ‘req’ be at the L level at the timing t108. Next, corresponding to that the request signal line ‘req’ is at the L level, the confirmation signal line ‘comp2’ is made to be at the L level at the timing t109. Accordingly, the transmitter 10 has the request signal line ‘req’ at the L level while the receiver 20 has the confirmation signal line ‘comp2’ at the L level, so that the transmitter 10 and the receiver 20 are back in the state before the communication.
According to the above, when only the request signal line ‘req’ and the confirmation signal line ‘comp2’ are focused, the transmitter 10 and the receiver 20 communicate each other by the four way handshaking.
Further, while communicating each other by the four way handshaking with the request signal line ‘req’ and the confirmation signal line ‘comp2’, the transmitter 10 and the receiver 20 perform burst transmitting and receiving to transmit and receive data by the symbol 0, the symbol 1, and the symbol N during a period that the request signal line ‘req’ is at the H level, that is, a period in which the data transmission lines d0 and d1 do not transmit the symbol I.
Further, since the symbol N is inserted between the symbol 0 and the symbol 1 during the burst transmitting and receiving, even when the data 0s or the data is are successively arranged, the receiver 20 can separately extract the data 0s and the data 1s by using the symbol N.
[Configuration of the Transmitter 10]
Next, a configuration of the transmitter 10 will be described with reference to
The transmitter 10 includes an encoder 100, an initial setting unit 101, a transmit data counter 104, a last data detector 105, a counter memory 110, and a data length memory 111.
Between the transmitter 10 and the receiver 20, the number of pieces of data to be transmitted at a time by a burst transfer is preliminarily stored in the data length memory 111 as the number of pieces of the burst data. The number of pieces of the burst data is a value such as 8, 16, 32, or 64, for example.
Further, the number of pieces of the burst data stored in the data length memory 111 is equal to the number of pieces of the burst data stored in a data length memory 211 that is included in the receiver 20 and will be described later.
The counter memory 110 stores the number of pieces of the data transmitted from the transmitter 10 as the number of pieces of the transmit data. The number of pieces of the data having been transmitted is stored in the transmit data counter 104 as described later.
The encoder 100 transmits the reception enable signal ‘ena’ to the transmission side bus 30. The reception enable signal ‘ena’ is a signal for indicating that the transmitter 10 is in a state that is transmittable (H) or untransmittable (L) to the receiver 20.
Further, the transmitter 100 starts burst transfer corresponding to an input of the communication start signal ‘start’ at the H level from the transmission bus 30. On corresponding to the start of the burst transfer, the encoder 100 makes the reception enable signal ‘ena’ be at the L level, transmitting a signal indicating an untransmittable state to the transmission side bus 30.
Further, after the burst transfer has started, the encoder 100 receives the transmit control signal ‘send’ and the transmit data ‘data1’ input from the transmission bus 30. Then, based on the transmit control signal ‘send’ having been input, the encoder 100 encodes and transmits the transmit data ‘data1’ to the receiver 20 via the two data transmit lines d0 and d1.
The encoder 100 encodes the transmit data ‘data1’ to the symbol I, for example, if the communication start signal ‘start’ is at the L level and the transmit control signal ‘send’ is at the L level. Further, the encoder 100 encodes the transmit data ‘data1’ if the communication start signal ‘start’ is at the H level and the transmit control signal ‘send’ is at the L level to the symbol N. Furthermore, when the communication start signal ‘start’ is at the H level and the transmit control signal ‘send’ is at the H level, the encoder 100 encodes the transmit data ‘data1’ to the symbol N if the transmit data ‘data1’ is the data 0. On the contrary, the encoder 100 encodes the transmit data ‘data1’ to the symbol 1 if the transmit data ‘data1’ is the data 1.
That is, during transmission of a fixed length serial transmit data each having binary digits, the encoder 100 encodes each transmit data to a transmit data symbol (symbol 0 or symbol 1) that is predetermined to correspond to each data. And then, the encoder 100 inserts an identification symbol (symbol N) between the encoded transmit data symbols so as to be encoded to identify the transmit data symbols one from another, and encodes the data so as to transmit to the receiver through the two data transmission lines. During non-transmission, a non-transmission symbol (symbol I) indicating a non-transmission state is transmitted to the receiver through the two data transmission lines.
Further, the encoder 100 outputs the symbol I corresponding to an input of a last data signal ‘lastdata’ at the H level from the last data detector 105 described later.
On corresponding to the input of the last data signal ‘lastdata’ at the H level from the last data detector 105, the encoder 100 outputs the reception enable signal ‘ena’ at the L level to the transmission side bus 30 so as to transmit a signal indicating a transmittable state.
Further, the encoder 100 outputs the transmit control signal ‘send’ to the transmit data counter 104 as a transmit signal ‘dsend’. The encoder 100 generates the symbols with a state machine to output to the data transmission lines d0 and d1 under the conditions described above. Therefore, the symbols to output to the data transmission lines d0 and d1 are not changed under conditions other than the above.
The transmit data counter 104 increments the number of pieces of the transmit data stored in the transmit data counter 104 corresponding to the transmit signal ‘dsend’ input from the encoder 100.
For example, corresponding to the input of the transmit signal ‘dsend’, the transmit data counter 104 reads the number of pieces of the transmit data stored in the transmit data counter 104. After incrementing the number of pieces of the transmit data being read by one, the transmit data counter 104 stores the number of pieces of the transmit data incremented. According to the above, the transmit data counter 104 increments the number of pieces of the transmit data stored in the transmit data counter 104 by updating the number of pieces of the transmit data stored in the transmit data counter 104.
After reading the number of pieces of the transmit data from the counter memory 110, and reading the number of pieces of the burst data from the data length memory 111, the last data detector 105 detects whether the number of pieces of the transmit data and the number of pieces of the burst data correspond with each other or not.
Further, in a case of detecting that the number of pieces of the transmit data and the number of pieces of the burst data correspond with each other, the last data detector 105 outputs the last data signal ‘lastdata’ at the H level to the encoder 100.
Further, when receiving a receiving completion signal that is the confirmation signal line ‘comp2’ at the H level from the receiver 20, the last data detector 105 outputs the last data signal ‘lastdata’ at the L level to the encoder 100.
Furthermore, when receiving the receiving completion signal that is the confirmation signal line ‘comp2’ at the H level from the receiver 20, the initial setting unit 101 outputs the receiving completion signal that is the confirmation signal line ‘comp2’ at the H level having been received to the transmission side bus 30 as the confirmation signal line ‘comp3’ at the H level.
[Configuration of the Receiver 20]
Next, a configuration of the receiver 20 will be described with reference to
The receiver 20 includes a decoder 200, a First-in First-out (FIFO) 201, a data invalid signal generator 202, a strobe signal generator 203, a receiving data counter 204, a receiving completion detector 205, a receiving completion reporter 206, a counter memory 210, and the data length memory 211.
Between the transmitter 10 and the receiver 20, the number of pieces of data to be transmitted at a time by a burst transfer is preliminarily stored in the data length memory 211 as the number of pieces of the burst data.
The counter memory 210 stores the number of pieces of the data that the transmitter 20 has received as the number of pieces of the receiving data. The number of pieces of the data having been received is stored in the receiving data counter 204 as described later.
The decoder 200 decodes the transmit data that is encoded by the two wire encoding and input from the transmitter 10 through the data transmission lines d0 and d1. Then, the decoder 200 outputs the receiving data decoded by corresponding to the symbol 0 or the symbol 1 of the transmit data to the FIFO 201 as receiving data ‘data 2’.
Further, the decoder 200 outputs the data receiving signal ‘receive’ at the H level to the strobe signal generator 203 corresponding to a change of the decoded data from the symbol I or the symbol N to the symbol 0 or the symbol 1.
The decoder 200 generates a data receiving signal ‘receive’ by an EXOR circuit having one input terminal coupled to the data transmission line d0 and the other input terminal coupled to the data transmission line d1, for example.
Further, the decoder 200 decodes the transmit data that has been encoded by the two wire encoding and input from the transmitter 10 through the data transmission lines d0 and d1. If the decoded transmit data is the symbol I, the decoder 200 outputs a symbol I signal ‘inv’ at the H level, on the contrary, if the decoded transmit data is not the symbol I, the decoder 200 outputs the symbol I signal ‘inv’ at the L level to the data invalid signal generator 202, the receiving completion detector 205, and the receiving completion reporter 206 through a symbol I signal line.
The decoder 200 generates the symbol I signal ‘inv’ by an AND circuit having one input terminal coupled to the data transmission line d0 and the other input terminal coupled to the data transmission line d1, for example.
Further, the decoder 200 decodes the transmit data that has been encoded by the two wire encoding and input from the transmitter 10 through the data transmission lines d0 and d1. If the decoded transmit data is the symbol N, the decoder 200 outputs a symbol N signal ‘null’ at the H level, on the contrary, if the decoded transmit data is not the symbol N, the decoder 200 outputs the symbol N signal ‘null’ at the L level to the data invalid signal generator 202 through a symbol N signal line.
The decoder 200 generates the symbol N signal ‘null’ by a NOR circuit having one input terminal coupled to the data transmission line d0 and the other input terminal coupled to the data transmission line d1, for example.
The data invalid signal generator 202 receives the symbol I signal ‘inv’ and the symbol N signal ‘null’ from the decoder 200 and then generates a data invalid signal ‘datadis’ at the H level (truth) in a period from when the symbol I signal ‘inv’ that has been input becomes at the H level (truth) to when the symbol N signal ‘null’ becomes at the H level (truth). Further, the data invalid signal generator 202 outputs the data invalid signal ‘datadis’ that has been generated to the strobe signal generator 203.
The strobe signal generator 203 receives the data invalid signal ‘datadis’ from the data invalid signal generator 202 while receiving the data receiving signal ‘receive’ from the decoder 200. Only when the data invalid signal ‘datadis’ is at the L level (false), the strobe signal generator 203 outputs the data receiving signal ‘receive’ being input to the FIFO 201 as a strobe signal ‘strobe’.
The strobe signal generator 203 as an example includes an inverter circuit 231 and an AND circuit 232. To an input terminal of the inverter circuit 231, the data invalid signal ‘datadis’ is input from the data invalid signal generator 202. The data invalid signal ‘datadis’ inverted by the inverter circuit 231 is input to one input terminal of the AND circuit 232. Further, to the other input terminal of the AND circuit 232, the data receiving signal ‘receive’ is input from the decoder 200. The strobe signal ‘strobe’ output from an output terminal of the AND circuit 232 is input to the FIFO 201.
The FIFO 201 receives and stores the receiving data ‘data2’ from the decoder 200 inside thereof according to the strobe signal ‘strobe’ input from the data invalid signal generator 202. For example, the FIFO 201 stores the receiving data ‘data2’ input from the decoder 200 inside thereof according to the strobe signal ‘strobe’, which is input from the data invalid signal generator 202, raising from the L level to the H level.
Further, corresponding to an input of the read signal ‘read’ from the reception side bus 40, the FIFO 201 outputs the data stored in the memory inside to the reception side bus 40 as the data ‘data 3’ in order that the data has been stored. Further, the FIFO 201 monitors the data amount stored inside. If the data amount stored inside reaches a certain rate that is preliminary defined with respect to the data amount storable in the FIFO 201 or more, the FIFO 201 outputs the read request signal ‘readreq’ to the reception side bus 40.
The receiving data counter 204 increments the number of pieces of the receiving data stored in the counter memory 210 corresponding to the strobe signal ‘strobe’ input from the strobe signal generator 203.
For example, corresponding to the input of the strobe signal ‘strobe’, the receiving data counter 204 reads the number of pieces of the receiving data stored in the receiving data counter 204. After incrementing the number of pieces of the receiving data being read by one, the receiving data counter 204 stores the number of pieces of the receiving data incremented in the receiving data counter 204. According to the above, the receiving data counter 204 increments the number of pieces of the receiving data stored in the transmit data counter 204 by updating the number of pieces of the receiving data stored therein.
After reading the number of pieces of the receiving data from the counter memory 210, and reading the number of pieces of the burst data from the data length memory 211, the receiving completion detector 205 detects whether the number of pieces of the receiving data and the number of pieces of the burst data correspond with each other or not. Further, in a case of detecting that the number of pieces of the receiving data and the number of pieces of the burst data correspond with each other, the receiving completion detector 205 outputs a receiving confirmation signal that is the confirmation signal line ‘comp1’ at the H level to the receiving completion reporter 206. Further, while outputting the confirmation signal line ‘comp1’ at the H level, the receiving completion detector 205 makes an output of the confirmation signal line ‘comp1’ be at the L level corresponding to the input of the symbol I signal ‘inv’ at the H level from the data invalid signal generator 202.
Corresponding to the input of the confirmation signal line ‘comp I’ at the H level from the receiving completion detector 205, the receiving completion reporter 206 transmits the receiving completion signal that is the confirmation signal line ‘comp2’ at the H level to the transmitter 10 through the confirmation signal line ‘comp2’. Further, while transmitting the receiving completion signal that is the confirmation signal line ‘comp 2’ at the H level, the receiving completion reporter 206 makes an output of the confirmation signal line ‘comp2’ be at the L level corresponding to the input of the symbol I signal ‘inv’ at the H level from the data invalid signal generator 202.
[Operation of the Transmitter 10]
Next, an operation of the transmitter 10 will be described with reference to
First, at a timing t200 before the burst transmission, the encoder 100 outputs the reception enable signal ‘ena’ at the L level to the transmission side bus 30. Further, the encoder 100 receives the transmit control signal ‘send’ at the L level and the burst communication start signal ‘start’ at the L level from the transmission side bus 30. The encoder 100 further receives the transmit data ‘data1’ at the H level (data1) or at the L level (data0) from the transmission side bus 30 depending on the burst transmission performed immediately before. Furthermore, the encoder 100 outputs the symbol I to the receiver 20 through the two data transmission lines d0 and d1.
Next, at a timing t201, the encoder 100 receives the data 0 as the transmit data ‘data1’ from the transmission side bus 30. Next, at a timing t202, the encoder 100 receives the burst communication start signal ‘start’ at the H level from the transmission side bus 30. Corresponding to the input of the burst communication start signal ‘start’ at the H level at the timing t202, the encoder 100 makes the reception enable signal ‘ena’ be at the H level and outputs the symbol N to the receiver 20.
Next, at a timing t203, the encoder 100 receives the transmit control signal ‘send’ at the H level from the transmission side bus 30. Corresponding to the input of the transmit control signal ‘send’ at the H level at the timing t203, the encoder 100 outputs the symbol 0 to the receiver 20, and outputs the transmit signal ‘dsend’ at the H level to the transmit data counter 104.
Further, corresponding to the input of the transmit signal ‘dsend’ from the encoder 100 at the timing t203, the transmit data counter 104 increments the number of pieces of the transmit data stored in the transmit data counter 104. The number of pieces of the transmit data incremented is defined as 1.
Next, at a timing t204, the encoder 100 receives the transmit control signal ‘send’ at the L level from the transmission side bus 30. Corresponding to the input of the transmit control signal ‘send’ at the L level at the timing t204, the encoder 100 outputs the symbol N to the receiver 20, and makes the transmit signal ‘dsend’ be at the L level.
Next, at a timing t205, the encoder 100 receives the data 1 as the transmit data ‘data1’ from the transmission side bus 30. Then, at a timing t206, the encoder 100 receives the transmit control signal ‘send’ at the H level from the transmission side bus 30. Corresponding to the input of the transmit control signal ‘send’ at the H level at the timing t206, the encoder 100 outputs the symbol 1 to the receiver 20, and outputs the transmit signal ‘dsend’ at the H level to the transmit data counter 104.
Further, corresponding to the input of the transmit signal ‘dsend’ from the encoder 100 at the timing t206, the transmit data counter 104 increments the number of pieces of the transmit data stored in the transmit data counter 104. The number of pieces of the transmit data increased is defined as 2.
Furthermore, corresponding to that the number of pieces of the transmit data stored in the transmit data counter 104 is 2 at the timing t206, the last data detector 105 outputs the last data signal ‘lastdata’ at the H level to the encoder 100. Corresponding to the input of the last data signal ‘lastdata’ at the H level at the timing t206, the encoder 100 outputs the reception enable signal ‘ena’ at the L level to the transmission side bus 30.
Next, at a timing t207, the encoder 100 receives the transmit control signal ‘send’ at the L level from the transmission side bus 30. Corresponding to the input of the transmit control signal ‘send’ at the L level and the last data signal ‘lastdata’ at the H level at the timing t207, the encoder 100 outputs the symbol I to the receiver 20. Further, corresponding to the input of the transmit control signal ‘send’ at the L level at the timing t207, the encoder 100 makes the transmit signal ‘dsend’ be at the L level.
Next, at a timing t208, the initial setting unit 101 receives the confirmation signal line ‘comp2’ at the H level from the receiver 20. Next, at the timing t208, corresponding to the reception of the confirmation signal line ‘comp2’ at the H level from the receiver 20, the initial setting unit 101 outputs the confirmation signal line ‘comp3’ at the H level to the transmission side bus 30. Further, at the timing t208, corresponding to the reception of the confirmation signal line ‘comp2’ at the H level from the receiver 20, the last data detector 105 makes the last data signal ‘lastdata’ be at the L level.
Next, corresponding to that the initial setting unit 101 outputs the confirmation signal line ‘comp3’ at the H level to the transmission side bus 30 at the timing t208, the encoder 100 receives the burst communication start signal ‘start’ at the L level from the transmission side bus 30 at a timing t209.
Next, at a timing t210, the initial setting unit 101 receives the confirmation signal line ‘comp2’ at the L level from the receiver 20. At the timing t208, corresponding to the reception of the confirmation signal line ‘comp2’ at the L level from the receiver 20, the initial setting unit 101 outputs the confirmation signal line ‘comp3’ at the L level to the transmission side bus 30.
[Operation of the Receiver 20]
Next, an operation of the receiver 20 will be described with reference to
First, at a timing t300 before communication starts, the receiver 20 receives both the data transmission lines d0 and d1 at the H level. That is, the receiver 20 receives the symbol I from the transmitter 10 through the data transmission lines d0 and d1.
At the timing t300, the symbol I signal ‘inv’ output from the decoder 200 is at the H level. Further, the symbol N signal ‘null’ output from the decoder 200 is at the L level. Further, the receiving signal ‘receive’ output from the decoder 200 is at the L level. Further, the data invalid signal ‘datadis’ output from the data invalid signal generator 202 is at the H level. Further, the strobe signal ‘strobe’ output from the strobe signal generator 203 is at the L level. Further, the number of pieces of the receiving data stored in the counter memory 210 is 0.
Next, at a timing t301, the decoder 200 receives the symbol 0. The symbol 0 is a hazard and indefinite. At the timing t301 corresponding to the reception of the symbol 0, the decoder 200 makes the symbol 1 signal ‘inv’ be at the L level and makes the data receiving signal ‘receive’ be at the H level so as to output the data 0 as the receiving data ‘data2’.
At the timing t301, because the data invalid signal ‘datadis’ output from the data invalid signal generator 202 is at the H level, the decoder 200 makes the data receiving signal ‘receive’ be at the H level. However, the strobe signal ‘strobe’ output from the strobe signal generator 203 is maintained to be at the L level. Therefore, data is not written in the FIFO 201, and further the receiving data counter 204 does not count up the number of pieces of the receiving data stored in the counter memory 210. That is, the strobe signal generator 203 can mask the data receiving signal ‘receive’ at the H level output from the decoder 200 by the data invalid signal ‘datadis’ output from the data invalid signal generator 202 corresponding to indefinite receiving data caused by a hazard.
Next, at a timing t302, the decoder 200 receives the symbol N. At the timing t302, the decoder 200 makes the symbol N signal ‘null’ be at the H level and makes the data receiving signal ‘receive’ be at the L level corresponding to the reception of the Symbol N. Further, corresponding to that the symbol N signal ‘null’ is at the H level, the data invalid signal generator 202 makes the data invalid signal ‘datadis’ to be at the L level.
Next, at a timing t303, the decoder 200 receives the symbol 0. At the timing t303, corresponding to the reception of the symbol 0, the decoder 200 makes the symbol N signal ‘null’ be at the L level and makes the data receiving signal ‘receive’ be at the H level so as to output the data 0 as the receiving data ‘data2’.
At the timing t303, because the data invalid signal ‘datadis’ output from the data invalid signal generator 202 is at the L level, corresponding to that the data receiving signal ‘receive’ is at the H level, the strobe signal generator 203 makes the strobe signal be at the H level.
Further, at the timing t303, corresponding to that the strobe signal ‘strobe’ becomes at the H level, the FIFO 201 stores the data 0 input as the receiving data ‘data2’. Further, the receiving data counter 204 increments the number of pieces of the receiving data stored in the counter memory 210. The number of pieces of the receiving data incremented is defined as 1.
Next, at a timing t304, the decoder 200 receives the symbol N. Then, at a timing t305, the decoder 200 receives the symbol 1. Operations of the decoder 200, the strobe signal generator 203, the FIFO 201, and the receiving data counter 204 at the timing t304 and the timing t305, are the same as those at the timing t302 and the timing t303.
However, at the timing t305, the data that the FIFO 201 stores is the data 1 and the number of pieces of the receiving data stored in the counter memory 210 is 2 unlike the timing t302 and the timing t303. Further, unlike the timing t302 and the timing t303, the data invalid signal ‘datadis’ output from the data invalid signal generator 202 is maintained in the L level.
Next, corresponding to that the number of pieces of the receiving data stored in the counter memory 210 becomes 2 at the timing t305, the receiving completion detector 205 makes the confirmation signal line ‘comp1’ be at the H level. Corresponding to that the confirmation signal line ‘comp1’ becomes at the H level at the timing t305, the receiving completion reporter 206 transmits the acknowledged signal ‘ack’ that is the confirmation signal line ‘comp2’ at the H level to the transmitter 10 through the confirmation signal line ‘comp2’.
Next, at a timing t307, the decoder 200 receives the symbol I. At the timing t307, the decoder 200 makes the symbol I signal ‘inv’ be at the H level and makes the data receiving signal ‘receive’ be at the L level corresponding to the reception of the symbol I. Further, at the timing 307, corresponding to that the symbol I signal ‘inv’ is at the H level, the data invalid signal generator 202 makes the data invalid signal ‘datadis’ be at the H level. Further, at the timing t307, corresponding to that the data receiving signal ‘receive’ becomes the L level, or the data invalid signal ‘datadis’ becomes the H level, the strobe signal generator 203 makes the strobe signal be at the L level.
Next, corresponding to that the symbol I signal ‘inv’ is at the H level at the timing t307, the receiving completion detector 205 makes the confirmation signal ‘comp1’ be at the L level, while the receiving completion reporter 206 makes the confirmation signal ‘comp2’ be at the L level.
Next, a configuration of a receiver 21 that is a high speed serial data transfer system according to a second embodiment of the invention will be described with reference to
In the high speed serial data transfer system according to the first embodiment, the receiver 20 stores serial data and outputs the stored serial data in serial form to the reception side bus 40. Unlike the high speed serial data transfer system according to the first embodiment, the high speed serial data transfer system according to the second embodiment is formed so that the receiver 21 corresponding to the receiver 20 stores parallel data and enables parallel output of the stored parallel data to the reception side bus 40.
In the receiver 21 according to the second embodiment shown in
The FIFO 201 according to the first embodiment sequentially stores and outputs data in 1 bit. On the other hand, the FIFO 221 according to the second embodiment sequentially stores data in a predetermined bit number and sequentially outputs data in a predetermined bit number.
That is, the FIFO 201 stores serial data and outputs serial data. On the other hand, the FIFO 221 stores parallel data and outputs parallel data.
The data ‘data3’ output from the FIFO 201 is changed into data ‘data5’ output from the FIFO 221. The data ‘data3’ is serial data, while the data ‘data5’ is parallel data in n-bit.
The receiver 21 according to the second embodiment shown in
The serial-to-parallel converter 220 converts the serial data ‘data2’ decoded by the decoder 200 into parallel data ‘data4’ by the predetermined bit number (n-bit number) that is preliminary determined and outputs the converted parallel data ‘data4’.
For example, the serial-to-parallel converter 220 receives the serial data ‘data2’ from the decoder 200 and receives the strobe signal ‘strobe’ from the strobe signal generator 203. Corresponding to the input of the strobe signal ‘strobe’, the serial-to-parallel converter 220 converts the serial data ‘data2’ input by a predetermined bit that is preliminary determined into the parallel data ‘data4’ and outputs the converted parallel data to the FIFO 221. Further, the serial-to-parallel converter 220 outputs a strobe signal ‘strobep’ by a predetermined bit number that is preliminary determined to the FIFO 221 corresponding to the input of the strobe signal ‘strobe’.
The FIFO 221 receives the parallel data ‘data4’ and the strobe signal ‘strobep’ from the serial-to-parallel converter 220 and stores the parallel data ‘data4’ inside corresponding to the strobe signal ‘strobep’.
Further, corresponding to an input of the read signal ‘read’ from the reception side bus 40, the FIFO 201 outputs the data stored in the memory inside to the reception side bus 40 as the data ‘data 5’ in the predetermined bit number preliminary determined in order that the data has been stored.
As the above, compared to the high speed serial data transfer system according to the first embodiment, the high speed serial data transfer system according to the second embodiment can store the data received in the predetermined bit number preliminary determined by the serial-to-parallel converter 220 and the FIFO 221.
Further, the high speed serial data transfer system according to the second embodiment enables parallel output of the data stored in parallel form and in the predetermined bit number preliminary determined to the reception side bus 40 or the reception side bus master coupled to the reception side bus 40.
Next, a high-speed serial data transfer system according to a third embodiment of the invention will be described.
In the high speed serial data transfer system according to the first embodiment, the burst data length is preliminary determined between the transmitter 10 and the receiver 20. That is, the high-speed serial data transfer system in the first embodiment is for transmission of burst data having a fixed length. On the other hand, the high-speed serial data transfer system according to the second embodiment enables variable burst transmission and reception.
Unlike the high speed serial data transfer system according to the first embodiment, the high speed serial data transfer system according to the second embodiment is, firstly, made to include burst length setting information that is information of the number of pieces of the burst data into transmit data of burst communication.
Next, the transmitter 10 and the receiver 20 extract the burst length setting information included in the transmit data. Based on the extracted data, the number of pieces of the burst data for the data length memory 111 and the data length memory 211 is set, enabling variable burst transmission and reception.
First, two methods for including the burst length setting information into the transmit data of the burst communication will be explained with reference to
In a first method for including the burst length setting information into the transmit data shown in
In
In a second method for including the burst length setting information into the transmit data shown in
Next, a configuration of a transmitter 12 according to the third embodiment will be described with reference to
The transmitter 12 according to the third embodiment shown in
The data length setting unit 140 extracts the burst length setting information from the transmit data to be transmitted, and writes the extracted information in the data length memory 111, so that the burst length setting information having been extracted is set.
Next, a configuration of a receiver 22 according to the third embodiment will be described with reference to
The receiver 22 according to the third embodiment shown in
The data length setting unit 240 extracts the burst length setting information from receiving data having been received, and writes the extracted information in the data length memory 211, so that the burst length setting information being extracted is set.
Here, although information of the number of pieces of the burst data is included in the transmit data as the burst length setting information in the above, an index indicating a burst data length may be included instead of the information indicating a value of the burst data length in the transmit data.
For example, as shown in
Next, each of the data length setting unit 140 and the data length setting unit 240 extracts the burst data length index included in the transmit data described above, and reads a burst data length corresponding to the extracted index from the burst data length corresponding table included in each of the data length setting unit 140 and the data length setting unit 240.
Then, the data length setting unit 140 and the data length setting unit 240 write the burst data lengths having been read in the data length memories 111 and 211 respectively.
This enables the burst data length index to be transmitted alone by using the burst data length corresponding table. Therefore, the burst data length information is transmitted by using the smaller number of pieces of the data than that of the burst data length information itself.
As described above, compared to the high speed serial data transfer system according to the first embodiment, in the high speed serial data transfer system according to the third embodiment, the transmitter 12 includes the data length setting unit 140, and the receiver 22 includes the data length setting unit 240 so that the burst length setting information is included in the transmit data, achieving variable burst transmission and reception between the transmitter 12 and the receiver 22.
The third embodiment described above is applicable not only to the first embodiment, but also applicable to the second embodiment in a similar way.
Instead of the confirmation signal line ‘comp2’ coupling the transmitter 10 and the receiver 20 in
Further, instead of the confirmation signal line ‘comp3’ coupling the transmitter 10 and the transmission side bus 30 in
In the high speed serial data transfer system according to the first embodiment shown in
On the other hand, in the high speed serial data transfer system according to the fourth embodiment shown in
The acknowledged signal ‘ack’ indicates that a symbol transmitted through the data transmission lines d0 and d1 is not the symbol I, that is, the symbol is the symbol 0, the symbol 1, or the symbol N. Therefore, the acknowledged signal ‘ack’ includes the transmit data transmitted by burst transmission.
As the above, in the high speed serial data transfer system according to the fourth embodiment, the receiver 25 starts the communication.
[Outline Operation of the Transmitter 15 and the Receiver 25]
Next, referring to
Here, a case of burst transmission of the transmitter 15 transmitting the two transmit data, data 0 and data 1, will be described. That is, a case where the number of pieces of the burst data between the transmitter 15 and the receiver 25 is 2 will be explained.
First, at a timing t401 that is before transmission, the transmitter 15 transmits the symbol I.
Next, corresponding to the reception of the burst request signal through the burst request signal line ‘breq1’ from the reception side bus 40 at a timing t402, the receiver 25 transmits the burst request signal as the burst request signal line ‘breq2’ at the H level to the transmitter 15.
Next, corresponding to the reception of the burst request signal through the burst request signal line ‘breq2’, the transmitter 15 outputs the burst request signal that is the burst request signal line ‘breq3’ at the H level to the transmission side bus 30 through the burst request signal line ‘breq3’.
Next, the transmit bus master coupled to the transmission side bus 30 starts burst transmission corresponding to the reception of the burst request signal.
Corresponding to that the transmit bus master starts the burst transmission, the transmitter 15 starts transmitting transmit data at a timing t403, and outputs the symbol N at a timing t405. A signal output from the transmitter 15 between the timing t403 and the timing t405 is a hazard. In general, during the period between the time t403 and the time t405, there is a possibility to output the symbol 0 or the symbol 1, therefore, it is indefinite. Here, the explanation will be given in a case of the symbol 0 between the time t403 and the time t405.
Corresponding to the reception of the symbol 0 that is other than the symbol I at the timing t403, the receiver 25 makes the burst request signal line ‘breq2’ be at the L level at a timing t404. Corresponding to the reception of the symbol 0 that is other than the symbol I at the timing t403, the receiver 25 detects that the transmitter 15 has started burst transmission corresponding to the burst request signal.
Next, the transmitter 15 transmits the symbol 0 at a timing t406. The receiver 25 receives the symbol 0 as the transmit data symbol, and counts the transmit data symbol, defining the number of pieces of receiving data as 1. Next, the transmitter 15 transmits the symbol N at a timing t407, and transmits the symbol 1 at a timing t408.
The receiver 25 receives the symbol 1 as the transmit data symbol at the timing t408 and counts the transmit data symbol that is received, defining the number of pieces of receiving data as 2. By detecting that the number of pieces of the receiving data is 2, the receiver 25 detects that the burst transmission has terminated.
Since the transmitter 15 also counts the transmit data, the transmitter 15 also outputs the symbol I at a timing t409 upon detecting that the number of pieces of the receiving data is 2.
Next, a configuration of the transmitter 15 will be described with reference to
In
The burst request receiver 151 receives the burst request signal from the receiver 25 through the burst request signal line ‘breq2’.
Further, the burst request receiver 151 makes the received burst request signal be the burst request signal line ‘breq2’ at the H level so as to output the received burst request signal to the transmission side bus 30 through the burst request signal line ‘breq2’.
Then, the transmit bus master coupled to the transmission side bus 30 starts burst transmission upon receiving the burst request signal through the burst transmission side bus 30.
Next, a configuration of the receiver 25 will be described with reference to
In the fourth embodiment shown in
Further, in the first embodiment shown in
The burst request transmitter 251 receives the burst request signal from the reception side bus 40 through the burst request signal line ‘breq1’.
The burst request transmitter 251 transmits the burst request signal that has been input, to the transmitter 15 through the burst request signal line ‘breq2’.
Further, corresponding to the input of the symbol I signal ‘inv’ at the H level from the decoder 200, the burst request transmitter 251 terminates the transmission of the burst request signal that is transmitted to the transmitter 15 through the burst request signal line ‘breq2’.
Since the configuration and operation for the first embodiment and the fourth embodiment other than the above are the same, the description will be omitted.
Next, a configuration of a receiver 26 in a high speed serial data transfer system according to a fifth embodiment of the invention will be described with reference to
The receiver 26 according to the fifth embodiment is formed by adding a serial-to-parallel converter 220 between the decoder 200 and the FIFO 201 to the receiver 25 according to the fourth embodiment in
Further, similarly to this, the receiver 25 according to the fifth embodiment shown in
Therefore, similarly to the second embodiment with respect to the first embodiment, compared to the high speed serial data transfer system according to the fourth embodiment, the high speed serial data transfer system according to the fifth embodiment enables output in parallel form and in the predetermined bit number preliminary determined to the reception side bus 40, or the receiving bus master coupled to the reception side bus 40 by the serial-to-parallel converter 220 and the FIFO 221.
Next, configurations of a transmitter 17 and a receiver 27 in a high speed serial data transfer system according to a sixth embodiment of the invention will be described with reference to
The transmitter 17 according to the sixth embodiment shown in
Further, the receiver 27 according to the sixth embodiment shown in
Therefore, similarly to the high speed serial data transfer system according to the third embodiment being compared to the high speed serial data transfer system according to the first embodiment, in the high speed serial data transfer system according to the sixth embodiment, compared to the high speed serial data transfer system according to the fourth embodiment, the transmitter 17 includes the data length setting unit 140 and the receiver 27 includes the data length setting unit 240 so that the burst length setting information is included in the transmit data, achieving variable burst transmission and reception between the transmitter 17 and the receiver 27.
The sixth embodiment described above is applicable not only to the fourth embodiment, but also applicable to the fifth embodiment in a similar way.
Further, in the first to sixth embodiments, a case of communication between the transmitter and the receiver by employing four-way handshaking has been described. However, the communication can be also achieved by two-way handshaking.
Further, in the first to sixth embodiments, only a case of the burst transmission transmitting two transmit data between the transmitter and the receiver has been described. However, the invention is not limited to this, thereby burst transmission of transmit data in arbitrary number is possible.
In addition, in the first to sixth embodiments, it has been described that the data transmission lines d0 and d1 are respectively made of metal. The data transmission lines d0 and d1 can be replaced to optical fibers so as to achieve communication.
In this case, the encoder 100 includes a light emitter outputting a transmit symbol of a transmit data symbol, an identification symbol, or a non-transmit symbol through the optic fibers while the decoder 200 includes a light receiver to receive the transmit symbol through the optic fibers.
Further, the light emitter performs high-frequency modulation on an optical output corresponding to the transmit symbol. The light receiver receives and decodes high-frequency light modulated corresponding to the transmit symbol.
According to the above, when the high speed serial data transfer system according to the first to sixth embodiments is communicated through the optic fiber, the high speed serial data transfer system can communicate while reducing external influences such as electromagnetic waves.
Further, the high-speed serial data transfer system according to the first to sixth embodiments is possibly formed on a single silicon substrate so as to form a semiconductor device. This enables communication of a circuit in a semiconductor device formed on a single silicon substrate with the high-speed serial data transfer system.
Further, the high-speed serial data transfer system according to the first to sixth embodiments is possibly formed on a plurality of various silicon substrates so as to form a hybrid semiconductor device.
This enables communication of a circuit in a semiconductor device composed of various silicon substrates with the high-speed serial data transfer system.
The counter memory 110, the data length memory 111, the counter memory 210, and the data length memory 211 include a nonvolatile memory such as a hard disk drive, an optical magnetic disk drive, and a flash memory; a storage medium that is read only such as a CR-ROM; and a volatile memory such as a random access memory (RAM), or combination of them.
Further, a transmitter such as the transmitter 10, 12, 15 or 17, and a receiver such as the receiver 20, 21, 22, 25, 26, or 27 may be respectively realized by dedicated hardware, further, realized by a memory and a microprocessor.
The transmitter and the receiver may be realized by dedicated hardware, and alternatively composed of a memory and a CPU, and the function thereof may be realized by loading and executing a program to realize the function of the transmitter and the receiver.
In the above, although the embodiments of the invention have been described referring to the drawings, the concrete configurations are not limited to the embodiments. Therefore, designs or the like without departing from the scope and spirit of the invention are also included in the invention.
The high-speed serial data transfer system according to the invention is favorable for a communication device coupling various in-house manufacturing equipment.
Further, the high speed serial data transfer system according to the invention is favorable for a communication device in a semiconductor device performing at a high speed, with low power consumption, and having flexibility to be bent as it is made of a film or the like.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-123353 | May 2007 | JP | national |
