This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2012-128688 filed Jun. 6, 2012.
(i) Technical Field
The present invention relates to a transmitting and receiving system, a transmitting and receiving method, and a computer readable medium.
(ii) Related Art
There is known a system that detects an error occurred during transmission using a cyclic redundancy check (CRC) code as an error-detecting code, transmits as a reception response a positive acknowledgement (ACK) when reception is successful, and transmits a negative acknowledgement (NAK) when an error is detected.
According to an aspect of the invention, there is provided a transmitting and receiving system that includes a first transmitting and receiving apparatus including a generating unit that generates a transmission packet by attaching an error correction code to data to be transmitted, the data being subjected to a bit number conversion, wherein a code that detects or corrects, in the case where a single-bit error occurs, the single-bit error is used as information bits contained in a header of the transmission packet, the code being used when a bit error uncorrectable by the error correction code occurs due to transmission during transmission of the transmission packet, and a transmitting unit that transmits the transmission packet.
Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:
Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the components having the substantially same functions are denoted by the same reference numerals, and the same description will not be repeated.
(Configuration of First Transmitting and Receiving Apparatus)
As illustrated in
(Configuration of Second Transmitting and Receiving Apparatus)
As illustrated in
(Transmission Path)
In this exemplary embodiment, an electric cable for transmitting electrical signals is used as the transmission path 3. However, an optical cable for transmitting optical signals may alternatively be used. In the case of using an optical cable, a photoelectric converter needs to be provided in each of the transmitting end and receiving end. Each of the lanes 31, 32, and 33 of the transmission path 3 includes two transmission lines, and may be a differential line for transmitting differential signals. The number of lanes included in the transmission path 3 is not limited to three.
(Configuration of Components of First Transmitting and Receiving Apparatus)
The input and output controller 21 of the first transmitting and receiving apparatus 2 exchanges data with a reproduction apparatus, for example. The input and output controller 43 of the second transmitting and receiving apparatus 4 exchanges data with a video display apparatus, for example. Further, the input and output controller 21 of the first transmitting and receiving apparatus 2 includes a transmission buffer (not shown) that holds transmitted data for a predetermined time period. It is to be noted that the transmission buffer may hold transmitted data until a positive acknowledgement (ACK) is received. Data exchange may be performed not only between the reproduction apparatus and the video display apparatus, but also between an image information generating apparatus and an image forming apparatus.
The transmit packet generating unit 22 includes 8B10B converters (8B10B) 221A and 221B and ECC generating units 222A and 222B, which are provided to correspond to the first lane 31 and the second lane 32, and generates a transmit packet by putting data to be transmitted (transmission data) (e.g., image information) into a packet. The transmit packet will be described below in greater detail. The transmit packet is an example of a transmission packet.
The transmit packet generating unit 22 puts data of a fixed length (e.g., 100 bytes) to be transmitted into a packet by attaching a header and an ECC (described below) thereto.
Each of the 8B10B converters 221A and 221B performs, as a bit number conversion, an 8B10B conversion on 8-bit data using a conversion table so as to output data in units of 10 bits. The 8B10B conversion is configured to adjust the DC balance such that the transmission data contain the moderate amount of 0s and 1s. A scheme known as 8B10B conversion adjusts the DC balance by converting data of 8 bits into data of 10 bits having a predetermined ratio of 0s to 1s, which is close to 50%.
Each of the ECC generating units 222A and 222B performs an error correction coding (ECC) operation, and generates a transmit packet by attaching the obtained ECC to the data to be transmitted. The ECC is an encoding technique that transmits transmission data with a redundant bit attached thereto such that the receiving end can perform an error detection so as to determine whether the received data are correct, and correct an error if the error is correctable. In the exemplary embodiments of the present invention, well-known ECCs such as Hamming codes and Reed-Solomon codes may be used. The ECC is an example of an error correction code.
Each of the parallel-to-serial converters 23A and 23B is configured to convert parallel data to serial data (P/S conversion) and send the converted data, and includes a register for setting a de-emphasis that attenuates direct-current components of the signal waveform, a pre-emphasis that emphasizes high-frequency components of the signal waveform, a differential voltage, and the like, as the initial settings upon power-on.
The serial-to-parallel converter 24 is configured to convert serial data to parallel data (S/P conversion), and includes a register for setting an equalizer that compensates for degradation of the signal waveform occurred in the transmission path 3 and the like, as the initial settings upon power-on.
The 10B8B converter 25 performs, as an inverse conversion of the number of bits, an 8B10B inverse conversion (10B8B conversion) on 10-bit data using a conversion table so as to output data in units of 8 bits.
The retransmission controller 26 instructs the input and output controller 21 to perform a retransmission in response to a retransmission request packet transmitted from the second transmitting and receiving apparatus 4 to the first transmitting and receiving apparatus 2.
(Configuration of Components of Second Transmitting and Receiving Apparatus)
Each of the serial-to-parallel converters 41A and 41B has the same configuration as the serial-to-parallel converter 24 of the first transmitting and receiving apparatus 2, and is configured to convert serial data to parallel data (S/P conversion).
The error detecting unit 42 includes ECC error detecting and correcting units 421A and 421B, 10B8B converters (10B8B) 422A and 422B, and header error detecting and correcting units 423A and 423B, which are provided to correspond to the first lane 31 and the second lane 32.
Each of the ECC error detecting and correcting units 421A and 421B extracts data from a transmit packet transmitted from the first transmitting and receiving apparatus 2, performs an ECC check, and reports the ECC check results to the retransmission request packet generating unit 44. More specifically, if there is no ECC error or if there is an ECC error of two or more bits, each of the ECC error detecting and correcting units 421A and 421B outputs data as they are to the subsequent stage. If there is a single-bit ECC error, each of the ECC error detecting and correcting units 421A and 421B outputs data to the subsequent stage after performing an error correction. The ECC error detecting and correcting units 421A and 421B are examples of a correcting unit.
Each of the 10B8B converters 422A and 422B performs, as an inverse conversion of the number of bits, an 8B10B inverse conversion (10B8B conversion) on 10-bit data using a conversion table so as to output data in units of 8 bits.
Each of the header error detecting and correcting units 423A and 423B performs a header check so as to determine whether there is an error with a header 110, and reports the header check results to the retransmission request packet generating unit 44. The header check results contain information indicating the presence or absence of an error, the error type (ID error, NIT error), and the data type. More specifically, each of the header error detecting and correcting units 423A and 423B performs an error correction if there is a single-bit error in the header 110, outputs data to the subsequent stage if the data are image information, discards data if the data are information other than image information, and switches the mode to a retransmission mode if there is a not-in-table (NIT) error. The “NIT error” as used herein refers to an error indicating that data are not present in an 8B10B conversion table. The header error detecting and correcting units 423A and 423B are examples of a correcting unit.
The retransmission request packet generating unit 44 is configured to, on the basis of the ECC check results reported from the ECC error detecting and correcting units 421A and 421B and the header check results reported from the header error detecting and correcting units 423A and 423B, switch the mode to the retransmission mode if the ECC error is in two or more bits and if the header 110 has a NIT error, and generate a retransmission request packet and transmit the retransmission request packet to the first transmitting and receiving apparatus 2 if the header 110 has an error other than a NIT error and if the data are information other than image information. The retransmission request packet contains a header indicating that the packet is a retransmission request, and a sequence ID of data whose retransmission is requested. The retransmission request packet will be described below in greater detail. The retransmission request packet generating unit 44 is an example of a generating unit. The retransmission request packet is an example of a response packet.
The 8B10B converter 45 performs, as a bit number conversion, an 8B10B conversion on 8-bit data using a conversion table so as to output data in units of 10 bits.
The parallel-to-serial converter 46 has the same configuration as the parallel-to-serial converters 23A and 23B of the first transmitting and receiving apparatus 2, and is configured to convert parallel data to serial data (P/S conversion) and send the converted data.
Part or all of the elements of each of the first and second transmitting and receiving apparatuses 2 and 4 may be formed of hardware circuits such as a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC). Alternatively, the elements of the first and second transmitting and receiving apparatuses 2 and 4 may be realized by a CPU operating in accordance with a program illustrated in
(Structure of Transmit Packet)
(Structure of Retransmission Request Packet)
(Error Patterns)
Next, error patterns will be described. In the case of transmitting data of 8 bits, the data are converted into data of 10 bits by an 8B10B conversion. There are 10 patterns of single-bit error which may occur to this 10-bit data.
In the case of Dxx.0 (see
Accordingly, in this exemplary embodiment, Dxx.0 and Dxx.3 are used as the identification information item 112 contained in the header 110 of the transmit packet 100. More specifically, when the data 120 are image information, Dxx.0 is used as the identification information item 112, and the data identification information 112a of the higher-order 3 bits are set to “000”. On the other hand, when the data 120 are information other than image information, Dxx.3 is used as the identification information item 112, and the data identification information 112a of the higher-order 3 bits are set to “011”. Accordingly, even if a single-bit error occurs in the data identification information 112a, it is possible to correct the error. Further, in the case where a single-bit error occurs in the lower-order 5 bits, i.e., the sequence ID 112b in the identification information item 112, a NIT error is caused. This prevents the sequence ID from being incorrectly recognized.
Next, exemplary operations in the present exemplary embodiment will be described with reference to the flowcharts of
(1) Generation of Transmit Packet
The transmit packet generating unit 22 of the first transmitting and receiving apparatus 2 puts data 120 to be transmitted, which are output from the input and output controller 21, into a packet by adding a header 110. The 8B10B converters 221A and 221B perform an 8B10B conversion on the header 110 and the data 120 included in the packet, and the ECC generating units 222A and 222B perform an ECC operation on the 8B10B-converted data 120 so as to generate an ECC 130. Then, the transmit packet generating unit 22 generates transmit packet 100 which contains the header 110, the data 120, and the ECC 130.
The transmit packet generating unit 22 uses Dxx.y (xx: 0 through 31, y=0, 3) shown in
(2) Transmission of Transmit Packet
The transmit packet 100 generated by the transmit packet generating unit 22 is converted from parallel data to serial data by the parallel-to-serial converters 23A and 23B, and is serially transmitted from the first transmitting and receiving apparatus 2 to the second transmitting and receiving apparatus 4 through the first lane 31 and the second lane 32, respectively, of the transmission path 3.
(3) Reception of Transmit Packet
The transmit packet 100 received by the second transmitting and receiving apparatus 4 is converted from the serial data to parallel data by the serial-to-parallel converters 41A and 41B, and is input to the error detecting unit 42.
(4) ECC Check
The ECC error detecting and correcting units 421A and 421B of the error detecting unit 42 perform an ECC check, and report the ECC check results to the retransmission request packet generating unit 44 (S1). If there is a single-bit ECC error, the ECC error detecting and correcting units 421A and 421B correct the single-bit ECC error (S2), and output the data to the 10B8B converters 422A and 422B, respectively. The 10B8B converters 422A and 422B perform an 8B10B inverse conversion on the data (S3), and output the data to the input and output controller 43 through the header error detecting and correcting units 423A and 423B, respectively. The data are stored in a memory (not shown) in the input and output controller 43 (S4).
If there is an ECC error of two or more bits in the ECC check of the above Step S1, the ECC error detecting and correcting units 421A and 421B cannot correct the ECC error, and therefore output the data to the 10B8B converters 422A and 422B, respectively. The 10B8B converters 422A and 422B perform an 8B10B inverse conversion on the data (S5), and output the data to the header error detecting and correcting units 423A and 423B, respectively.
(5) Header Check
The header error detecting and correcting units 423A and 423B perform a header check on the header 110, and report the header check results to the retransmission request packet generating unit 44 (S6). If there is no error in the header 110, the header error detecting and correcting units 423A and 423B determine whether the type of the data 120 is image information on the basis of the data identification information 112a (S7). If the data type is image information (S7: Yes), the data are output to the input and output controller 43. The data are stored in a memory (not shown) in the input and output controller 43 (S4). The reason why the same operations as those performed in the case where there is no ECC error are performed even if an ECC error of two or more bits is present is because, if the data are image information, one corrupted byte in the data only creates one pixel with incorrect information, which does not cause a problem.
If there is a single bit error (ID error) in the data identification information 112a (ID) in the header 110 in the header check of the above Step S6, the header error detecting and correcting units 423A and 423B correct the data identification information 112a (ID) using the table of
(6) Retransmission Mode
If the type of the data 120 is not image information in the above Steps S7 and S9, the data 120 are discarded, and a NAK is returned so as to switch the mode to the retransmission mode (S10). Similarly, if a NIT error is detected in the header 110 in the header check of the above Step S6, the data are discarded, and a NAK is returned so as to switch the mode to the retransmission mode (S10). More specifically, the retransmission request packet generating unit 44 generates a retransmission request packet 200 that contains a start packet 210, a negative acknowledgement (NAK) 211a, and a sequence ID 211b, as illustrated in
The retransmission request packet 200 transmitted from the first transmitting and receiving apparatus 2 is converted from serial data to parallel data by the serial-to-parallel converter 24, is subjected to a 10B8B conversion by the 10B8B converter 25, and is input to the retransmission controller 26.
An error detecting unit 261 of the retransmission controller 26 performs an error check on the response information item 211. If an error is detected, an error correcting unit 262 corrects the error. The transmission data shown in
The input and output controller 21 transmits data held in the transmission buffer for retransmission and corresponding to the sequence ID to the transmit packet generating unit 22. The transmit packet generating unit 22 generates a transmit packet 100 whose retransmission is instructed. The regenerated transmit packet 100 is parallel-to-serial converted, and then is transmitted to the second transmitting and receiving apparatus 4, in the manner described above.
As illustrated in
In the ECC check of the above Step S11, if there is an ECC error of two or more bits, as in the case of the flow of
In the header check of the above Step S17, if there is a NIT error, a system failure is determined to be caused.
More specifically, a first transmitting and receiving apparatus 2 of this exemplary embodiment includes an input and output controller 21, a transmit packet generating unit 22, parallel-to-serial converters (P/S) 23A and 23B, a serial-to-parallel converter (S/P) 24, a 10B8B converter (10B8B) 25, and a retransmission controller 26.
The second transmitting and receiving apparatus 4 includes serial-to-parallel converters (S/P) 41A and 41B, an error detecting unit 42, an input and output controller 43, an 8B10B converter (8B10B) 45, a parallel-to-serial converter (P/S) 46, and a response packet generating unit 47. The response packet generating unit 47 is an example of a generating unit.
As shown in
As shown in FIG. 8B, a NAK response packet 200b includes a start packet 210 including, for example, K28.0, and plural (e.g., three) response information items 211. Each response information item 211 includes a negative acknowledgement (NAK) 211a of the higher-order 3 bits, and a sequence ID 211b of the lower-order 5 bits for identifying the lanes 31 and 32 and the transmit packet 100. As the response information item 211 of the NAK response packet 200b, a code that makes it possible to distinguish between an positive acknowledgement (ACK) and a negative acknowledgement (NAK) even in the case where a single-bit error due to transmission occurs during transmission of the NAK response packet 200b to the first transmitting and receiving apparatus 2 is used. For example, Dxx.3 may be used. With this configuration, the second transmitting and receiving apparatus 4 transmits the response information item 211 three times. It is possible to determine in which of the lanes 31 and 32 and to which transmit packet 100 an error has occurred, on the basis of the negative acknowledgement (NAK) 211a and the sequence ID 211b. It is to be noted that Dxx.3 may be used for the response information item 211 of the ACK response packet 200a, and Dxx.0 may be used for the response information item 211 of the NAK response packet 200b. The number of response information items 211 included in the NAK response packet 200b is not limited to three.
A transmit packet 100 of this exemplary embodiment contains a header 110, data 120, and an ECC 130 in the same manner as that of the first exemplary embodiment, but differs from that of the first exemplary embodiment in the configuration of an identification information item 112 of the header 110. More specifically, the identification information item 112 includes data identification information 112a of 3 bits for identifying whether the data 120 are image information or information other than image information, and color information 112c of 5 bits indicating color information of the data 120 representing image information. As for the color information 112c, “00001” may represent yellow; “00010” may represent magenta; “00100” may represent cyan; “01000” may represent black; and “10000” may represent a special color. It is to be noted that the relationship between the code of 5 bits and the color is not limited thereto.
A transmit packet 100 of this exemplary embodiment contains a header 110, data 120, and an ECC 130 in the same manner as that of the first exemplary embodiment, but differs from that of the first exemplary embodiment in the configuration of an identification information item 112 of the header 110. More specifically, the identification information item 112 includes data identification information 112a of 3 bits for identifying whether the data 120 are image information or information other than image information, monochrome/color identification information 112d of 1 bit indicating whether the data 120 representing image information are in a monochrome mode or a color mode, and color information 112c of 4 bits indicating color information of the data 120 representing image information. As for the monochrome/color identification information 112d and the color information 112c, “10000” may represent the monochrome mode; “00001” may represent yellow in the color mode; “00010” may represent magenta in the color mode; “00100” may represent cyan in the color mode; and “01000” may represent black in the color mode. It is to be noted that the relationship between the code of 5 bits and the color is not limited thereto.
The foregoing description of the exemplary embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art.
Further, part of the elements of the above exemplary embodiments may be omitted, and steps in the flows of the above exemplary embodiments may be added, deleted, modified, or rearranged, without departing from the scope of the present invention. Furthermore, programs used in the above exemplary embodiments may be stored and provided in a recording medium such as a CD-ROM.
Number | Date | Country | Kind |
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2012-128688 | Jun 2012 | JP | national |