Patent Grant
12010379
The present application is a continuation of International Application No. PCT/CN2021/100921 filed on Jun. 18, 2021, which is based upon and claims priority to Chinese Patent Application Serial No. 202011432933.X on 9 Dec. 2020, the disclosure of which is herein by incorporated by reference.
The disclosure relates to the technical field of communications, and particularly to a transmitting method, a receiving method, a transmitting device, and a receiving device for high-definition video data.
With the rapid development of science and technology, people have higher and higher requirements for the clarity, image quality or fluency during video playing, and have requirements on farther and farther video transmission distance. However, a high-definition video has a relatively large data volume. Therefore, a higher transmission bandwidth is required. At the present, there are very few products in the market that can meet the above requirements, and their results are not satisfactory.
Based on the above problems and the shortcomings of the prior art, the disclosure provides a transmitting method, a receiving method, a transmitting device, and a receiving device for high-definition video data. The transmitting device can transmit the high-definition video data to the receiving device through a first communication module and based on a network cable or an optical fiber. Lossless high-definition video transmission with ultra-low latency can be realized.
In a first aspect, a transmitting method for high-definition video data is provided, where the transmitting method includes the following.
The high-definition video data with different color space formats is obtained, by the transmitting device, via an input interface.
The high-definition video data is processed, by the transmitting device, into a data packet.
The data packet is transmitted, by the transmitting device, to a first communication module. The transmission rate of the first communication module is not less than a first threshold, and the first communication module is configured to transmit the data packet.
In a second aspect, a receiving method for high-definition video data is provided, where the receiving method includes the following.
The data packet is obtained, by a receiving device, by a second communication module. the transmission rate of the second communication module is not less than a second threshold.
The data packet is processed, by the receiving device, to obtain high-definition video data.
In a third aspect, a transmitting device is provided. The transmitting device includes a memory and a processor coupled to the memory. The memory is configured to store an application program code, and the processor is configured to call the application program code to obtain high-definition video data with different color space formats, process the high-definition video data into a data packet, and transmit the data packet to a first communication module, wherein the transmission rate of the first communication module is not less than a first threshold, and the first communication module is configured to transmit the data packet.
In a fourth aspect, a receiving device is provided. The receiving device includes a memory and a processor coupled to the memory. The memory is configured to store an application program code. The processor is configured to call the application program code to
The disclosure provides a transmitting method, a receiving method, a transmitting device, and a receiving device for high-definition video data. The transmitting method includes the following. The high-definition video data with different color space formats is obtained by the transmitting device via an input interface. The high-definition video data is processed by the transmitting device into a data packet. The data packet is transmitted by the transmitting device to a first communication module, and the first communication module is configured to transmit the data packet to the receiving device. By the adoption of the disclosure, the high-definition video data can be transmitted by the transmitting device to the receiving device by the first communication module and based on a network cable or an optical fiber, so that lossless high-definition video transmission with ultra-low latency can be realized.
In order to explain the technical solutions in the implementations of the disclosure more clearly, the drawings used in the description of the implementations are briefly introduced below. Obviously, the drawings in the following description are some implementations of the disclosure. For ordinary technicians, other drawings can be obtained based on these drawings without paying creative efforts.
The technical solutions in the disclosure will be described clearly and completely in combination with the accompanying drawings in the disclosure. Obviously, the embodiments described are part of the implementations of the disclosure, but not all of the implementations.
At block 101, high-definition video data with different color space formats through an input interface is obtained by a transmitting device.
According to an embodiment of the disclosure, the transmitting device obtains high-definition video data with different color space formats via an input interface may include, but not limited to, the following.
Method 1: the high-definition video data with different color space formats is obtained by the transmitting device based on a high definition multimedia interface (HDMI) protocol. Specifically,
The high-definition video data may include, but not limited to, multimedia data such as characters, data, sounds, graphs, images or videos (such as 1080P, 4K or 8K high-definition videos with a frame rate of 30 FPS, 60 FPS, 100 FPS or 120 FPS). The high-definition video data may further include, but not limited to, the following characteristic: high dynamic range imaging (HDR). Different color space formats may be YUV of 4:2:2, YUV of 4:2:0, YUV of 4:4:4, or RGB of 8 bit depth.
Method 2: the high-definition video data with different color space formats is obtained by the transmitting device through a Type-C protocol.
Method 3: the high-definition video data with different color space formats is obtained by the transmitting device through a universal serial bus (USB) protocol.
Method 4: the high-definition video data with different color space formats is obtained by the transmitting device through a video graphics array (VGA) protocol.
Method 5: the high-definition video data with different color space formats is obtained by the transmitting device through a display port (DP) protocol.
Method 6: the high-definition video data with different color space formats is obtained by the transmitting device through a mobile industry processor interface (MIPI) protocol.
Method 7: the high-definition video data with different color space formats is obtained by the transmitting device through a low-voltage differential signaling (LVDS) protocol.
Method 8: the high-definition video data with different color space formats is obtained by the transmitting device through a transistor transistor logic (TTL) protocol.
Method 9: the high-definition video data with different color space formats is obtained by the transmitting device through a digital visual interface (DVI) protocol.
At block 102, the high-definition video data is processed by the transmitting device into a data packet.
According to an embodiment of the disclosure, the high-definition video data may be processed by the transmitting device into a data packet in the following ways.
Way 1: the transmitting device further includes a conversion chip. The conversion chip and a first integrated circuit are independently integrated in the transmitting device respectively. Specifically,
The first interface protocol includes the HDMI protocol, the DVI protocol, the Type-C protocol, the DP protocol, the USB protocol, the MIPI protocol, or the VGA protocol. The second interface protocol includes the TTL protocol, the LVDS protocol, the MIPI protocol, or a custom interface protocol. The custom interface protocol may be configured to realize hybrid transmission of audios and videos in the high-definition video data. The TTL protocol and the LVDS protocol may respectively realize separate transmission of the audios and videos in the high-definition video data.
More specifically, the transmitting device transmits the high-definition video data to the conversion chip in the FPGA chip based on the first interface protocol, and adds, by the FPGA chip integrated in the transmitting device, a UDP data packet header and a UDP data packet tail to the high-definition video data that is transmitted by the conversion chip based on the second interface protocol. The UDP data packet header or the UDP data packet tail may separately include a destination address, a source address, a port number, a flag bit, and other control information.
Or,
the transmitting device transmits the high-definition video data to the conversion chip in an FPGA chip based on a first interface protocol, and encapsulates, by the FPGA chip based on a transmission control protocol (TCP), the high-definition video data transmitted by the conversion chip based on a second interface protocol to obtain a UDP data packet. More specifically,
The communication protocol may include, but not limited to, the UDP, the TCP, or the custom communication protocol.
Way 2: the conversion chip is integrated inside the first integrated circuit. Specifically,
Way 3: the transmitting device encapsulates the high-definition video data into a UDP data packet by the FPGA chip integrated in the transmitting device based on the UDP. More specifically,
the transmitting device adds a UDP data packet header and a UDP data packet tail to the high-definition video data via the FPGA chip integrated in the transmitting device. The UDP data packet header or the UDP data packet tail may include a destination address, a source address, a port number, a flag bit, and other control information.
Way 4: the transmitting device encapsulates the high-definition video data into a TCP data packet by the FPGA chip based on the TCP.
The transmitting device adds a TCP data packet header and a TCP data packet tail to the high-definition video data by the FPGA chip integrated in the transmitting device. The TCP data packet header or the TCP data packet tail may include a destination address, a source address, a port number, a flag bit, and other control information.
Way 5: the transmitting device encapsulates the high-definition video data into a custom data packet by the FPGA chip based on the custom communication protocol. More specifically,
Way 6: the transmitting device encapsulates the high-definition video data into a UDP data packet by the ASIC chip integrated in the transmitting device based on the UDP.
Way 7: the transmitting device encapsulates the high-definition video data into a TCP data packet by the ASIC chip based on the TCP.
Way 8: the transmitting device encapsulates the high-definition video data into a custom data packet by the ASIC chip based on the custom communication protocol.
Way 9: the transmitting device includes a first integrated circuit;
The communication protocol includes the UDP, the TCP, or a second custom communication protocol.
The distortionless coding algorithm may include, but not limited to:
The custom arithmetic coding algorithm is taken as an example. The first integrated circuit can compress redundant data in the high-definition video data based on the custom arithmetic coding algorithm to obtain the first data, and encapsulates the first data through the communication protocol to obtain a data packet.
For example, when the high-definition video data is 0 that occupies 6 bytes, that is, 000000000000, the first integrated circuit can obtain the first data (0600) that only needs to occupy 2 bytes after compressing redundant data in the high-definition video data based on the custom arithmetic coding algorithm, so that compression of the redundant data in the high-definition video data is realized.
At block 103, the transmitting device transmits the data packet to a first communication module.
According to an embodiment of the disclosure, the transmission rate of the first communication module is not less than a first threshold, and the first threshold may include, but not limited to 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
It should be noted that the transmitting device transmits the data packet to the first communication module in, but not limited to, the following methods.
Method 1:
The first communication module includes an electrical module. The electrical module includes a physical layer (PHY) chip and a RJ-45 interface.
The transmitting device transmits the data packet to the PHY chip (an Ethernet PHY data transceiver) via a MAC unit based on a third interface protocol. The PHY chip is configured to output the data packet to the RJ-45 interface, and the RJ-45 interface is configured to transmit the data packet. The third interface protocol includes a XFI protocol, a media independent interface (MII) protocol, a gigabit media independent interface (GMII) protocol, a reduced gigabit media independent interface (RGMII) protocol, a serial gigabit media independent interface (SGMII) protocol, a Serdes protocol, a XAUI protocol or a RXAUI protocol. The data packet includes a UDP data packet, a TCP data packet, or a custom data packet.
Method 2:
The first communication module includes an optical module.
The transmitting device transmits the data packet to the optical module via the MAC unit based on the third interface protocol. The optical module is configured to convert the data packet into an optical signal and transmit the optical signal based on an optical fiber. The optical module may include, but not limited to, a single-fiber bidirectional optical module (specifically including a single-mode optical module for long-distance transmission and a multi-mode optical module for short-distance transmission).
It should be noted that when the first communication module is an electrical module,
The transmitting device modulates the data packet by the PHY chip, then outputs the data packet to the RJ-45 interface, and transmits the data packet to a receiving device via the RJ-45 interface; or,
The data packet includes a UDP data packet, a TCP data packet, or a custom data packet.
It should be noted that when the first communication module is an optical module,
The transmitting device converts the data packet into an optical signal by the optical module and transmits the optical signal to the receiving device; or,
The data packet includes a UDP data packet, a TCP data packet, or a custom data packet.
It should be noted that when the receiving device includes a first receiving device and a second receiving device, and the data packet includes a UDP data packet or a TCP data packet,
The transmitting device modulates the UDP data packet by the PHY chip, then outputs the data packet to the RJ-45 interface, and transmits the data packet to a switch via the RJ-45 interface, and the switch is configured to forward the UDP data packet to the first receiving device and the second receiving device respectively; or,
The transmitting device modulates the TCP data packet by the PHY chip, then outputs the data packet to the RJ-45 interface, and transmits the data packet to a switch via the RJ-45 interface, and the switch is configured to forward the TCP data packet to the first receiving device and the second receiving device respectively.
It should be noted that when the receiving device includes a first receiving device and a second receiving device, and the data packet includes a UDP data packet or a TCP data packet,
The transmitting device converts the UDP data packet or the TCP data packet into an optical signal by the optical module and transmits the optical signal to the switch, and the switch is configured to forward the optical signal to the first receiving device and the second receiving device.
At block 501, a data packet is obtained by a receiving device by a second communication module.
According to an embodiment of the disclosure, the transmission rate of the second communication module is not less than a second threshold, and the second threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
It should be noted that the data packet is obtained by the receiving device by the second communication module in, but not limited to, the following methods.
Method 1: when the second communication module includes an electrical module, the electrical module includes a PHY chip and a RJ-45 interface.
The receiving module obtains, via the RJ-45 interface integrated in the receiving device, a data packet transmitted by the transmitting device or forwarded by the switch, and transmits the data packet to the PHY chip (an Ethernet PHY data transceiver). Specifically,
Method 2:
It should be noted that the receiving device may output the data packet to a second integrated circuit by the second communication module.
At block 502, the data packet is processed by the receiving device to obtain high-definition video data.
According to an embodiment of the disclosure, the data packet is processed by the receiving device to obtain high-definition video data, which may include, but not limited to, the following methods.
Method 1:
Method 2:
When the second integrated circuit is a FPGA chip,
Method 3: when the receiving device includes a second integrated circuit, and the second integrated circuit is a FPGA chip,
Method 4: when the receiving device includes a second integrated circuit, and the second integrated circuit is a FPGA chip, the receiving device decapsulates the TCP data packet based on the TCP by the FPGA chip to obtain high-definition video data. Specifically,
Method 5: when the receiving device includes a second integrated circuit, and the second integrated circuit is a FPGA chip, the receiving device decapsulates a custom data packet based on the custom communication protocol by the FPGA chip to obtain high-definition video data. Specifically,
Method 6: when the receiving device includes a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the UDP data packet based on the UDP communication protocol by the ASIC chip integrated in the receiving device to obtain high-definition video data.
Method 7: when the receiving device includes a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the TCP data packet based on the TCP communication protocol by the ASIC chip to obtain high-definition video data.
Method 8: when the receiving device includes a second integrated circuit, and the second integrated circuit is an ASIC chip, the receiving device decapsulates the custom data packet based on the custom communication protocol by the ASIC chip to obtain high-definition video data.
Method 9: the receiving device includes a second integrated circuit. When the second integrated circuit is a FPGA chip,
The communication protocol includes the UDP communication protocol, the TCP, or the custom communication protocol.
The distortionless decoding algorithm includes a run-length decoding algorithm, a Huffman decoding algorithm, a constant block decoding algorithm for binary images, a quadtree decoding algorithm, a wavelet transform decoding algorithm or a custom arithmetic decoding algorithm.
It should be noted that the receiving device may perform interpolation on the first data based on the custom arithmetic decoding algorithm and recover the high-definition video data.
It should be noted that the receiving device processes the data packet via the second integrated circuit, and may further execute the following after obtaining the high-definition video data.
The receiving device outputs the high-definition video data to a display device through a fifth interface protocol. The fifth interface protocol includes the HDMI protocol, the DVI protocol, the Type-C protocol, the DP protocol, the USB protocol, the MIPI protocol, or the VGA protocol.
The disclosure provides a transmitting device, as shown in
The input interface 601 is configured to receive high-definition video data with different color space formats; and
The first communication temporal interface includes a LVDS interface, a TTL interface, a MIPI, or a custom interface.
It should be noted that the LVDS interface or the TTL interface may respectively be interfaces configured to separately transmit audios and videos in the high-definition video data. The custom interface is an interface configured to realize hybrid transmission of the audios and videos in the high-definition video data.
The first integrated circuit 602 may be configured to process the high-definition video data into a data packet based on a communication protocol;
It should be noted that the high-definition video data with different color space formats in the embodiments of the disclosure is source data or raw data.
It should be noted that the high-definition video data with different color space formats may include, but not limited to, multimedia data such as characters, data, sounds, graphs, images or videos (such as 1080P, 4K or 8K high-definition videos with a frame rate of 30 FPS, 60 FPS, 100 FPS or 120 FPS). The high-definition video data may further include, but not limited to, the following characteristic: high dynamic range imaging (HDR). Different color space formats may be YUV of 4:2:2, YUV of 4:2:0, YUV of 4:4:4, or RGB of 8 bit depth.
It should be noted that the input interface 101 may include, but not limited to:
The protocol includes a UDP, a TCP, or a custom communication protocol. The first integrated circuit 602 may include, but not limited to, a FPGA chip or an ASIC chip.
The first integrated circuit 602 is specifically configured to:
It should be noted that the transmission rate of the first communication module 603 is not less than a first threshold.
It should be noted that the first integrated circuit 602 is also specifically configured to:
The distortionless coding algorithm includes:
The custom arithmetic coding algorithm is taken as an example. The first integrated circuit 602 can compress redundant data in the high-definition video data based on the custom arithmetic coding algorithm to obtain the first data, and encapsulates the first data through a communication protocol to obtain a data packet.
For example, when the high-definition video data is 0 that occupies 6 bytes, that is, 000000000000, the first integrated circuit 602 can obtain the first data (0600) that only needs to occupy 2 bytes after compressing redundant data in the high-definition video data based on the custom arithmetic coding algorithm, so that compression of the redundant data in the high-definition video data is realized. The first communication module 603 may include, but not limited to, an electrical module or an optical module. The electrical module includes a PHY chip and an RJ-45 interface. The transmission rate of the optical module is not less than the first threshold, and the transmission rate of the electrical module is not less than the first threshold. The first threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
When the first communication module 603 is an electrical module, the transmission rate of the electrical module is not less than the first threshold. The electrical module is configured to:
The optical module is configured to:
The second communication temporal interface includes a XFI, a GMII, a SMII, a RGMII, a XGMII, a Serdes interface, a XAUI or a RXAUI. The data packet includes a UDP data packet, a TCP data packet, or a custom data packet.
The transmitting device 60 may also be configured to:
It should be understood that the transmitting device 60 is only one example according to the embodiments of the disclosure. The transmitting device 60 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that an embodiment for functional parts included in the transmitting device 60 of
The disclosure provides another transmitting device, as shown in
It should be noted that the first integrated circuit 702 is also specifically configured to:
The distortionless coding algorithm includes:
The first communication module 703 is configured to transmit the data packet.
It should be understood that the transmitting device 70 is only one example according to the embodiments of the disclosure. The transmitting device 70 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the transmitting device 70 of
The disclosure provides another transmitting device, as shown in
The input interface 801 is configured to obtain the high-definition video data;
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the transmitting device 80 of
The disclosure provides another transmitting device, as shown in
The input interface 901 is configured to obtain high-definition video data with different color space formats;
It should be noted that the high-definition video data may include, but not limited to, sensation multimedia data such as characters, data, sounds, graphs, images or videos (such as 1080P, 4K or 8K high-definition videos with a frame rate of 30 FPS, 60 FPS, 100 FPS or 120 FPS). The high-definition video data may further include, but not limited to, the following characteristic: high dynamic range imaging (HDR). Data formats may be YUV of 4:2:2, YUV of 4:2:0, or RGB of 8 bit depth.
The communication protocol includes a UDP communication protocol, a TCP communication protocol, or a custom communication protocol.
It should be noted that the input interface 901 may include, but not limited to:
It should be noted that the first integrated circuit 902 may include, but not limited to a FPGA chip or an ASIC chip.
The first integrated circuit 902 is specifically configured to:
It should be noted that the first integrated circuit 902 is also specifically configured to:
The first communication module 903 may include, but not limited to, an electrical module or an optical module. The electrical module includes a PHY chip and a RJ-45 interface. The transmission rate of the optical module is not less than the first threshold, and the transmission rate of the electrical module is not less than the first threshold. The first threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps, or 25 Gbps.
The transmitting device 90 may also be configured to:
It should be understood that the transmitting device 90 is only one example according to the embodiments of the disclosure. The transmitting device 80 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the transmitting device 90 of
The disclosure provides a receiving device, as shown in
The second communication module 1001 may be configured to obtain the data packet from the transmitting device, or obtain the data packet from the switch;
The conversion chip is configured to output the high-definition video data to the output interface 1003 via a third communication temporal interface of the conversion chip. The third communication temporal interface may include, but not limited to, a HDMI, a DVI, a Type-C interface, a DP interface, a USB interface, a VGA interface, or a MIPI.
When the second communication module 1001 includes an electrical module, the electrical module includes a PHY chip and a RJ-45 interface.
The electrical module may be configured to:
receive the data packet transmitted by the transmitting device via the RJ-45 interface and output the data packet to the second integrated circuit 1002 by the PHY chip and a fourth communication temporal interface of a MAC unit in the second integrated circuit 1002. The fourth communication temporal interface includes a XFI, a GMII, a SMII, a RGMII, a XGMII, a Serdes interface, a XAUI, or a RXAUI; or,
The optical module may be configured to:
The data packet includes a UDP data packet, a TCP data packet, or a custom data packet. The second integrated circuit 1002 is specifically configured to:
The second integrated circuit 1002 is also configured to:
The distortionless decoding algorithm includes:
The second integrated circuit 1002 may be specifically configured to perform interpolation on the first data based on the custom arithmetic decoding algorithm and recover the high-definition video data.
The output interface 1003 may be configured to output the high-definition video data to an output device (such as a display device) connected to the receiving device 100.
It should be noted that the second communication module 1001 may include, but not limited to, an electrical module or an optical module. The transmission rate of the optical module is not less than the second threshold, and the transmission rate of the electrical module is not less than the second threshold. The second threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps or 25 Gbps.
It should be understood that the receiving device 100 is only one example according to the embodiments of the disclosure. The receiving device 100 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the receiving device 100 of
The disclosure provides another receiving device, as shown in
The receiving device 110 may include, but not limited to, a second communication module 1101, a second integrated circuit 1102 and an output interface 1103, and may further include a conversion chip. The conversion chip is integrated in the second integrated circuit 1102.
The second communication module 1101 may be configured to obtain a data packet from a transmitting device, or obtain a data packet from a switch;
The output interface 1103 may be configured to output the high-definition video data to a display device (such as a display).
It should be understood that the receiving device 110 is only one example according to the embodiments of the disclosure. The receiving device 100 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the receiving device 110 of
The present application provides another receiving device, as shown in
The receiving device 120 may include, but not limited to, a second communication module 1201, a second integrated circuit 1202 and an output interface 1203, and may further include a conversion chip. The second communication module 1201 and the conversion chip are independently integrated in the second integrated circuit 1202.
The second communication module 1201 may be configured to obtain a data packet from the transmitting device, or obtain a data packet from the switch;
It should be noted that the second integrated circuit 1202 may include, but not limited to, a FPGA chip or an ASIC chip.
It should be noted that the second communication module 1201 may include, but not limited to, an electrical module or an optical module. The transmission rate of the optical module is not less than the second threshold, and the transmission rate of the electrical module is not less than the second threshold. The second threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps or 25 Gbps.
The disclosure provides another receiving device, as shown in
The receiving device 130 may include, but not limited to, a second communication module 1301, a second integrated circuit 1302 and an output interface 1303. The second communication module 1301, the second integrated circuit 1302 and the output interface 1303 are sequentially connected.
The second communication module 1301 may be configured to obtain a data packet from a transmitting device, or obtain a data packet from a switchboard;
The second integrated circuit 1302 may be configured to process the data packet based on a communication protocol to obtain the high-definition video data.
The output interface 1303 may be configured to output the high-definition video data to an output device (such as a display device).
The second integrated circuit 1302 is specifically configured to:
The second integrated circuit 1302 is also specifically configured to:
The distortionless decoding algorithm includes:
The communication protocol includes a UDP, a TCP, or a custom communication protocol.
It should be noted that the output interface 1303 may include, but not limited to:
It should be noted that the second integrated circuit 1302 may include, but not limited to a FPGA chip or an ASIC chip.
It should be noted that the transmission rate of the second communication module 1301 is not less than a second threshold.
The second communication module 1301 may include, but not limited to, an electrical module or an optical module. The transmission rate of the optical module is not less than the second threshold, and the transmission rate of the electrical module is not less than the second threshold. The second threshold may include, but not limited to, 1 Gbps, 2.5 Gbps, 5 Gbps, 10 Gbps or 25 Gbps.
It should be understood that the receiving device 110 is only one example according to the embodiments of the disclosure. The receiving device 110 may have more or fewer parts than indicated, may combine two or more parts, or may have different configuration implementations of parts.
It can be understood that embodiments and undefined definitions or illustrations for functional parts included in the receiving device 130 of
Those ordinary skilled in the art may realize that the modules and algorithm steps of each example described in combination with the implementations of the disclosure can be performed by electronic hardware, computer software, or a combination thereof. In order to clearly explain the interchangeability of hardware and software, the composition and steps of each example have been described generally in terms of functions in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the disclosure.
Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the devices and modules described above can refer to the corresponding processes in the foregoing implementations of method, and are not repeated here.
In the several implementations provided in the disclosure, it should be understood that the disclosed equipment, device, and method may be implemented in other ways. For example, to describe the composition and steps of each example. Whether these functions are executed in hardware or software depends on the specific application of the technical solution and design constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.
The implementations of device and equipment described above are only schematic. For example, the division of the modules is only a logical function division. In actual implementation, there may be another division manner. For example, multiple modules or components may be combined or integrated into another device, or some features can be ignored or not be implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, equipment, devices or modules, and may also be electrical, mechanical or other forms of connection.
The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the objects of the solutions in the implementations of the disclosure.
In addition, each functional module in each implementation of the disclosure may be integrated into one processing module, or each module may exist separately physically, or two or more modules may be integrated into one module. The above integrated modules may be implemented in the form of hardware or software functional modules.
When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the disclosure essentially or a part that contributes to the existing technology, or all or part of the technical solution may be embodied in the form of a software product. The computer software product is stored in a storage medium which includes instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the implementations of the disclosure. The foregoing storage media include: U-disks, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks and other media that can store program codes.
The above is only a specific implementation of the disclosure, but the scope of protection of the disclosure is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the disclosure which should be covered by the protection scope of the disclosure. Therefore, the protection scope of the disclosure shall be subject to the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011432933.X | Dec 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/079016 | 3/4/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/121126 | 6/16/2022 | WO | A |
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| 20060123455 | Pai | Jun 2006 | A1 |
| 20070061840 | Walter | Mar 2007 | A1 |
| 20070061842 | Walter | Mar 2007 | A1 |
| 20070136742 | Sparrell | Jun 2007 | A1 |
| 20080025693 | Lee | Jan 2008 | A1 |
| 20080028318 | Shikuma | Jan 2008 | A1 |
| 20080109849 | Wang | May 2008 | A1 |
| 20100115557 | Billmaier | May 2010 | A1 |
| 20100251304 | Donoghue | Sep 2010 | A1 |
| 20110023081 | Mornhineway | Jan 2011 | A1 |
| 20110173665 | Shim | Jul 2011 | A1 |
| 20110320482 | Barbieri | Dec 2011 | A1 |
| 20120074863 | Shimomura | Mar 2012 | A1 |
| 20120151529 | Andersson | Jun 2012 | A1 |
| 20120159551 | Walter | Jun 2012 | A1 |
| 20130326560 | Wang | Dec 2013 | A1 |
| 20150020088 | Velasco | Jan 2015 | A1 |
| 20160127771 | Pasqualino | May 2016 | A1 |
| 20190132148 | Kambhatla | May 2019 | A1 |
| 20210099773 | Bouazizi | Apr 2021 | A1 |
| 20220109908 | Chan | Apr 2022 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230102364 A1 | Mar 2023 | US |
