BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a prior art traveling wave amplifier.
FIG. 2 is a schematic of a prior art Cascode traveling wave amplifier.
FIG. 3 is a schematic of the present invention.
FIG. 4 is a schematic of the present invention to illustrate gain analysis.
FIG. 5 is a schematic of the present invention to illustrate feedback analysis.
FIG. 6 is a graphical representation of the gain response and feedback response of the present invention.
FIG. 7 is a schematic of an alternate embodiment of the present invention.
DETAILED DESCRIPTION
The prior art traveling wave amplifiers and Cascode traveling wave amplifiers are illustrated schematically in FIGS. 1 and 2. As explained in the Background of the Invention section above, these configurations suffer from defects that are solved by the present invention.
Referring to FIG. 3, the amplifier circuit is shown to include a plurality of semiconductor amplifier devices (1) each having an input electrode or gate (g) and output electrode or drain (d), a plurality of coupled transmission line pairs (2), and input and output termination networks (3) and (4). In the preferred embodiment, illustrated in FIG. 4, there are 2 FET devices, (10), (12), and a coupled transmission line pair (14) connected between the FET gate terminals (11) and drain terminals (13), in keeping with the object of wide bandwidth with low device count. In operation, a signal is fed to the input electrode of (10), and subsequently to the input electrode of the next semiconductor, (12), through the gate-to-gate transmission line (17), (18) which provides the correct time delay to cause cancellation of reflections from the device input electrodes, and finally into the input termination network (19) providing for a low reflection at the amplifier input terminal. The output electrodes of the semiconductor devices are likewise connected through the drain-to-drain transmission line (16), (20) with a time delay designed to provide both-reflection and cancellation from the FET output electrodes, and signal summation of the amplified FET outputs. The gate-to-gate transmission line (17), (18) is designed to be physically in close proximity to the drain-to-drain transmission line (16), (20) to allow some of the amplified signal present on the drain-to-drain line to couple back to the gate-to-gate line. The amplitude of feedback signal is determined by the physical separation of the drain transmission lines from the gate transmission lines. The phase of the feedback signal is determined by the length of the line pair. For the purpose of computing the precise effect of the coupling by computer modeling, the coupled transmission lines can be described by the so-called even-mode and odd-mode impedances, (Z0e, Z0o), and the phase length at a specified frequency as shown in FIG. 5. The graph in FIG. 6 shows a computer simulation of a computer-optimized DRF amplifier made with commercially available FET devices. This circuit has been computer-optimized for flat gain from DC to 40 GHz. Referring to the circuit of FIG. 5, the amplitude and phase of the feedback signal can be analyzed by “breaking the loop” at the input and thereby computing the signal returned to the input by the amplifier network. This is also shown in the graph in FIG. 6. The amplitude of the feedback signal is shown by the trace labeled (50), and the phase of the feedback signal is shown by the trace labeled (52). It is shown in this plot that the amplitude increases towards the high frequency end of the band, and the phase tends toward 0°. This in-phase feedback effectively enlarges the input signal as the amplifier gain is rolling off, resulting in enhanced bandwidth.
FIG. 7 illustrates one alternative embodiment of the present invention. In this embodiment, a plurality of FET amplifiers (101), (102), (103) are utilized. One skilled in the art may use this technique with the variation of using coupled-inductor models (105) in place of the coupled-line pairs. This alternate embodiment is the same technique with a different, and less accurate, method of computing the terminal parameters of the gate-to-gate and drain-to-drain coupling networks using self and mutual inductances as shown in FIG. 7.
One skilled in the art will recognize that the foregoing merely represents embodiments of the present invention. Many obvious modifications may be made thereto without departing from the spirit or scope of the present invention as set forth in the appended claims.
Patent Application
20080074191
