Patent Application
20090219087
This invention relates to travelling wave amplifiers.
Travelling wave amplifiers comprise a succession of amplifying devices, each having an input and an output, connected between two inductor chains. Each inductor chain comprises a succession of inductances connected in series with one another.
An input capacitance is associated with the input of each of the amplifying devices and a respective output capacitance is associated with the output of each of the amplifying devices.
The inputs of the amplifying devices are coupled to one inductor chain at the junctions between inductors, and the outputs of the amplifying devices are coupled to the other inductor chain, again at the junctions between inductors. An input transmission line is defined by the first inductor chain and the input capacitances associated with the amplifying devices, and an output transmission line is defined by the second inductor chain and the output capacitances associated with the amplifying devices.
At each frequency in the operating frequency range of the amplifier, for each pair of successive amplifying devices, the phase delays for electromagnetic energy propagating along the input transmission line and along the output transmission line are substantially equal. A wave propagates along each transmission line, and for the correct operation of the amplifier, these waves need to propagate at the same speed.
The concept of a travelling wave (or distributed) amplifier is well known and this amplifier configuration has been used to provide amplification of microwave signals over a broad frequency range, using Field Effect Transistors (FETs) as the amplifying devices. This offers the possibility of integrating the travelling wave amplifier, together with other RF circuitry, onto a single semiconductor substrate.
Ideally, an amplifier is provided with matched input and output impedances. The input and output impedances of the travelling wave amplifier described above is dependent on the input and output capacitance of the individual amplifying devices. In the case of FETs, the input and output capacitances are not easily controlled, and typically the FET design will not result in the travelling wave amplifier having matched input and output impedances. The drain-source (output) capacitance of a FET is generally less than the gate-source (input) capacitance.
For given input and output characteristics of the amplifiers, the inductances in the transmission lines are selected to achieve the required equal wave propagation speeds, and this leaves no scope for also obtaining input and output impedance matching.
The input and output capacitances of the individual amplifiers can be equalised, by introducing additional capacitive elements, but this introduces additional complexity and degrades performance.
There is therefore a need to provide input and output impedance matching for a travelling wave amplifier, whilst leaving design freedom for the individual amplifying devices and maintaining equal propagation speeds in the transmission lines, and with minimum additional complexity to the circuit.
According to the invention, there is provided a travelling wave amplifier comprising:
a first transmission line associated with an input to the amplifier, and comprising a first plurality of inductive elements in series;
a second transmission line associated with an output of the amplifier, and comprising a second plurality of inductive elements in series; and
a plurality of amplifier devices connected between the first and second transmission lines,
wherein at least one of the first and second transmission lines further comprises a plurality of delay elements, each delay element being provided in series between a respective pair of inductive elements.
The delay elements provided in one of the transmission lines enable the pulse propagation speeds in the two transmission lines to be matched while leaving freedom in the selection of impedance values to provide input and output impedance matching of the amplifier. In this way, even when the individual amplifier devices have unequal input and output impedances, the amplifier can be configured to provide matched input and output impedances as well as matched propagation speeds.
Each amplifier device preferably comprises a field effect transistor arrangement, having a gate connected to the first transmission line and a drain connected to the second transmission line. This enables IC integration of the amplifier components. Each field effect transistor arrangement may comprise one or more field effect transistors connected in series between the second transmission line and a common terminal.
The second transmission line, associated with the output, preferably comprises the plurality of delay elements. In particular, the amplifier device outputs connect to the second transmission line, and the lower output capacitance of the FETs gives rise to higher propagation speed in the second transmission line. This higher speed is compensated by the delay elements.
Each delay element may comprise an integrated circuit delay line, integrated into an integrated circuit of the amplifier devices. The delay lines can easily be incorporated into the IC design in known manner, with little or no additional manufacturing complexity or reduction in yield.
Each delay element may have an impedance selected in dependence on the output capacitance of each amplifier device and the inductance of the inductor elements in the second transmission line. The impedance value is selected to provide the input and output impedance matching. However, each delay element has a time delay selected to ensure equal propagation speeds through the first and second transmission lines.
The input 16 is preferably provided to one end of the first transmission line, and the other end of the first transmission line is connected to a common potential through a first terminating resistance. The output is preferably provided from one end of the second transmission line, and the other end of the second transmission line is connected to a common potential through a second terminating resistance. This defines a known configuration.
The impedance of each delay element is preferably equal in magnitude to the resistance of the second terminating resistance.
An example of the invention will now be described in detail with reference to the accompanying drawings, in which:
The first transmission line 12 is associated with an input 16 to the amplifier, and comprises a first plurality of inductive elements in series. The inductive elements between any pair of cascode cells have inductance Lg, whereas the first and last inductive elements have inductance ½ Lg, as shown.
The second transmission line 14 is associated with an output 18 of the amplifier, and comprises a second plurality of inductive elements in series. The inductive elements between any pair of cascode cells have inductance Ld, whereas the first and last inductive elements have inductance ½ Ld, as shown.
The input 16 is provided to one (input) end of the first transmission line 12, and the other (output) end of the first transmission line is connected to a common potential through a first terminating resistance Rg. The output 18 is provided from the output end of the second transmission line 14, and the input end of the second transmission line 14 is connected to a common potential through a second terminating resistance Rd. The terminating resistances prevent reflections along the transmission lines and the common potential is typically ground.
Each amplifier device 10 is shown in this example as two field effect transistors in series, defining a cascode configuration. The gate of one is connected to the first transmission line 12 and the drain of the other is connected to the second transmission line 14.
Before describing the invention, a simplified analysis of the circuit of
In
Two waves propagate through the transmission lines, and these are shown as “Drain Wave” for the output transmission line 14 and “Gate Wave” for the input transmission line 12.
A voltage impulse is applied at the input 16, and this propagates along the transmission line 12, which comprises the inductors Lg and the input capacitances Cin, towards the terminating resistor Rg.
Each time this impulse reaches one of the transistor inputs of the amplifier device 10, it launches a current pulse to the drain of the output transistor of the amplifier device 10. This impulse propagates along the output transmission line 14, which comprises the inductors Ld, and the output capacitances Cout, towards the output 18.
These two waves must have the same velocity for correct signal amplification.
There are two conflicting desirable circuit parameters in the circuit of
The input and output impedances are given by:
(Lg/Cin)−0.5=Rg=Rsource
(Ld/Cout)−0.5=Rd=Rload
For impedance matching, Rg=Rd is required. Hence:
Lg/Cin=Ld/Cout (1)
The propagation times along the two transmission lines are given by:
Tg=(Lg×Cin)−0.5
Td=(Ld×Cout)−0.5
For velocity matching, Tg=Td is required. Hence:
Lg×Cin=Ld×Cout (2)
The two conditions above are contradictory, and can only be satisfied if Cin=Cout and Ld=Lg. However, in practical implementations of the amplifiers 10, Cin is different to Cout and a tradeoff is necessary. Typically, Cin is higher than Cout.
The impedance matching condition (1) in this case gives rise to impedance values Ld<Lg. This in turn gives rise to the relation Ld*Cout<Lg*Cin.
Thus, setting the circuit of
In accordance with the invention, at least one of the first and second transmission lines further comprises a plurality of delay elements, each delay element being provided in series between a respective pair of inductive elements. In the case described above, where the impedance matching gives rise to a greater velocity drain wave, the output transmission line 14 through which the drain wave propagates is provided with the plurality of delay elements.
This arrangement is shown in
The delay elements 50 enable the pulse propagation speeds in the two transmission lines to be matched while leaving freedom in the selection of impedance value to provide input and output impedance matching of the amplifier. In this way, even when the individual amplifier devices 10 have unequal input and output impedances, the amplifier can be configured to provide matched input and output impedance as well as matched propagation speeds.
The delay line impedance is matched to the terminating resistor Rd and is selected to satisfy the impedance matching condition:
Zd=Rd=(Ld/Cout)−0.5 (3)
Each delay element impedance is thus selected in dependence on the output capacitance of each amplifier device 10 and the inductance of the inductor elements in the second transmission line.
The delay line time delay is selected to provide the matched propagation speed:
Td=(Lg*Cin)−0.5−(Ld*Cout)−0.5 (4)
For a given delay line design with desired impedance, this time delay is varied by selecting the length of the delay line (generally the time delay varies with the square of the delay line length).
Each delay element may comprise an integrated circuit delay line, integrated into an integrated circuit of the amplifier devices. The delay lines can easily be incorporated into the IC design in known manner, with little or no additional manufacturing complexity or reduction in yield.
In the example above, only the output transmission line is provided with delay elements. However, when the operation frequency is very high, for example around 150 GHz, the required dimensions of the inductors become less than the width of the amplifier circuit 10.
The required effective time delay is given by:
Td1−Td2=(Lg*Cin)−0.5−(Ld*Cout)−0.5 (5)
The values of Td1 and Td2 can thus be selected accordingly.
The invention can be applied to all known uses of travelling wave amplifier, essentially when wide band amplification is required. Travelling wave amplifiers are used in broadcast transmitters and receivers, cable networks, space communications and many other applications.
The invention can be implemented in an MMIC (monolithic microwave IC), and is suitable for electrical signal processing at high frequencies, for example corresponding to the high bit rates used in optical communications systems, for example 10 GB/s-40 GB/s In the example above, the amplifier devices are shown as twin TFT cascode cells. However, a single TFT may function as the amplifying device.
The invention is also applicable to vacuum tube travelling wave amplifiers, used for very high power amplifications. Other designs for the amplifying device are also possible.
Only two detailed examples have been given above, but it will be apparent to those skilled in the art that other circuit configurations for travelling wave amplifiers are possible. The invention is applicable to any such circuit configuration in which two transmission lines are provided. The use of delay elements in accordance with the invention enables the propagation speeds to be matched using the delay elements, so that design freedom is kept for other circuit parameters, for example to provide impedance matching. This design freedom may, however, be used for other purposes, and the invention is not limited to an amplifier with matched input and output impedance.
The invention particularly enables an improved gain across the required bandwidth with improved impedance matching. The invention can also improve the stability factor of the amplifier.
Various other modifications will be apparent to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 04300215.3 | Apr 2004 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB2005/051264 | 4/19/2005 | WO | 00 | 10/18/2006 |
