Patent Application
20050246614
The present invention relates generally to trellis-based detection techniques as exemplified by the solution known as the Viterbi Algorithm (VA).
In typical trellis-based detection arrangements, when a 16-state intersymbol interference (ISI) channel is combined with a single bit parity code, the number of states in the combined trellis is 32. The minimum-distance error-events in the combined trellis consist of either a single even parity error-event (i.e., +−, +−+, +0+, . . . ) or two odd-parity error events (i.e., +, +−+, +0+0+, . . . ). Since the two odd parity error-events do not have to be close to each other, the path memory for the 32-state trellis must be longer than the parity-code block length, which is typically very large.
For example, if the parity-code block length for a channel is 82 bits, a path-memory length of L=97 is currently required. A standard 32-state shift register exchange algorithm contains 32·(L-1) flip-flops. If, e.g. the number of flip-flops is 3072, this means that the path memory alone is more than 17 times larger than the path memory for typical read channel with 16-states and L=12.
An example of a parity-sensitive Viterbi detector is disclosed and discussed in detail in U.S. Pat. No. 6,662,338, which is incorporated by reference.
In view of the foregoing, the need exists for trellis detector arrangements of reduced complexity wherein reduction in complexity does not adversely affect the performance level.
According to an embodiment of the present invention, a two-stage path memory arrangement is used in order to reduce complexity. The first stage is a 32-state shift register exchange with a short path memory length λ=28 and the second stage is a 2-state shift register exchange with a longer path memory length of Λ=L−λ=69. In direct comparison with the example made above, the number of flip-flops is reduced to 32·λ+2·(Λ−1)=1032, which is only five times larger than the path memory of a typical non-parity-sensitive Viterbi detector with 16 states and L=12.
The invention will now be described, by way of example only, with reference to the annexed drawings.
FIG., 12 is a block diagram of a read channel that incorporates the Viterbi detector of
By way of premise, a brief overview is provided of a standard 32-state path memory, with path memory length L, for single-bit parity.
The path memory stores the survivor path leading to each of the 32 states at time k.
Let Sk=[Pk, xk-3, xk-2, xk-1, xk] denote one of the states at time k, where Pk denotes even or odd parity. A decimal value for the state is obtained from the binary representation, Sk=16·Pk+8·xk-3+4·xk-2+2·xk-1+xk.
There are two paths leading to this state coming from states [Pk-1, 0, xk-3, xk-2, xk-1] and [Pk-1, 1, xk-3, xk-2, xk-1] at time k-1, with Pk-1=Pk⊕xk. The path with the minimum metric is selected by sending the selected binary value for xk-4 to the input of the path memory.
The new survivor path for state [Pk, xk-3, xk-2, xk-1, xk] is obtained by shifting the old survivor path for state [Pk-1, xk-4, xk-3, xk-2, xk-1] to the right by one and shifting in xk-4. The output of the 32-state shift register exchange unit is {x0k-L-3, x1k-L-3, x2k-L-3, . . . , x31k-L-3}, where the superscript indicates the state at time k. The final decision at the output of the sequence detector is selected from the survivor path leading to the best state at time k, which is obtained by comparing all 32 state metrics at time k. The output of the sequence detector is xAkk-L-3, where Ak denotes the best state at time k.
For one of the two subtrellises shown in
In the block diagram of
The kind of formal representation adopted in the captioned figures is well known to those of skill in the art, thus making it unnecessary to provide a more detailed description herein.
Also, it will be appreciated that such logical representations lend themselves to being implemented both in the form of dedicated processors and by resorting to general-purpose processors such as a DSP programmed by means of a suitable computer software product.
Since each block in
In the reduced complexity algorithm according to an embodiment of the invention, the first stage involves a standard 32-state shift register exchange with length λ. However, the first stage is modified to output the state at time k-λ on the survivor path for the best state at time k, SAkk-λ. This requires keeping track of the parity for the state at time k-λ on each of the 32 survivor paths.
This is done using a shift-register exchange method that initializes the parity values near the beginning of the sector. The parity bit at the end of register S should be initialized to the parity state of S.
Since the survivor paths are initialized to all zeros at the beginning of the sector at an arbitrary time k=t0 relative to the data, the parity of the state at time k-λ at the end of the survivor path leading to state j at time k should be initialized to the modulo 2 sum of the 5 bits in the state number
parityvec[j]=((j>>4)&1){circumflex over ( )}((j>>3)&1){circumflex over ( )}((j>>2) &1){circumflex over ( )}((j>>1)&1){circumflex over ( )}(j&1).
If time 0 corresponds to the first data bit, then due to the trellis pruning all the states in the survivor paths at time −1 must have parity 0. Therefore, at time k=λ-1, parityvec[j] should be zero for all values of j.
Since there is not infinite memory, a correct initialization is important to ensure that the parity in parityvec is the exact value that it is supposed to be.
It will be appreciated that this solution is somewhat resilient to incorrect initialization. However, under an incorrect-initialization criterion, this solution may not work properly when there is an error-event straddling the end of the address mark and the beginning of the data.
When testing the initialization, the relationship between the initialization time t0 and the data should be varied.
In current operation according to an embodiment of the invention, the first stage outputs the state at time k-λ on the survivor path for state Bk=Ak⊕16 at time k, SBkk-λ. State Bk has the same ISI state as the best state and the opposite parity state.
A diagram of the first stage of the reduced complexity path memory is shown in
Given the two states at the output of the first stage, SAkk-λ and SBkk-λ, there are three cases for consideration according to an embodiment of the invention: SBkk-λ=SAkk-λ⊕16, SBkk-λ=SAkk-λ, and none of the above.
In the first case, the survivor paths for states Ak and Bk=Ak⊕16 are parallel paths with opposite parity states and exactly the same ISI states from time k-λ to time k. As shown in
In the second case, shown in
In the third case, a new error-event in stage 2 of the path memory (event 1) becomes dominant and replaces the old error-event (event 2), as shown in
Since event 1 has not reached its full distance, this can cause diminished performance unless the path-memory length of stage 1 is long enough too avoid an error-event starting in stage 2 (event 1) from overlapping with an error-event ending in the future (event 3).
The performance issue is eliminated when λ≦2Lmax−2, where Lmax is the maximum length of an odd parity error-event, since overlapping events are resolved in stage 1 before entering stage 2. The remaining survivor paths are shown in
The second stage of the reduced complexity algorithm consists of a 2-state shift-register exchange with path memory length Λ, shown in
As a consequence, the final decision from the path memory comes from the output of register(0).
The other register, referred to as register(1), contains the backend of an alternative survivor path. The alternative path the survivor path is for the state at time k with the same ISI state as the best state and the opposite parity state, Bk=Ak⊕16.
That is unless SBkk-λ=SAkk-λ, in which case it is an extension of an old alternative path. The connection bit for each new state indicates which of the old states is connected to the new state. The new state σ0k is connected to the old state σconnect0kk-1 and the new state σ1k is connected to the old state σconnect1kk-1.
Register(0) is updated by shifting in the old survivor path stored in register(connect0k) and inputting the most significant ISI bit in state σconnect0kk-1. The input to register(0) is the decision bit at time k-λ-4 along the survivor path leading to the best state Ak,
input0k=(msb of ISI state σconnect0kk-1)=(sconnect0kk-1>>3)&1=xAkk-λ-4.
Similarly, register(1) is updated by shifting in the old survivor path stored in register(connect1k) and inputting the most significant ISI bit in the state designated σconnect1kk-1.
At time k, there are two new states σ0k and σ1k to be connected up with the two old states σ0k-1 and σ1k-1.
In
In
In
The following is an algorithm for determining the connection bit for the new state σk[Q,e,f,g,h], given the old states σ0k-1=[P0,a0,b0,c0,d0] and σ1k-1=]P1,a1,b1,c1,d1].
The shortest connection is selected, with the state on the old best path, σ0k-1, taking preference when there is a tie.
Define a routine that returns the connect bit such that
If SBkk-λ is not equal to SAkk-λ, then set σ1k-λ=SBk-λ.
If SBkk-λ is equal to SAkk-λ, and we are out of the pruning region, then we extend the old state that is not connected to the best path, denoted by σconnect0k⊕1k-1.
Define prune_region as the region where the states will be overridden (for PR targets with 5 taps, this happens at 5 time instances every codeword).
The extended state is derived from (σconnect0k⊕1k-1) as follows:
Next, we use the connection routine to determine which of the old states is connected to σk1,
connect1k=connection(σ0k-1, σ1k-1, σ1k).
The input to register(1) is the most significant ISI bit in the old state that is connected to σ1k,
input1k=(σconnect1kk-1>>3)& 1.
Note that pruning is done at time k (i.e. at the front end of Viterbi trellis) in the same way as with the full complexity Viterbi algorithm.
After the sixth (and final) stage of the pruning, all survivor paths pass through the even-parity states at the time corresponding to the first pruning stage (which corresponds to the end of codeword), so all survivor paths are valid.
During the first five stages of pruning, Bk will not be a valid state, but this will not affect the algorithm because only states that are valid at the end of the first stage will be passed to the second stage.
On the half-rate implementation, two ITR samples are input at a time, and two bits are output at a time. Since the front end of the Viterbi algorithm operates at half rate, the ACS is modified so that two branch metrics are added to a state metric to produce a path metric, and a 6-way comparison is used to compare among four path metrics.
Regarding the reduced complexity implementation, the part of the algorithm performed at time k (i.e. at the front end of the Viterbi) is done every two bits. The part of the reduced complexity algorithm done at the boundary between the first and the second stage is also done every two bits, and the connect algorithm looks for two-step connections, four-step connections, and six-step connections (there will always be a six-step connection).
The Viterbi detector tracks r possible states S0-Sr-1 of a received bit stream, and recovers the code words that compose the bit stream, each of the code words including at least one parity bit. For example, as discussed above in conjunction with
The path-history section 100 includes r state registers 1020-102r-1, one for each possible state S0-Sr-1. Each state register 102 has n=log2r locations 0−n-1 that store the bit values for corresponding state—the most-significant-bit (MSB) location(s) 0 of each register 102 stores the parity bit(s). For example, where r=32, n=5, S0=00000, S1=00001, and S31=11111, the register 1020 stores 00000 (MSB=0 for even parity), the register 1021 stores 00001 (MSB=0 for even parity), and the register 10231 stores 11111 (MSB=1 for odd parity).
In addition, the path-history section 100 includes r stage-1 registers 1040-104r-1, one for each possible state S0-Sr-1. Each stage-1 register 104 has λ locations 0-λ-1 that store the surviving bit path for the corresponding state from sample time k-(n+λ-1) to the most recent sample time k-n. The value of λ depends on the ISI latency of the Viterbi algorithm implemented by the Viterbi detector (
Furthermore, the path-history section 100 includes z stage-2 registers 1060-106z-1, one for each possible parity state. For example, because the Viterbi algorithm discussed above in conjunction with
The path-history section 100 often contains fewer bit locations than the path-history section of conventional parity-sensitive Viterbi detectors. For example, for the same bit-stream coding scheme, the path-history section of a conventional thirty-two-state parity-sensitive Viterbi detector would include r(n+λ+Λ)=3264 bit locations, whereas the path-history section 100 includes approximately one-third fewer bit locations, i.e., r(n+λ)+zΛ=1194 bit locations. This savings of memory in the path-history section often reduces the cost and complexity of the Viterbi detector.
Still referring to
Data is shifted into the stage-1 registers 104 from the respective registers 102 via the left side of the stage-1 registers in a manner similar to that of a conventional Viterbi algorithm.
At an interface 108 between the stage-1 registers 104 and the stage-2 registers 106, the stage-interface algorithm discussed above in conjunction with
The recovered bit stream is then shifted out of the registers 106 (via the rightmost multiplexer of
The Viterbi detector 110 includes a terminal 112 for receiving the synchronized samples of a read signal (i.e., a bit stream), a terminal 114 for receiving a synchronization signal, a terminal 116 for receiving a clock signal, and a terminal 118 for providing the recovered data sequence. In one embodiment, the sync and clock signals are binary logic signals, and the data sequence is binary. As discussed below, the sync signal identifies the beginning of the data sequence, and the detector 110 uses the clock signal—which in one embodiment is the same as or is derived from the read-signal sample clock—to provide timing to the detector 110. The detector 110 also includes a recovery circuit 120 that executes the Viterbi algorithm discussed above in conjunction with
In operation, the synchronization signal transitions from one logic state to the other to indicate that the next read sample represents the first bit of the data sequence. A circuit for generating the sync signal is disclosed in U.S. Pat. No. 6,604,204, which is incorporated by reference. In response to this transition of the sync signal, the recovery circuit 120 process the next and subsequent read samples according to a trellis diagram that accounts for the parity of the data sequence. Examples of such trellis diagrams are discussed below in previously incorporated U.S. Pat. No. 6,662,338. The circuit 120 uses these samples to calculate and update the surviving-path metrics, and stores the surviving paths in the shift registers of the path-history section 100 as discussed above in conjunction with
The disk-drive system 140 also includes write and read interface adapters 164 and 166 for respectively interfacing the write and read controllers 148 and 150 to a system bus 168, which is specific to the system used. Typical system busses include ISA, PCI, S-Bus, Nu-Bus, etc. The system 140 also typically has other devices, such as a random access memory (RAM) 170 and a central processing unit (CPU) 172 coupled to the bus 168.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.
For example, although the Viterbi algorithm discussed above in conjunction with
Referring to
Furthermore, although a disk drive system 140 of
This application claims priority to U.S. Provisional Application Ser. No. 60/530,949, filed on Dec. 19, 2003, which is incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60530949 | Dec 2003 | US |
