Patent Application
20070063269
This application is an improvement of copending application Ser. No. 11/204,074, filed Aug. 15, 2005 entitled DEEP N DIFFUSION FOR TRENCH IGBT in the names of Richard Francis and Chiu Ng and assigned to the assignee of the present invention (IR-2703) which is an improvement of the devices and processes disclosed in U.S. Pat. Nos. 6,683,331 and 6,482,681.
This invention relates to trench type Insulated Gate Bipolar Transistors (IGBTs) and more specifically relates to such IGBTs with a increased short circuit capability.
IGBTs are well known and are frequently implemented with a planar cellular or stripe topology. These devices have an inherent JFET which increases the device on-resistance RDSON and, thus the forward voltage drop VCE(ON). Further, such devices have an inherent four layer parasitic thyristor structure which will latch on if the NPN transistor of the thyristor turns on.
It is known that IGBTs can be made with a trench topology which eliminates the inherent JFET of the planar device. However, trench IGBTs still have the inherent four layer structure whereby, if the inherent NPN transistor in the four layer device turns on (if the current through RB′ is sufficiently high), the device will latch on. It is also desirable to reduce the saturation current of the device without increasing the value of RB′.
It has further been found that trench IGBTs tend to be “fragile”, that is, they can fail particularly when switching an inductive load. This is sometimes termed a low safe operating area (SOA) under reverse bias. This problem again is aggravated by an increased RB.
U.S. Pat. No. 6,683,331 the disclosure of which is incorporated herein by reference, describes a trench IGBT structure and process for its manufacture, creating a non-punch through (NPT) IGBT having a reduced RB′, a reduced saturation current, a low threshold voltage VT and an enlarged SOA. More specifically, a structure is provided having a deep emitter diffusion which is very narrow (of small lateral extent) to reduce RB′. Further, a very deep P channel diffusion is employed between spaced trenches to create a very long inversion channel. Thus, when the device goes into avalanche, the path for hole current under the emitter has a reduced lateral extent, reducing RB′ and the trench is very deep (about 8 microns) so that the P region adjacent the channel can support reasonable voltage and the N− body concentration and depth can be optimized. The increased depth of the emitter along the trench controls threshold voltage since it permits the use of a very deep P+ region without the danger of its encroaching into the channel (which would increase VT). Finally, a helium implant may be employed for lifetime killing in only the P well.
Further, the device of the 6,683,331 patent may be built in float zone silicon and no epitaxial layer is needed, with a weak anode structure being employed as in copending application Ser. No. 09/565,922, filed May 5, 2000 in the names of Richard Francis and Chiu Ng now U.S. Pat. No. 6,482,681.
In the trench IGBT structure disclosed in U.S. Pat. No. 6,683,331 the current during forward conduction can be seen as a combination of MOSFET and bipolar currents. The specific on-resistance to the MOSFET current is determined by several components. In 300-1200V devices, due to the relatively high resistivity of the drift layer (typically 14-60 Ohm-cm) the major contribution of on resistance from drift region resistance and spreading resistance below the channel region.
Copending application Ser. No. 11/204,074 (IR-2703) describes a deep diffusion, or “deep enhancement” in which the spreading and drift region resistance in a trench type IGBT is reduced by the introduction of a deep diffusion layer below the base diffusion. This deep diffusion has an opposite doping concentration with respect to the P type base (or N type for an N channel device). The present invention reduces the device forward voltage drop by reducing on resistance. Further the invention provides the possibility to optimize the device to specific applications (e.g. switching frequency). Further, with the invention, in a high injection, epitaxial type trench IGBT, the irradiation dose can be increased to reduce the turn-off current and the switching time, hence reducing switching losses for the same forward drop. This is very useful in many applications, and significantly, in a low injection, depletion stop type trench IGBT, the deep enhancement of the invention will substantially reduce the device forward drop.
One of the major challenges in the design of a trench IGBT device such as those disclosed in U.S. Pat. No. 6,683,331 or application Ser. No. 11/204,074 (IR-2703) which are to be utilized in appliance and industrial motor drive applications is to guarantee a short circuit withstand capability. In specific application conditions (for instance for a short circuit fault at motor start-up) both high voltage and high current can appear across the device terminals for a few microseconds and until the control circuit can shut off the gate voltage. In such conditions the device should withstand the full bus voltage and forward current, usually at junction temperatures well above 100° C., without failing. Due to the carrier enhancement effect and increased channel width, a trench IGBT has, typically, a very high saturation current (well above 1000 A/cm2). That results in excessive power dissipation during a short circuit fault, leading to device thermal destruction.
In order to ensure high short circuit capability, special attention must also be paid to avoid device latching (loss of control of the collector current by the gate voltage). Latch-up would also result in device failure due the turn-on of the parasitic npnp Thyristor structure in the IGBT.
Several techniques, as follows, are known to improve IGBT short circuit capability, by a modification of either the cell geometry or the vertical structure of the device:
Technique (a) above causes a decrease in breakdown voltage. Techniques (b) through (g) inevitably result in the increase of conduction losses.
In accordance with the invention, the structure of trench IGBT is tailored to insure reduced saturation current and increased short circuit withstand capability yet avoiding the drawbacks outlined above. This is achieved by increasing the gate oxide thickness grown on the sidewalls and bottom of the trench cell to greater than the traditional 1000Å, and to a range of 1800Å to 2500Å, and preferably, about 2000Å. Normally, designers use the thinner gate oxide (1000Å) to improve transconductance. However, the increased thickness gate provides the best trade-off between Vce on and short circuit current. The higher resulting threshold voltage VT gives a longer withstand time.
Referring first to
The detail of manufacture of the device of
The structure of
Trenches 31 and 32 extend through N+ emitter regions 40 and 41 respectively which are very deep (2 microns to 4 microns) and have a very short lateral extension, for example 1.5 microns to 3 microns. Note that emitter regions 40 and 41 have shallow shelf contact regions 42 and 43 respectively, which have a lateral extension of about 0.2 microns to 0.5 microns. Trenches 31 and 32 extend into the deep enhancement region 100 for about 2 μm (non-critical).
A P+ contact region 50 extends into P− base 37 and between emitter regions 40 and 41. The polysilicon gates 35 and 36 are covered by a suitable insulation oxide 51 and the top surface of the device receives an aluminum or other suitable emitter contact 52. The backside of the device contains a P+ diffusion 54 which receives collector contact 53.
The use of the very deep trench (6.5 microns) and very deep P− base 37 (4 microns) permits the use of the very deep, but narrow emitter regions 40 and 41 while still leaving a sufficiently long invertible channel below the emitter regions (for example, 2 microns) to permit the P regions 37 to support a reasonable voltage and so that the N− body 26 can be optimized. Further, when the device operates in avalanche, a hole current flows from P+ region 54 and up and under the emitters 40 and 41 and through the effective resistance RB′ under the emitter regions 40 and 41. This resistance is very low to avoid the turn on of the NPN transistor 40, 37, 26, for example, and to avoid latching on the IGBT structure.
Note that the ledge regions 42, 43 of emitters 40 and 41 respectively are atop the P+ regions 50 and do not form a part of the RB′ of the device. These ledges 42, 43, however are major points for connection of the emitter regions 40 and 41 to emitter contact and permit such connection even with unavoidable mask misalignment during manufacture.
The deep enhancement 100 may have a depth of 4 μm to 10 μm (with a 6 μm deep trench) and has a concentration substantially greater than that of N− body 26. This deep enhancement 100 reduces the spreading and drift region resistance of the device, thereby to reduce the forward voltage drop of the device. Further, the region 100 can be adjusted in concentration and depth to optimize the device to a specific application. For example, switching frequency can be preferred over other parameters for a particular application. In a high injection epitaxial device, the irradiation dose can be increased to reduce turn-off current at the switching time to reduce switching losses for the same forward voltage drop. Further, in a low injection depletion stop type trench IGBT, the deep enhancement region 100 will substantially reduce the forward voltage drop.
In accordance with the invention, and to tailor the device to one having an improved short circuit capability, the gate oxide has a thickness greater than 1500Å and in the range of 1800Å to 2500Å; preferably 2000Å. This increased gate oxide thickness unexpectedly provides the best tradeoff of Vce on (forward voltage drop) and short circuit current. Thus, the higher VT provides a longer short circuit current withstand time. The N region 100 would be a P region in a P channel device with all other concentration types reversed.
FIGS. 3 to 9 show a process sequence which can be used to make the device of
The photoresist 112 is then stripped and the phosphorus implant is driven for 4 to 16 hours at 1175° C. to drive the novel deep N diffusion 100. At the same time, oxide 111 grows to about 1.2 μm and thinner oxide layer 120 grows to about 7000Å as shown in
A termination mask step is then carried out and, as shown in
Thereafter, as shown in
The cell structure is then completed as shown in U.S. Pat. No. 6,683,331 and as shown in
In accordance with the invention, the gate oxide 172 is made greater than about 1500Å thick and preferably about 2000Å and the trench spacing is about 6 μm. Preferably, the same gate oxide thickness lines the bottom of the trenches. The trench widths are about 1.5 microns.
In the process described, the cells described are two of up to many thousands in a single die, and are formed with the die in the wafer stage. The terms die and wafer may herein be used interchangeably.
The use of a gate oxide thickness greater than 1500Å produces the benefits shown in
In
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.
