Patent Application
20080044981
The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that although the terms first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted regions. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning in other words consistent with their meaning in the context of the relevant art and this specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some embodiments of the present invention will now be discussed with respect to
As further illustrated in
A photoresist pattern 106 is formed on the nitride layer 104 by using, for example, a photolithography process. The nitride layer 104 may be at least partially exposed through the photoresist pattern 106. An isolation region may be subsequently formed at the exposed portions of the nitride layer 104 through the photoresist pattern 106. In addition, a portion of the semiconductor substrate 100 covered by the photoresist pattern 106 may correspond to an active region thereof.
Referring now to
A first opening 112, exposing at least a portion of the semiconductor substrate 100, may be formed by shaping the preliminary mask pattern. The semiconductor substrate 100 may be partially exposed from a bottom face of the first opening 112. In addition, the exposed portion of the semiconductor substrate 100 through the first opening 112 may be further etched after the preliminary mask pattern is formed.
Referring now to
The edge portion of the preliminary pad oxide layer pattern 108 may be removed using, for example, a wet etching process. An etching solution used in the wet etching process may be, for example, a diluted hydrogen fluoride (HF) solution or a limulus amebocyte lysate (LAL) solution that includes ammonium fluoride (NH4F), hydrogen fluoride (HF) and water (H2O).
The wet etching process may be performed using the etching solution for about, for example, thousands of seconds to remove the edge portion of the preliminary pad oxide layer pattern 108 to about 50 Å. Thus, a mask pattern having the pad oxide layer pattern 114 and the nitride layer pattern 110 that has a line width substantially larger than that of the pad oxide layer pattern 114 may be formed.
Referring now to
The portion of the semiconductor substrate 100 exposed through the pad oxide layer pattern 114 may be removed using, for example, a wet etching process. The wet etching process may be performed using, for example, a standard cleaning 1 (SC1) solution. The SC1 solution may include ammonia (NH4OH), hydrogen peroxide (H2O2) and water (H2O). In addition, a temperature of the SC1 solution may be from about 70° C. to about 80° C.
The temperature of the SC1 solution may determine an etch rate. According to some embodiments of the present invention, an etch rate with respect to the semiconductor substrate 100 including silicon may be reduced by using the SC1 solution having a relatively high temperature of from about 70° C. to about 80° C. That is, an etch rate of the semiconductor substrate 100 may be effectively controlled by adjusting a temperature of the SC1 solution.
The sidewall 116a of the second opening 116 formed using the SC1 solution and etching the exposed portion of the semiconductor substrate 100 may have the first inclination angle substantially smaller than that of a sidewall 112a of the first opening 112. In some embodiments of the present invention, the portion of the semiconductor substrate 100 having the first inclination angle may correspond to an edge portion of the active region making contact with the isolation region that is subsequently formed. Thus, the edge portion of the isolation region making contact with the isolation region may be slightly inclined.
Referring now to
In particular, a plasma dry etching process is performed on the semiconductor substrate 100 by using the mask pattern as an etch mask to form the trench 118. In some embodiments of the present invention, the width of the trench 118 may become substantially narrow from an upper portion of the trench 118 toward a lower portion of the trench 118. The trench may be narrow from the upper portion toward the lower potion because the trench 118 may be formed using, for example, the plasma dry etching process. Thus, the sidewall 118a of the trench 118 may have a second inclination angle substantially larger than the first inclination angle. In some embodiments of the present invention, the second inclination angle may substantially correspond to an angle between the sidewall 118a of the trench 118 and a bottom face 118b of the trench 118.
A thermal oxidation layer (not shown) and an insulating liner (not shown) are successively formed on an inner face of the trench 118 after the trench 118 is formed. The thermal oxidation layer may have a relatively thin thickness. The thermal oxidation layer may be formed by, for example, oxidizing the inner face of the trench 118 so that damage caused by performing the dry etching process may be cured. The insulating liner may be formed on the thermal oxidation layer and the mask pattern. A thickness of the insulating liner may be about hundreds of angstroms. The insulating liner may decrease a stress generated in a silicon oxide layer subsequently filling up the trench 118 to form an isolation layer. Furthermore, the insulating liner may reduce the likelihood that impurity ions will penetrate into the isolation region. In some embodiments of the present invention, the insulating liner may be formed using a material having a relatively high etching selectivity with respect to the silicon oxide layer under predetermined etching conditions. For example, the insulating liner may be formed using silicon nitride (SiN).
Referring now to
An annealing process may be performed on the insulating layer at an environment having a relatively high temperature of from about 800° C. to about 1050° C. and an inert gas. In embodiments of the present invention where the annealing process is performed on the insulating layer, the insulating layer may become dense. Thus, a wet etch rate may decrease while a cleaning process is subsequently performed.
The insulating layer may be planarized by an etch-back or a chemical mechanical polishing (CMP) process until at least a portion of the mask pattern is exposed. Thus, the insulating layer may be transformed into an insulating layer pattern 120 located in the trench 118.
Although not illustrated in the figures, the mask pattern is removed so that a portion of the semiconductor substrate 100 corresponding to the active region may be exposed.
A center portion of the active region may be relatively planar. Furthermore, an edge portion of the active region may have the first inclination angle. Thus, in case that a thermal oxidation process is performed on the edge portion of the active region, a stress due to a three dimensional effect may not be generated. As a result, when an oxide layer is subsequently formed on the active region by using a thermal oxidation process, a portion of the oxide layer located on the edge portion of the active region may have substantially the same thickness as a portion of the oxide layer located on the center portion of the active region. In some embodiments of the present invention, the oxide layer may be used as a gate oxide layer of a gate structure, a tunnel oxide layer of a non-volatile memory device, and the like without departing from the scope of the present invention.
Referring now to
Referring now to
The mask pattern is then removed so that a third opening 203 exposing the active region may be formed. In particular, the nitride layer pattern included in the mask pattern is removed by a wet etching process using phosphoric acid (H3PO4). Thereafter, the pad oxide layer pattern included in the mask pattern is removed using a wet etching process using a dilute hydrogen fluoride (HF) solution.
In some embodiments of the present invention, the insulating layer pattern 202 may be partially removed while the pad oxide layer pattern is removed because the insulating layer pattern 202 is formed from a silicon oxide. Thus, an edge portion of the active region having a first inclination angle may be also exposed from the third opening 203.
Referring now to
The gate oxide layer 204 may be formed using, for example, a thermal oxidation process. A gate oxide layer 204 may be formed on the center portion and edge portions of the active region. The gate oxide layer 204 may have a relatively uniform thickness because the edge portion of the active region is slightly inclined.
Referring now to
Thereafter, an upper portion of the conductive layer may be partially removed such that an upper face of the insulating layer pattern 202 may be exposed. Thus, the gate electrode 206 may be formed.
Referring now to
Referring now to
Thereafter, the mask pattern is removed so that the active region may be exposed. In some embodiments of the present invention, a third opening 303 may be formed between the insulating layer patterns 302. In particular, the nitride layer pattern included in the mask pattern is removed by a wet etching process using phosphoric acid (H3PO4). Thereafter, the pad oxide layer pattern included in the mask pattern is removed by a wet etching process using a dilute hydrogen fluoride (HF) solution.
While the pad oxide layer pattern is removed, the insulating layer pattern 302 may be partially removed. In other words, the insulating layer pattern 302 may be partially removed while etching the pad oxide layer pattern because the insulating layer pattern 302 includes silicon oxide. As a result, an edge portion of the active region having a first inclination angle may be also exposed from a bottom face of the third opening 303.
Furthermore, a process for enlarging the active region may be performed such that the edge portion of the active region is fully exposed. In the process for enlarging the active region, a sidewall of the insulting layer pattern 302 may be partially removed. As discussed above, the active region may include the center portion that is relatively planar and the edge portion that has a first inclination angle.
Referring now to Figure, a tunnel oxide layer 304 is formed on the active region having the center portion and the edge portion. To form the tunnel oxide layer 304, a radical oxidation process is initially performed. Thereafter, an annealing process is performed in-situ with nitric oxide (NO). In some embodiments of the present invention, the tunnel oxide layer 304 formed on the center portion and the edge portion may have a relatively uniform thickness because the active region has the center portion that is relatively planar and the edge portion that has a slight incline.
The possibility of current leakage due to an irregular thickness of the tunnel oxide layer 304 may be decreased by forming the tunnel oxide layer 304 on the active region, thereby having a relatively uniform thickness.
Referring now to
The insulating layer pattern 302 may be partially removed such that an outer sidewall of the floating gate electrode 306 is exposed. Although not illustrated in the figures, a floating gate electrode having a substantial “U” shape may be formed on the tunnel oxide layer 304 such that the floating gate is formed along an inner surface of the third opening. In particular, a first conductive layer formed along the inner surface of the third opening may be formed such that the third opening is not completely filled with the first conducive layer. A sacrificial layer may be formed in the third opening. The first conductive layer is partially removed such that an upper face of the insulating layer pattern 302 is exposed. Thus, the floating gate electrode having a substantial “U” shape may be formed.
Referring now to
Although not illustrated in the figures, the second conductive layer 210, the dielectric layer and the floating gate electrode 306 are etched so that a non-volatile memory device including the control gate electrode (not shown), a dielectric layer pattern (not shown) and a floating gate electrode 306 may be formed.
According to some embodiments of the present invention, a pad oxide layer is partially removed by a diluted hydrogen fluoride solution. An exposed portion of a semiconductor substrate is removed by a standard cleaning 1 (SC1) solution. Thus, an active region having a center portion that is relative planar and a slightly inclined edge portion may be efficiently formed. As a result, an oxide layer having a relatively uniform thickness may be continuously formed on the active region by an oxidation process.
When the oxide layer is used as a tunnel oxide layer of a non-volatile memory device or a gate oxide layer of a gate electrode, the likelihood of a current leakage decreasing reliability of a semiconductor device may be reduced because a portion of the oxide layer formed on the edge portion and a portion of the oxide layer formed on the center portion have substantially the same thickness.
In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0063897 | Jul 2006 | KR | national |
