Patent Application
20250176276
This application claims priority to Chinese patent application No. 202311575226.X, filed on Nov. 23, 2023, and entitled “Trench Semiconductor Power Device”, the disclosure of which is hereby incorporated by reference in its entirety.
The present invention relates to a trench-type semiconductor power device, and more particularly, relates to a trench-type semiconductor power device having an electrostatic discharge protection structure.
Semiconductor power devices are widely used in the fields of automotive electronics, switching power supplies, etc. Trench power devices, in which gate oxide layers are grown on the sidewalls of gate trenches and polysilicon is filled to form gates, are one of the most popular power switching devices at present. Trench power devices can improve device area utilization efficiency so that a larger device cell channel width per unit area can be obtained, thereby obtaining a larger current conducting capability.
Semiconductor power devices are susceptible to voltage spikes caused by electrostatic discharge (ESD) events (including the human-body model or the machine model). Large instantaneous currents and voltages caused by ESD events can cause gate oxide layers of trench power devices to be broken down, thereby causing damage, even burning or causing high current leakage. Therefore, a trench-type semiconductor power device having an ESD protection structure is required.
Embodiments of the present disclosure relate to a trench-type semiconductor power device. The trench-type semiconductor power device includes: a substrate having a first conductivity type; an epitaxial layer that is located on the substrate and has the first conductivity type; a body doped region that is located in the epitaxial layer and away from the substrate and that has a second conductivity type; a source doped region that is located in the body doped region and away from the substrate and that has the first conductivity type; and a trench structure that has a first depth in a first direction extending from the source doped region to the substrate and that comprises a first semiconductor layer extending in a second direction, the first direction being perpendicular to the second direction. The first semiconductor layer includes: a first part that abuts against the body doped region and the source doped region, and serves as a gate electrode having the first conductivity type; and a second part that extends in the second direction and away from the source doped region, and comprises a plurality of first doped regions having the first conductivity type and a plurality of second doped regions having the second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are staggered to form a first diode string having one or more back-to-back diodes. A first end of the first diode string is electrically connected to the gate electrode, and a second end of the first diode string is electrically connected to the source doped region by means of a first connection structure.
When the following detailed description is read with reference to the accompanying drawings, aspects of several embodiments of the present disclosure may be best understood. It should be noted that various structures may not be drawn to scale. Indeed, for clarity of discussion, the dimensions of the various structures can be arbitrarily enlarged or reduced.
The same or similar components are denoted with the same reference signs in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description with reference to the accompanying drawings.
The following disclosure provides numerous different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and configurations will be described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, the reference to forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may further include an embodiment in which another feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Moreover, reference numerals and/or letters may be repeated in various examples of the present disclosure. This repetition is for simplicity and clarity, and does not per se indicate the relationship between the embodiments and/or configurations discussed.
The embodiments of the present disclosure will be discussed in detail below. However, it should be understood that the present disclosure provides a number of applicable concepts that can be embodied in a wide variety of particular environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.
The present disclosure provides a trench-type semiconductor power device. Compared with general trench-type semiconductor power devices, the trench-type semiconductor power device of the present disclosure is formed in a cell region, and has diodes capable of providing electrostatic discharge (ESD) protection in the cell region. The trench-type semiconductor power device has diode strings that are formed, in trenches, by one or more back-to-back diodes (i.e., one or more pairs of diodes, each pair having two diodes connected in a back-to-back manner). When an ESD event occurs, an instantaneous large current will be directed out of the trench-type semiconductor power device by means of the diode strings in the trench, so that damage caused by the instantaneous large current to a gate of a power transistor in a trench can be avoided. Compared with power devices that require additional use of an ESD protection circuit, the trench-type semiconductor power device of the present disclosure can ensure that the power device is protected by diode strings in trenches, thereby increasing the reliability of the power device. Furthermore, the diode strings formed in the trenches will not affect the configuration of a gate pad, therefore, there is flexibility in circuit design and layout, and manufacturing costs can be reduced.
A gate of the vertical power transistor 10 is coupled to the gate terminal G by means of the gate resistor 30. The diode string 20 is coupled between the gate terminal G and the source terminal S. The diode string 20 is formed from one or more back-to-back diodes 22 (i.e., one or more pairs 22 of diodes, each pair 22 having two diodes connected in a back-to-back manner, as shown in
When an ESD event occurs, the gate resistor 30 may prevent an instantaneous large current from the gate terminal G from directly attacking the gate (e.g., a gate oxide) of the vertical power transistor 10. In addition, the instantaneous large current caused by the ESD event will flow through the diode string 20 to the source terminal S in order to be transferred away from the vertical power transistor 10 (e.g., to be transferred to a ground terminal). In other words, when the ESD event occurs, the gate resistor 30 and the diode string 20 may provide ESD protection to the vertical power transistor 10.
In some embodiments, the trench-type semiconductor power device 100_1 includes a semiconductor material layer 103, trench structures 110, conductive plugs 152, 161 and 162, and metal wires (or electrodes) 210a, 210b and 220a. The metal wires 210a, 210b and 220a form a metal layer (e.g., an M1 layer) closest to the semiconductor material layer 103 in an interconnect structure. In some embodiments, the metal wires 210a, 210b and 220a extend in the X direction and are parallel to each other. In some embodiments, the width of the metal wire 210a is greater than the widths of the metal wires 210b and 220a, and the widths of the metal wires 210b and 220a are the same, the widths being measured in the Y direction. Materials of the metal wires 210a, 210b and 220a may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys.
The semiconductor material layer 103 may include, for example, an N-type or P-type monocrystalline silicon material, an epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the semiconductor material layer 103 is an N-type (first conductivity type) epitaxial material. For ease of illustration, using the N-type semiconductor material layer 103 as an example, the semiconductor material layer 103 has an N-type lightly doped region 104 to illustrate an N-type vertical power transistor 10, but the present disclosure is not limited to this. The N-type (first conductivity type) or P-type (second conductivity type) semiconductor material layer 103 may be adjusted depending on the conductivity type of the vertical power transistor 10.
A substrate 102 is formed on a lower surface of the semiconductor material layer 103, and has the same conductivity type doping as the lightly doped region 104, e.g., N type. The substrate 102 is a drain contact region of the vertical power transistor 10, and is coupled to the source terminal S and used to contact a drain metal layer (not shown in drawings). In some embodiments, the substrate 102 may be disposed adjacent to an upper surface of a silicon wafer or another semiconductor material substrate. In some embodiments, the substrate 102 is part of the silicon wafer. Materials of the substrate 102 may include a monocrystalline silicon material, an epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the doping concentration of the substrate 102 is greater than that of the lightly doped region 104.
The trench structures 110 extend in the Y direction, are parallel to each other, and have a depth D1 in the semiconductor material layer 103. The trench structures 110 may have vertical sidewalls and arc-shaped bottom surfaces. In some embodiments, the trench structures 110 may be circular, elliptical, rectangular, or polygonal. The trench structures 110 may be formed by an etching process (e.g., a plasma dry etching process) after locations and patterns are defined through a photoresist. Three trench structures 110 are shown in the embodiments of the trench-type semiconductor power device 100_1; the number of the trench structures 110 is merely an example, and not intended to limit the present disclosure.
Each of the trench structures 110 includes a semiconductor layer 120 extending in the Y direction and an insulating layer 115, wherein the semiconductor layer 120 has a width W1 in the X direction. The semiconductor layer 120 is surrounded by the insulating layer 115. The semiconductor layer 120 is formed from polysilicon, and can be divided into three parts 120_1, 120_2, and 120_3 (hereinafter referred to as first partial semiconductor layer 120_1, second partial semiconductor layer 120_2, and third partial semiconductor layer 120_3, respectively). In some embodiments, the trench-type semiconductor power device 100_1 further includes an interlayer dielectric layer 116 overlying the semiconductor material layer 103.
A doped region 106 is formed in the lightly doped region 104 of the semiconductor material layer 103 by means of an ion implantation process. The doped region 106 located between the first partial semiconductor layers 120_1 serves as a body doped region (hereinafter collectively referred to as body doped region 106) of the vertical power transistor 10. The body doped region 106 and the substrate 102 are located on two opposite sides of the lightly doped region 104 in a Z direction, respectively. The body doped region 106 has a different conductivity type than the lightly doped region 104, e.g., a P type. Electrically, the coverage area of the body doped region 106 will not have the characteristics of an N-type conductivity type. In other words, the body doped region 106 is located above the lightly doped region 104 and abuts against the lightly doped region 104. In the Z direction, the depth (or thickness) of the body doped region 106 is less than the depth D1 of the trench structure 110. In some embodiments, the semiconductor layer 120 includes silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond-based materials.
A doped region 108 located between the first partial semiconductor layers 120_1 serves as a source (hereinafter collectively referred to as source doped region 108) of the vertical power transistor 10. The source doped region 108 is located in (or above) the body doped region 106 and distant from the substrate 102. The source doped region 108 has a depth that is less than the depth of the body doped region 106, and has a different conductivity type to the body doped region 106, e.g., the N type. In some embodiments, the doping concentration of the source doped region 108 is greater than that of the lightly doped region 104.
In the trench structure 110, the second partial semiconductor layer 120_2 is located between the first partial semiconductor layer 120_1 and the third partial semiconductor layer 120_3. The first partial semiconductor layer 120_1 and the second partial semiconductor layer 120_2 have the same conductivity type doping as the lightly doped region 104, e.g., the N type. In some embodiments, the doping concentration of the first partial semiconductor layer 120_1 and the doping concentration of the second partial semiconductor layer 120_2 are greater than the doping concentration of the lightly doped region 104. Furthermore, the first partial semiconductor layer 120_1 is a part of the semiconductor layer 120 adjacent to the source doped region 108 to serve as a gate electrode of the vertical power transistor 10. The second partial semiconductor layer 120_2 extends in the Y direction and away from the source doped region 108, and has a length L1 (e.g., the distance from the source doped region 108 to a conductive plug 162 in the Y direction) to serve as a gate resistor Rg. The impedance of the gate resistor Rg is determined by the ratio of the length L1 to the width W1 of the second partial semiconductor layer 120_2. The third partial semiconductor layer 120_3 is a part of the semiconductor layer 120 located between the conductive plugs 161 and 162 to serve as an ESD protection structure ESD_P1 that forms the diode string 20. The semiconductor layer 120 is separated from the semiconductor material layer 103 by means of the insulating layer 115. Furthermore, the ESD protection structure ESD_P1 (i.e., the third partial semiconductor layer 120_3) is further separated from the doped region 106 by means of the insulating layer 115. It is worth noting that an upper surface of the semiconductor layer 120 will be lower than upper surfaces of the source doped region 108 and the insulating layer 115 to ensure that the semiconductor layer 120 will not remain on the upper surface of the source doped region 108 after etching is performed; if the semiconductor layer 120 remained on the upper surface of the source doped region 108 after etching, then this would affect the characteristics of the source doped region 108 or cause a short circuit between the source doped region 108 and the semiconductor layer 120.
The ESD protection structure ESD_P1 includes a plurality of doped regions 120n and a plurality of doped regions 120p. The doped regions 120n and the doped regions 120p have different conductivity types. For example, the doped regions 120n have the same conductivity type doping as the lightly doped region 104, e.g., N type, and the doped regions 120p have the same conductivity type doping as the body doped region 106, e.g., P type. In some embodiments, the doping concentration of the doped region 120n is greater than that of the lightly doped region 104. An interface between the doped regions 120n and the doped regions 120p will form a PN junction. Furthermore, each of the doped regions 120p and two of the doped regions 120n adjacent to the doped region 120p will form one back-to-back diode 22, for example, interfaces between each of the doped regions 120p and two of the doped regions 120n adjacent to the doped region 120p respectively form a first PN junction and a second PN junction of the back-to-back diode 22. In an embodiment of the ESD protection structure ESD_P1, the doped regions 120n and the doped regions 120p are staggered to form a diode string having two back-to-back diodes 22 connected in series (hereinafter collectively referred to as diode string 20_1).
It is worth noting that in the diode string 20_1 of the ESD protection structure ESD_P1, the number of the back-to-back diodes 22 is determined by the voltage resistance (e.g., breakdown voltage) of a gate oxide layer of the vertical power transistor 10. For example, the greater the breakdown voltage of the gate oxide layer, the higher the number of back-to-back diodes 22 in the diode string 20_1, that is, the higher the number of doped regions 120n and doped regions 120p. Moreover, by forming the diode string 20_1 in the trench structure 110, no additional ESD protection circuit or structure is required, and thus manufacturing costs can be reduced.
The first partial semiconductor layer 120_1 overlaps the metal wire 210a and is completely covered by the metal wire 210a. The second partial semiconductor layer 120_2 partially overlaps the metal wire 210a. The second partial semiconductor layer 120_2 and the third partial semiconductor layer 120_3 partially overlap the metal wire 220a, and the metal wire 220a is connected to the second partial semiconductor layer 120_2 and the doped regions 120n of the third partial semiconductor layer 120_3 by means of the conductive plug 162. The third partial semiconductor layer 120_3 partially overlaps the metal wire 210b, and the metal wire 210b is connected to the doped regions 120n of the third partial semiconductor layer 120_3 by means of the conductive plug 161.
A heavily doped region 112 is located in the body doped region 106. The conductive plug 152 extends in the Z direction penetrating through the interlayer dielectric layer 116 to connect the metal wire 210a, as well as the source doped region 108 and the heavily doped region 112 in the semiconductor material layer 103. The heavily doped region 112 has a different conductivity type than the lightly doped region 106, e.g., the N type. In some embodiments, the doping concentration of the heavily doped region 112 is less than that of the source doped region 108. The metal wire 210a is connected to the source terminal S by means of an interconnect structure 215. In the embodiments of the present invention, other metal wires (not shown) or conductive plugs (not shown) that are electrically connected between the metal wire 210a and the source terminal S are collectively referred to as the interconnect structures 215. For ease of illustration, the metal wire 210a, the conductive plug 152 and the interconnect structure 215 may serve as a source connection structure.
A heavily doped region 132 is located between the second partial semiconductor layer 120_2 and the third partial semiconductor layer 120_3, and surrounds one end of the conductive plug 162. The conductive plug 162 extends in the Z direction penetrating through the interlayer dielectric layer 116 and extending to the semiconductor layer, so as to connect the metal wire 220a and the semiconductor layer 120. The heavily doped region 132 has the same conductivity type as the semiconductor layer 120, e.g., the N type. The metal wire 220a is connected to the gate terminal G by means of an interconnect structure 225. In the embodiments of the present invention, other metal wires (not shown) and conductive plugs (not shown) that are electrically connected between the metal wire 220a and the gate terminal G are collectively referred to as the interconnect structure 225. For ease of illustration, the metal wire 220a, the conductive plug 162 and the interconnect structure 225 may serve as a gate connection structure.
A heavily doped region 131 is located in the doped region 120n at the rearmost end of the third partial semiconductor layer 120_3 and surrounds one end of the conductive plug 161. The conductive plug 161 extends in the Z direction penetrating through the interlayer dielectric layer 116 and extends into the third partial semiconductor layer 120_3 to electrically connect the metal wire 210b and the doped region 120n at the rearmost end. The heavily doped region 131 has the same conductivity type as the doped region 120n, e.g., the N type. The metal wire 210b is connected to the source terminal S and the metal wire 210a by means of the interconnect structure 215. In the embodiments of the present invention, other metal wires (not shown) and conductive plugs (not shown) that are electrically connected between the metal wire 210b and the source terminal S are collectively referred to as the interconnect structures 215. In some embodiments, the metal wire 210b is connected to the metal wire 210a by passing through the interconnect structure 215 (e.g., an M2 metal wire and a corresponding conductive plug) located at the upper layer. In some embodiments, the metal wire 210b is connected to the metal wire 210a by passing through the interconnect structure 215 (e.g., an M1 metal wire) located at the same layer.
In the X direction, the doped regions 120p and the doped regions 120n have a width W1. In the Y direction, the length L2 of the doped regions 120p is greater than the length L3 of the doped regions 120n. In some embodiments, the length L2 is about 3-4 microns (um) and the length L3 is about 2 microns. Furthermore, distances from the heavily doped regions 131 and 132 to the doped regions 120p are each a length L4. In some embodiments, the length L4 is less than or equal to the length L3. The lengths L2, L3 and L4 are determined according to process parameters of the vertical power transistor 10.
In the trench-type semiconductor power device, the configuration of each of the conductive plugs may vary depending on process or electrical requirements. Materials of the conductive plugs may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, the conductive plugs 161, 162 are in a columnar configuration. In some embodiments, the conductive plug 161 or 162 has approximately the same depth in the Z direction. In some embodiments, the conductive plug 152 has a configuration that is wide at the top and narrow at the bottom.
In each of the ESD protection structures ESD_P1, a first end of the diode string 20_1 (i.e., the doped region 120n abutting against the second partial semiconductor layer 120_2 or the doped region 120n provided with the heavily doped region 132) is electrically connected to a gate of the vertical power transistor 10 by means of the gate resistor Rg, and a second end of the diode string 20_1 (i.e., the doped region 120n away from the second partial semiconductor layer 120_2 or the doped region 120n provided with the heavily doped region 131) is electrically connected to the source doped region 108 by means of a source connection structure (e.g., the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_1, the gate resistor 30 in
The ESD protection structure ESD_P2 includes a semiconductor layer 310 formed by plate-shaped polysilicon. The semiconductor layer 310 includes a plurality of doped regions 310n and a plurality of doped regions 310p, the doped regions 310n and the doped regions 310p having different conductivity types. For example, the doped regions 310n have the same conductivity type doping as the doped regions 120n, e.g., the N type, and the doped regions 310p have the same conductivity type doping as the doped regions 120p, e.g., the P type. In the ESD protection structure ESD_P2, the doped regions 310n and the doped regions 310p are staggered to form a diode string having two back-to-back diodes 22 connected in series (hereinafter collectively referred to as diode string 20_2). Furthermore, the number of the back-to-back diodes 22 in the diode string 20_2 is equal to the number of the back-to-back diodes 22 in the diode string 20_1. In some embodiments, in the X direction, the width of the doped regions 310p and 310n is greater than the width W1 of the doped regions 120p and 120n. In the Y direction, the doped regions 120p and 310p have the same length L2, and the doped regions 120n and 310n have the same length L3.
A heavily doped region 141 is located at the doped region 310n adjacent to the ESD protection structure ESD_P1 and surrounds one end of a conductive plug 171. The conductive plug 171 extends in the Z direction through the interlayer dielectric layer 116 and into the semiconductor layer 310 to connect the metal wire 210b. A heavily doped region 142 is located at the doped region 310n away from the ESD protection structure ESD_P1 and surrounds one end of a conductive plug 172. The conductive plug 172 extends in the Z direction through the interlayer dielectric layer 116 to connect the metal wire 220b. The metal wire 220b is connected to the gate terminal G and the metal wire 220a by means of the interconnect structure 225. The heavily doped regions 141 and 142 have the same conductivity type as the semiconductor layer 120, e.g., the N type. For ease of illustration, the metal wires and the conductive plugs connected to the interconnect structure 215 may serve as a source connection structure, and the metal wires and the conductive plugs connected to the interconnect structure 225 may serve as a gate connection structure.
In the trench-type semiconductor power device 100_1A, the ESD protection structure ESD_P2 is separated from the ESD protection structure ESD_P1 and surrounded by the interlayer dielectric layer 116. In addition, the semiconductor layer 310 of the ESD protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps the body doped region 106. Therefore, the depths of the conductive plugs 171 and 172 in the Z direction are less than those of the conductive plugs 161 and 162.
In the ESD protection structure ESD_P2, a first end (i.e., the doped region 120n away from the ESD protection structure ESD_P1, or the doped region 310n provided with the heavily doped region 142) of the diode string 20_2 is electrically connected to a gate resistor Rg by means of the gate connection structure (e.g., the metal wire 220b, the interconnect structure 225, etc.), and a second end (i.e., the doped region 120n adjacent to the ESD protection structure ESD_P1, or the doped region 310n provided with the heavily doped region 141) of the diode string 20_2 is electrically connected to the source doped region 108 by means of the source connection structure (e.g., the metal wire 210b, the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_1A, the diode string 20 in
The cross-sectional view of the trench-type semiconductor power device 100_1B shown in
In some embodiments of the trench-type semiconductor power device 100_1C, the semiconductor layer 310 of the ESD protection structure ESD_P2 has the same depth in the Z direction as the semiconductor layer 120 of the ESD protection structure ESD_P1. The trench of the ESD protection structure ESD_P2 may be formed at the same time as the trench structures 110, and at the same time, the insulating layer 115 will be underlaid in the trench of the ESD protection structure ESD_P2. The semiconductor layer 310 can be formed in the same step as the semiconductor layer 120, and surrounded by the insulating layer 115. The first end of the diode string 20_2 in the ESD protection structure ESD_P2 is electrically connected to the metal wire 220b by means of a heavily doped region 134 and a conductive plug 164, and the second end of the diode string 20_2 is electrically connected to the metal wire 210b by means of a heavily doped region 133 and a conductive plug 163. The heavily doped regions 133 and 134 have the same conductivity type as the heavily doped regions 131 and 132. The heavily doped regions 133 and 134 can be formed in the same step as the heavily doped regions 131 and 132, and thus have the same or similar configuration as the heavily doped regions 131 and 132, and the locations of the heavily doped regions 133 and 134 in the semiconductor layer 310 also correspond to the locations of the heavily doped regions 131 and 132 in the semiconductor layer 120. The depths of the conductive plugs 161-164 in the Z direction are the same. In the present embodiment, the same or similar process steps may be used to implement the ESD protection structures ESD_P1 and ESD_P2, therefore manufacturing costs may be reduced.
The shielding structure 111 is a comb-shaped trench structure, and consists of a plurality of trench structures extending in the Y direction (hereinafter referred to as first sub-shielding structures 111a) and one trench structure extending in the X direction (hereinafter referred to as second sub-shielding structure 111b). Each of the trench structures 110 is disposed between two adjacent first sub-shielding structures 11la, and the second sub-shielding structure 111b is disposed at an ESD protection structure ESD_P1 close to the trench structure 110, i.e., the second sub-shielding structure 111b is away from the source doped region 108. The shielding structure 111 has a depth D2 in the semiconductor material layer 103, and the depth D2 of the shielding structure 111 is greater than the depth D1 of the trench structures 110. The shielding structure 111 includes a semiconductor layer 122. The semiconductor layer 122 has a width W2 in the X direction and the width W2 is larger than the width W1. The semiconductor layer 122 has the same conductivity type doping as the lightly doped region 104, e.g., an N type. In addition, in the shielding structure 111, the semiconductor layer 122 is surrounded by the insulating layer 115.
In the trench-type semiconductor power device 100_2, similar to the trench-type semiconductor power device 100_1, each of the trench structures 110 includes one ESD protection structure ESD_P1. The ESD protection structure ESD_P1 is separated from the shielding structure 111 by means of the lightly doped region 104 and the body doped region 106. In some embodiments, the source doped region 108 of the trench-type semiconductor power device 100_2 is formed in the trench-type semiconductor power device 100_2, and only on the side of the conductive plug 152 adjacent to the trench structures 110. Heavily doped regions 135 and 137 are located in the semiconductor layer 122 and have the same conductivity type doping as the lightly doped region 104, such as the N type. Conductive plugs 165 and 167 extend in the Z direction penetrating through the interlayer dielectric layer 116 in order to electrically connect the semiconductor layer 122 to the metal wires 210a and 210b. As previously described, the metal wire 210b is connected to the source terminal S and the metal wire 210a by means of the interconnect structure 215. For ease of illustration, the conductive plugs 165 and 167 can be used as source connection structures.
In the embodiments of the trench-type semiconductor power device 100_2, the gate resistor 30 in
The ESD protection structure ESD_P2 includes the semiconductor layer 310 having a plurality of doped regions 310n and a plurality of doped regions 310p. In the trench-type semiconductor power device 100_2A, the ESD protection structure ESD_P2 is separated from the ESD protection structure ESD_P1 and surrounded by the interlayer dielectric layer 116. The shielding structure 111 is disposed between the ESD protection structure ESD_P2 and the ESD protection structure ESD_P1. Furthermore, the semiconductor layer 310 of the ESD protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps the body doped region 106. Accordingly, the depths of the conductive plugs 171 and 172 in the Z direction are less than those of the conductive plugs 161 and 162.
In the ESD protection structure ESD_P2, the first end (i.e., the doped region 120n distant from the ESD protection structure ESD_P1, or the doped region 310n provided with the heavily doped region 142) of the diode string 20_2 is electrically connected to the gate terminal G by means of a gate connection structure (e.g., the metal wire 220b, the interconnect structure 225, etc.), and the second end (i.e., the doped region 120n adjacent to the ESD protection structure ESD_P1, or the doped region 310n provided with the heavily doped region 141) of the diode string 20_2 is electrically connected to the source terminal S by means of a source connection structure (e.g., the metal wire 210b, the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_2A, the diode string 20 in
In other embodiments, the ESD protection structure ESD_P2 of the trench-type semiconductor power device 100_2A and the ESD protection structure ESD_P1 are formed in the same horizontal plane in the Z direction and disposed in different trenches separated from each other, e.g., the ESD_P1 and the ESD_P2 shown in
In the trench-type semiconductor power device 100_2B, the semiconductor layer 310 forming the ESD protection structure ESD_P2 extends in the Y direction towards the shielding structure 111 to connect the semiconductor layer 122 of the second sub-shielding structure 111b extending in the Z direction, that is, the semiconductor layer 310 will abut against the semiconductor layer 122. The semiconductor layer 122 is electrically connected to the metal wire 210b by means of the heavily doped region 141 and the conductive plug 171.
The ESD protection structure of the present disclosure may be integrated with a gate structure to achieve the effects of reducing manufacturing costs and reducing product area. In other embodiments, the ESD protection structures of the present disclosure may be further integrated with a shielding electrode to achieve the effect of enhancing the effectiveness of ESD protection. Various exemplary embodiments in which the ESD protection structures are integrated with the shielding electrode are provided below, but the present disclosure is not limited thereto.
In the ESD protection structures ESD_P3, the semiconductor layer 122 of the first sub-shielding structures 111a is divided into the first partial semiconductor layer 122 away from the second sub-shielding structure 111b and the second partial semiconductor layer 122 close to the second sub-shielding structure 111b. In other words, the first partial semiconductor layer 122 is close to the source doped region 108, and the second sub-shielding structure 111b is distant from the source doped region 108. The first partial semiconductor layer 122 is completely covered with the metal wire 210a, and electrically connected to the metal wire 210a by means of the conductive plug 165. The first partial semiconductor layer 122 has the same conductivity type doping as the lightly doped region 104, e.g., the N type. The second partial semiconductor layer 122 includes the plurality of doped regions 122n and the plurality of doped regions 122p. The doped regions 122n and the doped regions 122p have different conductivity types. For example, the doped regions 122n have the same conductivity type doping as the doped regions 120n, e.g., the N type, and the doped regions 122p has the same conductivity type doping as the doped regions 120p, e.g., the P type. An interface between the doped regions 122n and the doped regions 122p will form a PN junction. Furthermore, each of the doped regions 122p and two of the doped regions 122n adjacent to said doped region 122p form one back-to-back diode (that is, the back-to-back diode 22 in
In the embodiments of the trench-type semiconductor power device 100_2C, the first sub-shielding structures 111a of the shielding structure 111 (i.e., a trench structure extending in the Y direction) includes two ESD protection structures ESD_P3, e.g., an ESD protection structure ESD_P3 disposed between the metal wires 210b and 220a (hereinafter collectively referred to as ESD protection structure ESD_P3a) and an ESD protection structure ESD_P3 disposed between the metal wires 210a and 220a (hereinafter collectively referred to as ESD protection structure ESD_P3b). In some embodiments, an ESD protection structure ESD_P1 is disposed between two ESD protection structures ESD_P3a, and a gate resistor Rg is disposed between two ESD protection structures ESD_P3b. In some embodiments, the first sub-shielding structures 111a of the shielding structure 111 includes only one ESD protection structure ESD_P3, e.g., an ESD protection structure ESD_P3a or ESD_P3b.
In the ESD protection structure ESD_P3a, the first end (i.e., the doped region 120n adjacent to the first partial semiconductor layer 122, or the doped region 122n provided with a heavily doped region 136) of the diode string 20_3 is electrically connected to a gate terminal G by means of a gate connection structure (e.g., a conductive plug 166, the metal wire 220a, the interconnect structure 225, etc.), and the second end (i.e., the doped region 120n away from the first partial semiconductor layer 122, or the doped region 122n provided with a heavily doped region 137a) of the diode string 20_3 is electrically connected to the source terminal S by means of a source connection structure (e.g., a conductive plug 167a, the metal wire 210b, the interconnect structure 215, etc.). In the ESD protection structure ESD_P3b, the first end (i.e., the doped region 120n distant from the first partial semiconductor layer 122, or the doped region 122n provided with the heavily doped region 136) of the diode string 20_3 is electrically connected to the gate terminal G by means of the gate connection structure (e.g., the conductive plug 166, the metal wire 220a, the interconnect structure 225, etc.), and the second end (i.e., the doped region 120n adjacent to the first partial semiconductor layer 122, or the doped region 122n provided with a heavily doped region 135a) of the diode string 20_3 is electrically connected to the source terminal S by means of the source connection structure (e.g., a conductive plug 165a, the metal wire 210a, the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_2C, the diode string 20 in
In the trench-type semiconductor power device 100_2D, the ESD protection structure ESD_P2 is separated from ESD protection structures ESD_P1 and ESD_P3, and surrounded by the interlayer dielectric layer 116. Furthermore, the second sub-shielding structure 111b of the shielding structure 111 (i.e., a trench structure extending in the X direction) is disposed between the ESD protection structure ESD_P2 and the ESD protection structure ESD_P1 (or the ESD protection structure ESD_P3a). The semiconductor layer 310 of the ESD protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps the body doping region 106. Accordingly, the depths of the conductive plugs 171 and 172 in the Z direction are less than those of the conductive plugs 161, 162, 165a, 166, 167, and 167a.
In the ESD protection structure ESD_P2, the first end (i.e., the doped region 120n distant from the ESD protection structure ESD_P1, or the doped region 310n provided with a heavily doped region 142) of the diode string 20_2 is electrically connected to the gate terminal G by means of a gate connection structure (e.g., the metal wire 220b, the interconnect structure 225, etc.), and the second end (i.e., the doped region 120n adjacent to the ESD protection structure ESD_P1, or the doped region 310n provided with the heavily doped region 141) of the diode string 20_2 is electrically connected to the source terminal S by means of a source connection structure (e.g., the metal wire 210b, the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_2D, the diode string 20 in
In some embodiments, the ESD protection structure ESD_P2 of the trench-type semiconductor power device 100_2D and the ESD protection structure ESD_P1 are formed in the same horizontal plane in the Z direction and disposed in different trenches separated from each other. In some embodiments, the ESD protection structure ESD_P2 of the trench-type semiconductor power device 100_2D and the ESD protection structure ESD_P3 are formed in the same horizontal plane in the Z direction and disposed in different trenches separated from each other.
In the trench-type semiconductor power device 100_2E, the semiconductor layer 310 forming the ESD protection structure ESD_P2 extends in the Y direction towards the shielding structure 111 to connect the' semiconductor layer 122 in the second sub-shielding structure 111b extending in the Z direction, that is, the semiconductor layer 310 will abut against the semiconductor layer 122. The semiconductor layer 122 of the second sub-shielding structure 111b is electrically connected to the metal wire 210b by means of the heavily doped region 141 and the conductive plug 171.
Several embodiments in which the ESD protection structures are integrated with the gate structure and/or the shielding electrode structure are provided above, which illustrates that the present disclosure may be broadly applied to various types of trench-type semiconductor power devices. Various embodiments in which the ESD protection structures are integrated into the gate structure and/or the shielding electrode structure of a split gate (SGT) semiconductor devices are provided below as an exemplary description, but the present disclosure is not limited thereto.
In the embodiments of the trench-type semiconductor power device 100_3, the shielding structure 113 has a depth D3 in a semiconductor material layer 103, and the shielding structure 113 extends in the Y direction. In some embodiments, the depth D3 of the shielding structure 113 is greater than the depth D1 of the trench structure 110. Furthermore, the shielding structure 113 has a depth D4 in the semiconductor material layer 103, and the shielding structure 113 extends in the X direction. In some embodiments, the depth D3 is equal to the depth D4. In some embodiments, the depth D3 is different from the depth D4. The shielding structure 113 includes a semiconductor layer 126. The semiconductor layer 126 has the same conductivity type doping as the lightly doped region 104, e.g., N-type. In some embodiments, the doping concentration of the semiconductor layer 126 is greater than that of the lightly doped region 104. Furthermore, in the shielding structure 113, the semiconductor layer 126 is surrounded by the insulating layer 115. The shielding structure 113 is separated from the trench structure 110a by passing through the lightly doped region 104 and the body doped region 106.
In the trench structure 110a, the semiconductor layer 124 is separated from a semiconductor layer 120 and surrounded by the insulating layer 115. The semiconductor layer 124 has the same conductivity type doping as the lightly doped region 104, e.g., N-type. In some embodiments, the doping concentration of the semiconductor layer 124 is greater than that of the lightly doped region 104. The semiconductor layer 124 can be divided into two parts 124_1 and 124_2 (hereinafter referred to as first partial semiconductor layer 124_1 and second partial semiconductor layer 124_2, respectively). The first partial semiconductor layer 124_1 extends in the Y direction and is disposed between the semiconductor layer 120 and the lightly doped region 104. The second partial semiconductor layer 124_2 extends in the Z direction and is disposed between the ESD protection structure ESD_P1 and the body doped region 106 (or the shielding structure 113). In the Z direction, the first partial semiconductor layer 124_1 overlaps the semiconductor layer 120, and the second partial semiconductor layer 124_2 does not overlap the semiconductor layer 120. Furthermore, in the Z direction, the thickness of the first partial semiconductor layer 124_1 and the thickness of the semiconductor layer 120 are less than the depth D3.
A heavily doped region 151 is located in the second partial semiconductor layer 124_2 and surrounds one end of a conductive plug 181. The conductive plug 181 extends in the Z direction through the interlayer dielectric layer 116 to connect the metal wire 210b and the second partial semiconductor layer 124_2. A heavily doped region 139 is located in the semiconductor layer 126 and surrounds one end of a conductive plug 169. The conductive plug 169 extends in the Z direction through the interlayer dielectric layer 116 to connect the metal wire 210b and the semiconductor layer 126. The heavily doped regions 151 and 139 have the same conductivity type as the lightly doped region 104, e.g., the N type. In the trench-type semiconductor power device 100_3, the semiconductor layer 124 and the semiconductor layer 126 are connected to the source terminal S by means of a source connection structure (e.g., the metal wire 210b, the interconnect structure 215, etc.).
The ESD protection structures ESD_P4 are formed in the second partial semiconductor layer 124_2 of each of the trench structures 110a. Each of the ESD protection structures ESD_P4 includes a plurality of doped regions 124n and a plurality of doped regions 124p. The doped regions 124n and the doped regions 124p have different conductivity types. For example, the doped regions 124n have the same conductivity type doping as the doped regions 120n, e.g., the N type, and the doped regions 124p has the same conductivity type doping as the doped regions 120p, e.g., the P type. An interface between the doped regions 124n and the doped regions 124p will form a PN junction. Furthermore, each of the doped regions 124p and two of the doped regions 124n adjacent to the doped region 120p form a back-to-back diode 22. In the ESD protection structures ESD_P4, the doped regions 124n and the doped regions 124p are staggered to form a diode string having two back-to-back diodes 22 connected in series (hereinafter collectively referred to as diode string 20_4). Furthermore, the number of back-to-back diodes 22 in the diode string 20_4 is the same as that of the back-to-back diodes 22 in the diode string 20_1.
In some embodiments, the doped regions 124n and 120n have the same length L3 in the Y direction, and the doped regions 124p and 120p have the same length L2 in the Y direction. Furthermore, in the Z direction, the depths of the doped regions 124n and 124p are greater than the depths of the doped regions 120n and 120p.
A heavily doped region 151 is located in the doped region 124n at the frontmost end (e.g., abutting against the first partial semiconductor layer 124_1) of the second partial semiconductor layer 124_2, and surrounds one end of the conductive plug 181. The conductive plug 181 extends in the Z direction through the interlayer dielectric layer 116 to connect the metal wire 210b and the doped region 124n at the frontmost end. A heavily doped region 154 is located in the doped region 124n at the rearmost end (e.g., away from the first partial semiconductor layer 124_1) of the second partial semiconductor layer 124_2, and surrounds one end of the conductive plug 182. The conductive plug 182 extends in the Z direction through the interlayer dielectric layer 116 to connect the metal wire 220b and the doped region 124n at the rearmost end. The heavily doped regions 151 and 154 have the same conductivity type as the doped regions 120n, e.g., the N type. The metal wire 210b is connected to the source terminal S and the metal wire 210a by means of the interconnect structure 215.
In the ESD protection structures ESD_P4, the first end (i.e., the doped region 124n away from an ESD protection structure ESD_P1, or the doped region 124n provided with the heavily doped region 154) of the diode string 20_4 is electrically connected to the gate terminal G by means of a gate connection structure (e.g., the metal wire 220b, the interconnect structure 225, etc.), and the second end (i.e., the doped region 124n adjacent to the ESD protection structure ESD_P1, or the doped region 124n provided with the heavily doped region 151) of the diode string 20_4 is electrically connected to the source terminal S by means of a source connection structure (e.g., the metal wire 210b, the interconnect structure 215, etc.). The ESD protection structures ESD_P1 and ESD_P4 partially overlap the metal wire 210b. The metal wire 210b is connected to the doped region 120n of the ESD protection structure ESD_P1 by means of the conductive plug 161 and to the doped region 124n of the ESD protection structure ESD_P4 by means of the conductive plug 181. In each of the shielding structures 110a, the ESD protection structure ESD_P1 may be connected in parallel with the ESD protection structure ESD_P4 through the source connection structure (e.g., associated metal wires and conductive plugs connected to the interconnect structure 215) and the gate connection structure (e.g., associated metal wires and conductive plugs connected to the interconnect structure 225). In other words, in the embodiments of the trench-type semiconductor power device 100_3A, a diode string 20 in
In the trench-type semiconductor power device 100_3B, the ESD protection structure ESD_P2 is separated from an ESD protection structure ESD_P1 and an ESD protection structure ESD_P4, and surrounded by the interlayer dielectric layer 116. The shielding structure 113 is disposed between the ESD protection structure ESD_P2 and the ESD protection structure ESD_P4. Furthermore, the ESD protection structure ESD_P2 is formed above the semiconductor layer 120 and overlaps the body doped region 106.
In the ESD protection structure ESD_P2, the first end (i.e., a doped region 120n adjacent to the ESD protection structure ESD_P1, or a doped region 310n provided with a heavily doped region 141) of the diode string 20_2 is electrically connected to the gate terminal G by means of a gate connection structure (e.g., the conductive plug 171, the metal wire 220b, the interconnect structure 225, etc.), and the second end (i.e., a doped region 120n distant from the ESD protection structure ESD_P1, or a doped region 310n provided with a heavily doped region 142) of the diode string 20_2 is electrically connected to the source terminal S by means of a source connection structure (e.g., the conductive plug 172, the metal wire 210c, the interconnect structure 215, etc.). In the embodiments of the trench-type semiconductor power device 100_3A, the diode string 20 in
In some embodiments, the ESD protection structure ESD_P2 of the trench-type semiconductor power device 100_3B and the ESD protection structure ESD_P1 or the ESD protection structure ESD_P4 are formed in the same horizontal plane in the Z direction and disposed in different trenches separated from each other.
In the trench-type semiconductor power device 100_3C, the semiconductor layer 310 forming the ESD protection structure ESD_P2 extends in the Y direction towards the shielding structure 113 to connect a semiconductor layer 126 extending in the Z direction, that is, the semiconductor layer 310 will abut against the semiconductor layer 126. The semiconductor layer 126 is electrically connected to the metal wire 220b by means of the heavily doped region 141 and the conductive plug 171.
Herein, for convenience of description, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left side,” and “right side” may be used to describe the relationship between one component or feature and another or more components or features as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, the spatially relative terms may be intended to encompass different orientations of a device in use or operation. The apparatus may be otherwise oriented (by rotating 90 degrees or at other orientations) and similarly, spatially relative descriptors used herein may be interpreted in a corresponding manner. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to another component, or an intermediate component may be present.
As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and interpret small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs exactly as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term “about” refers generally to within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. The range may be expressed herein as one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may refer to the difference in position of two surfaces positioned along the same plane being within several microns (μm), such as the difference in locating position along the same plane being within 10 μm, 5 μm, 1 μm or 0.5 μm. When values or properties are referred to as being “substantially” identical, the term may refer to values that are within ±10%, ±5%, ±1%, or ±0.5% of the mean value of the stated values.
The foregoing summarizes the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures to facilitate implementation of the same or similar purpose and/or achieve the same or similar advantages of the embodiments introduced herein. Such equivalents are not departing from the spirit and scope of the present disclosure, and various changes, replacements and alterations may be made without departing from the spirit and scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311575226.X | Nov 2023 | CN | national |
