1. Field of the Invention
The present disclosure relates generally to graphical manipulation of objects defined in three-dimensional space, and more particularly but not exclusively, to the rendering of such objects into a color buffer for subsequent display on a two-dimensional screen such as a computer monitor.
One embodiment of the invention has been developed primarily for use in graphics chips where speed and throughput of rendered polygons is paramount, and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to use in this field.
2. Description of the Related Art
The market for “3D” accelerator video cards for PCs and other computing platforms has grown drastically in recent years. With this growth has come an increasing desire for faster accelerator chips incorporating an increasing number of features such as realistic lighting models and higher onscreen polygon counts at higher resolutions.
A typical 3D accelerator includes a rasterizing section that takes mathematical representations of the polygons (usually triangles) in three-dimensional space and renders them down to a two dimensional representation suitable for display on a computer monitor or the like. The steps in this procedure are relatively well known in the art, and include a color rendering stage where colors from a texture map associated with each polygon are mapped to individual pixels in the two dimensional buffer. Due to memory bandwidth issues, it is desirable to reduce the amount of textures that are imported for mapping onto each polygon.
To ensure that polygons are drawn correctly on the screen, each pixel of each polygon as it is considered is depth compared with any pixel already at a corresponding pixel location in the color buffer. This is usually done with reference to a depth buffer. In one such arrangement, the depth buffer is the same size as the color buffer, and is used to maintain depth data in the form of a depth value for each pixel that has been written to the color buffer. When a new pixel is being considered, its depth value is compared with the depth value associated with any pixel that has already been written to the color buffer at the new pixel's location. In the event that the new pixel is behind the old, then it is discarded because it will be obscured. Conversely, if the new pixel is in front of the old, the new pixel's depth value replaces that of the old pixel in the depth-buffer, and color data is retrieved from associated texture memory and written over the old pixel's color data in the color buffer.
Whilst it provides technically useful results, the use of a depth buffer in this fashion often results in large amounts of texture data unnecessarily being retrieved and written to the color buffer. This is because a particular pixel location in the color buffer may be written over several times as new is triangles are found to overlay existing triangles at those locations.
In accordance with a first aspect of the invention, there is provided a method of rendering a plurality of triangles into a color buffer defined by a plurality of pixel locations, utilizing a triangle identification buffer and a depth buffer, the method including:
In one embodiment, (f) includes:
In an embodiment, in the event a triangle being rasterized in (f) has a texture associated with it, (f) further includes forwarding information to the texture cache to enable prefetching of the texture to commence.
In an embodiment, the depth buffer and the triangle identification buffer are combined, such that, at each address defining a pixel location in the combined buffer, there is space for a depth value and a triangle identifier value.
In one form, the depth buffer and triangle buffer are combined with the color buffer, such that, at each address defining a pixel location in the combined buffer, there is space for the depth value, the triangle identifier value and color values.
In one embodiment, generating triangle pixels includes scan converting the triangles for which the pixels are to be generated.
The color data are based on textures stored in an associated texture memory according to one embodiment.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Embodiments of a triangle identification buffer are described herein. In the following description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In
The CSP 13 is in communication with the video card system memory (not shown) via an on-board bus 14, and is also connected to a set of programmable Vertex Processing units (VPUs) 15 which are themselves connected to the bus 14 to enable access to the video card and system memory.
The CSP 13 controls the VPU processors 15 on the basis of instructions from the host computer (as described later in relation to
One of the VPU processors 15 will now be described in more detail with reference to
With reference to
The tile processor provides an output to a depth raster fetch unit 102 which is arranged to request a triangle for processing. This depth information is provided to a depth raster unit 103 which is arranged to rasterize only the depth value for a given triangle.
The output of the depth raster unit 103 is input to a depth stencil unit 104 which is connected to a depth stencil buffer 105. The depth stencil unit and buffer are arranged to check whether the depth and stencil test passes and updates the depth and stencil buffers accordingly.
The output of the depth stencil unit is input to triangulation information buffer TIB write unit 106. This unit 106 is arranged for those pixels in the triangle which survive the depth and stencil test, to write the corresponding identifiers to the identification buffer 117. The ID buffer is connected to a first buffer 118 and a second buffer 119.
The output of the tile processor 100 is also input to a color raster fetch unit 107 which is arranged to fetch a triangle from the triangle buffer with an identifier that is valid in the identification buffer. For this reason there is a associative look up connection to the identification buffer 117.
The output of the color raster fetch unit 107 is provided to a color raster unit 111 which is arranged to rasterise only the color value (diffuse and specular) for each surviving triangle. The output of the color raster unit 111 is input to a depth stencil unit 112 which is connected to a depth stencil buffer 113. The depth stencil unit 112 and depth stencil buffer 113 provide the same function as the depth stencil unit 104 and depth stencil buffer 105 described previously.
The output of the depth stencil unit 112 is connected to a triangulation information buffer test unit 114 which is arranged so that if the color rasterized pixel passes the identifier test (ie the triangle identifier—that is the identifier in the triangle identifier buffer at that pixel position), then the pixel is passed on to a pixel shader/texture unit 115 which is connected to a texture cache 116. The pixel shader/texture unit 115 is connected to a fog unit 120 which computes the fog value based on the the distance from the observer and applies to the texture mapped pixel. The output of the fog unit 120 is input to a blending unit 121 which provides a blending operation. The output of the blending unit 120 is input to a color buffer 122 the output of which is connected to a write back unit 123. The output of the write back unit 123 is fed back to the texture cache 116.
Initially, triangles are set up for scan conversion. This is shown in more detail in
(X1, Y1, Z1, R1, G1, B1, A1, U11 V11, . . . , Un1,Vn1) (1)
(X2, Y2, Z2, R2, G2, B2, A2, U12 V12, . . . , Un2,Vn2) (2)
(X3, Y3, Z3, R3, G3, B3, A3, U13V13, . . . , Un3,Vn3) (3)
The values represented by the variables will be well understood by those skilled in the art of three-dimensional graphics. The tuplet information represents values of vertices of the triangle. By definition, this means that they lie in the plane of the triangle, so the triangle can be rasterized by interpolating the values at those vertices. Also, whilst only one set of color components (RGB) is defined in the above tuplets, it is common for two sets to be defined, one for diffuse lighting and the other for specular lighting.
As is shown in
In prior art methods, every pixel that passes the depth buffer test is plotted. This means that, unless the triangles are depth sorted and plotted from front to back, triangles that will not ultimately be visible will still be rasterized. Moreover, such triangles will also be texture mapped, which places an undesirable burden on memory bandwidth.
In accordance with one embodiment, this “overdraw” problem is ameliorated by making a depth assessment of each pixel prior to full rendering. In this way, only those triangles that will actually be visible in the final image will actually go through the relatively bandwidth-hungry rendering stages. It will be appreciated by those skilled in the art that this has the added advantage of speeding up subsequent anti-aliasing procedures.
In an embodiment, this result is achieved by allocating a relatively unique identifier to each triangle to be rendered. By “relatively unique”, it is meant that each triangle is uniquely identified with respect to all other triangles that define the three dimensional components of a particular tile or frame being rendered. For example, a triangle that appears in consecutive frames or adjacent tiles may well be allocated a different identifier in each of those frames.
Referring to
Prior to the steps of
In step 409, a comparison is made between the depth value of the current pixel and that representing the corresponding pixel location in the depth-buffer. If the pixel already at that position in the color buffer has a depth greater than that of the value at the corresponding position in the depth buffer, then the identifier for the triangle being compared is written into the triangle identification buffer and the depth overwritten into that position in the depth buffer.
For the first triangle being scanned, the contents of the identification buffer and the depth-buffer are shown in
Each of the pixel locations corresponding to the pixels generated in relation to the first triangle 702 contains the value of the unique identifier originally allocated to the triangle (in this case, the digit “1”). Each corresponding pixel location in the depth-buffer has stored within it a z-value associated with that pixel.
For subsequent triangles being scanned, the depth value of the current pixel being scanned is compared to the depth value stored in the pixel location in the depth-buffer corresponding to that of the triangle. It will be appreciated that, if the corresponding pixel location has not yet had triangle data written to it, the pixel presently being considered will by definition be visible in the event that no further triangles have pixels at that location. The unique identifier associated with the current triangle will then be written directly to the corresponding pixel location to replace the default value.
The contents of the triangle identifier buffer after a second triangle 800 has been written to it is shown in
Steps 401 to 410 are repeated until all triangles for the frame or tile being rendered have been processed. In the present example, only the two triangles need to be rendered, so the resultant triangle identifier buffer state is that shown in
At this stage, the final rendering procedure shown in the flowchart 500 of
Further steps are then undertaken in accordance with steps 502 to 505, which are known to those skilled in the art and therefore not described in detail. Once step 507 is reached, however, things proceed differently from the procedure of
It will be noted from
Once all pixels have been scanned and texture/color mapped, other processing, such as anti-aliasing, can be applied in accordance with known procedures. The resultant frame, representing a two-dimensional view of the three dimensional representations, is output to a display device such as a computer monitor.
Other architectures and approaches can be used in conjunction with the invention. For example, it will be appreciated that the invention is amenable to use with different triangle plotting schemes, such as strips or fans. Also, the method can be applied to entire frames, or sub-frames in the form of tiles, depending upon the desired implementation. It will be appreciated that additional steps may be required in some cases to, for example, convert polygons (generated during tiling or due to framing considerations) into triangles, but this is well known within the art and so has not been described further herein.
In one form, the invention is embodied in a specialist graphics processor on a graphics accelerator card. Such cards are used as components in personal and business computers, such as an IBM compatible PC 600 shown in
It will be seen from the detailed description that an embodiment of the present invention provides a method of rendering polygons from a three-dimensional to a two-dimensional space, whilst reducing overall texture bandwidth requirements.
All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention and can be made without deviating from the spirit and scope of the invention.
These and other modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Number | Date | Country | Kind |
---|---|---|---|
01309059.2 | Oct 2001 | EP | regional |
Number | Date | Country | |
---|---|---|---|
Parent | 10279091 | Oct 2002 | US |
Child | 10445295 | May 2003 | US |