Claims
- 1. An operational amplifier bias system that provides input offset voltage trim current to an operational amplifier with minimum offset thermal drift, the bias system comprising:
- a bias generator that provides bias generator current to the operational amplifier; and
- correction circuitry connected to receive the bias generator current and to provide an input offset trim current to the operation amplifier that compensates for offset drift error of the input offset voltage of the operational amplifier with change in temperature, the correction circuitry including a resistive element, an input current mirror connected to receive the bias generator current and to provide a reference current to the resistive element, the resistive element responding to the reference current by providing a temperature coefficient conversion current having a predetermined temperature coefficient, and voltage reference circuitry connected to provide a voltage reference signal that sets the resistance of the resistive element.
- 2. An operation amplifier bias system as in claim 1 wherein the resistive element comprises a linear resistive element.
- 3. An operational amplifier bias system as in claim 1 wherein the resistive element comprises an active resistor.
- 4. An operational amplifier bias systems as in claim 3 wherein the active resistor comprises a MOSFET device biased for operation in the triode region.
- 5. A method of providing input offset voltage trim current to an operational amplifier, the method comprising:
- providing a bias current to the operational amplifier;
- utilizing the bias current to reflect a reference voltage to a resistive element to provide a temperature coefficient conversion current having a predetermined temperature coefficient; and
- utilizing the temperature coefficient conversion current to generate the input offset voltage trim current.
- 6. An operational amplifier bias circuit for providing temperature compensated trim current to a CMOS operational amplifier to compensate for input offset voltage, the circuit comprising:
- a first current mirror that includes a first diode-connected N-channel mirror transistor and a second N-channel mirror transistor, the gate of the first mirror transistor being connected to the gate of the second mirror transistor;
- a diode-connected N-channel threshold voltage reference transistor operable in the subthreshold range and having its drain connected to the source of the first mirror transistor and its source connected to a negative supply; and
- an N-channel resistive transistor, operable in the triode mode, and having its drain connected to the source of the second mirror transistor, its source connected to the negative supply, and its gate connected to the commonly connected gates of the first and second mirror transistors.
- 7. An operational amplifier bias circuit for providing temperature compensated trim current to a CMOS operational amplifier to compensate for input offset voltage, the circuit comprising a first current mirror that includes a first diode-connected N-channel mirror transistor and a second N-channel mirror transistor, the second mirror transistor being operable in the subthreshold range;
- a diode-connected N-channel threshold voltage reference transistor having its drain connected to the source of the first mirror transistor, its source connected to a negative supply, and its gate connected to the gate of the second mirror transistor; and
- an N-channel resistive transistor, operable in the triode mode, and having its drain connected to the source of the second mirror transistor, its source connected to the negative supply, and its gate connected to the gate of the first mirror transistor.
RELATED APPLICATIONS
The present application is a continuation-in-part of prior commonly-assigned application Ser. No. 07/794,960 filed Nov. 20, 1991 now U.S. Pat. No. 5,200,654.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0140677 |
May 1985 |
EPX |
Non-Patent Literature Citations (1)
Entry |
J. Haspeslagh and W. Sansen, "Design Techniques for Fully Differential Amplifiers", IEEE 1988 Custom Integrated Circuits Conference, May 16, 1988, pp. 1221-1224. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
794960 |
Nov 1991 |
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