Patent Application
20060049912
The invention relates to the noise performance and long-term stability of trimmable polysilicon resistors. More specifically, it relates to improving the noise performance by increasing an area of polysilicon resistor on a thermally isolated microstructure.
When analog electronic circuits and systems are calibrated to very high precision, many forms of fine variability become significant. Subtle parasitic effects can degrade the performance of a finely tuned circuit or system. One very important type of parasitic effect is electrical noise phenomena. Another important type of parasitic effect is long-term instability.
Electrical noise is a significant issue in the design and performance of high-precision circuits. Signal-to-noise ratio is of fundamental importance in any circuit involving amplification, including Wheatstone bridges and many sensors and sensor-based systems.
Electrical noise in resistors made of polycrystalline materials has been shown to be roughly dependent on the number of grains in the body of the resistor (M. J. Deen, S. Rumyantsev, J. Orchard-Webb, “Low-Frequency Noise in Heavily-Doped Polysilicon Thin Film Resistors”, Journal of Vacuum Science and Technology B, 16(4) July/August 1998 p.1881-1884; R. Brederlow, W. Weber, C. Dahl, D. Schmidt-Landsiedel, R Thewes, “Low-Frequency Noise of Integrated Poly-Silicon Resistors”, IEEE Trans. Electron Devices, 48(6), June 2001, p.1180-1187; R. Thewes et al, “Explanation and Quantitative Model for the Matching Behavior of Poly-Silicon Resistors”, Proceedings of the 1998 International Electron Devices Meeting, pp. 28.7.1-28.7.4, and other publications). It is known that the noise is inversely proportional to the volume of the resistor.
Moreover, it is known (N. N. Tkachenko, “1/f Noise Transformation that Accompanies the Trimming of Polycrystalline Silicon Layers”, Solid State Phenomena, Vols. 51-52 (1996), pp.391-396), that the process of pulsed trimming of polysilicon resistors can affect their electrical noise (either reducing or increasing the noise, depending on some conditions). In general, it is known that thermal trimming of polysilicon involves changes at the grain boundaries. Feldbaumer and Babcock (1995) found that trimming polysilicon reduced the average grain size of the polysilicon, which can be seen as potentially favorable for systematic reduction of noise by thermal trimming.
Long-term drift of electronic component values over time is a substantial problem in the electronics industry. It is known that mechanical stress (e.g. introduced during packaging, or other operations), may adversely affect the long-term stability of electronic components (such as resistors, diodes, FET's, and larger circuits). It is also known that trimming is associated with high temperatures (e.g. 700° C.), which may locally alter the stresses in surface layers adherent to a rigid substrate, such as in a typical silicon integrated circuit. Kato et al (K. Kato, T. Ono, Y. Amemiya, A Monolithic 14 Bit D/A Converter Fabricated with a New Trimming Technique (DOT) IEEE J. Solid-State Circuits vol. SC-19 (1984), 5, pp.802-807) found that trimming of polysilicon resistors embedded in surface films on a substrate led to increase in instability, which could be reduced by using the proposed ETR technique to anneal the resistor. In general, lower mechanical stress should lead to better long-term stability of electronic components and circuits.
Thus, if it is desired to make a resistor for a high-performance analog system, which is simultaneously high-precision trimmable, and possessing low noise characteristics, one must use a physical resistor element taking considerable area on the chip. If such a large-area resistor were simply placed on the surface of a silicon chip, even if isolated by typical insulating films, the thermal isolation from the substrate would still not be very high. It would require considerable applied power to raise the temperature high enough to accomplish trimming, raising a variety of problems impacting the practicality of the technique. Indeed, it should be noted in the prior art of trimmable polysilicon resistors (e.g. Dallas Semiconductor patent application #6306718), that the tested trimmable resistors are very small, likely in order to limit the power needed to accomplish trimming. This entrains great difficulty in creating practically manufacturable low-noise trimmable resistors.
Therefore, there is a need for trimmable resistors to have low-noise properties.
Accordingly, an object of the present invention is to provide high-precision adjustability simultaneously with low-noise performance, suitable for use in high-performance analog systems including sensors and sensor-based systems.
According to a first broad aspect of the present invention, there is provided a circuit having favorable noise performance, the circuit comprising: a thermally isolated micro-platform on a substrate; and a thermally mutable component on the thermally isolated micro-platform taking up a majority of an area of said micro-platform.
According to a second broad aspect of the present invention, there is provided a method for providing a circuit including at least one trimmable electronic component having low noise performance, the method comprising: providing a thermally isolated micro-platform on a substrate; and placing the trimmable electronic component on the thermally isolated micro-platform such that the component covers a majority of an area of the micro-platform.
Preferably, the total area of a single thermally-trimmable component is greater than 10000 μm2, disposed on a single micro-platform or on a plurality of micro-platforms. Also, the component is disposed on one or more polysilicon layers in a given micro-platform.
According to a third broad aspect of the present invention, there is provided a circuit having favorable noise performance, the circuit comprising: a thermally isolated micro-platform on a substrate; and a thermally mutable component embedded in said thermally-isolated micro-platform and composed of a plurality of superimposed layers, whereby a large effective area of said component reduces noise.
According to a fourth broad aspect of the present invention, there is provided a method for providing a circuit having low noise performance, the method comprising: providing a thermally isolated micro-platform on a substrate; and embedding a thermally mutable electrical component composed of a plurality of superimposed layers in said thermally-isolated micro-platform, whereby a large effective area of said component reduces noise.
According to a fifth broad aspect of the present invention, there is provided a method for designing a circuit having a plurality of thermally mutable electrical components having different power dissipation and noise tolerance requirements, the method comprising: identifying a desired value for said noise tolerance and said power dissipation for each of said plurality of components; selecting a parameter value for each of said plurality of components; and selecting a dimension for each of said plurality of components as a function of said power dissipation and noise tolerance requirements to yield a trimmable range including said parameter value.
According to a sixth broad aspect of the present invention, there is provided a circuit comprising a plurality of thermally mutable electrical components having different power dissipation and noise tolerance requirements, characterized in that a dimension for each of said plurality of components is set as a function of said power dissipation and noise tolerance requirements to yield a trimmable range including a desired parameter value.
In the case that the components are resistors and the trimmable components are used in a low voltage logic circuit, power dissipation is typically very low and power dissipation considerations will have minimal or negligible impact on the specifications of the dimensions of the component. In the case of analog circuitry operating at higher current and/or voltage levels in which power dissipation must be accounted for, it will be appreciated that this factor will partly determine component dimensions. In the case that a trimmable resistor is provided on a micro-platform, one must also take into consideration that the micro-platform is a highly insulated environment and even smaller power dissipation can have appreciable effects. It will be appreciated that in the present invention, trimmable resistors or other component are preferably provided on micro-platforms for ease of trimming, however, it is contemplated that such components may also be provided directly in the substrate of an integrated circuit or any other suitable packaging.
In this patent application, the term “thermally-mutable material” is intended to mean a material that behaves like a polycrystalline semiconductor material having electrical and/or other material properties that can be reversibly changed within a certain range by restructuring of the “grains” making up the material and/or grain boundaries, and/or spatial distribution of dopants within the grains, and/or grain boundaries. Once a change to the property is effected, it remains essentially stable for the purposes of subsequent operation. Such restructuring can be achieved by thermal cycling and/or by physical stimulation such as application of pressure, etc. in the present state of the art, polycrystalline silicon (polysilicon) and polycrystalline silicon-germanium are known to be thermally-mutable materials. While the making of resistors from polysilicon is the most common application, it is known to make a resonator from polysilicon, in which the resonant frequency of the resonator is trimmable due to changes in its mechanical properties.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description and accompanying drawings wherein:
It should be noted that for the purpose of this disclosure, trimming is to be understood as increasing or decreasing the room-temperature resistance value of a resistor. It should also be noted that thermally-isolated is meant to describe an element that is isolated from other elements such that the heat flux (proportional to temperature differential) generated between the element and other elements, is generally low. Electrically-isolated is meant to describe an element that is isolated from other elements such that the resistance between this element and other elements is very high (e.g. hundreds of k-ohms). The term signal is meant to describe any data or control signal, whether it be an electric current, a light pulse, or any equivalent. Furthermore, obtaining a constant or flat temperature distribution, T(x), is equivalent to a relatively flat or substantially constant temperature distribution across a resistor. The entire resistance cannot be at the same temperature since a portion of the resistor must be off the micro-platform (due to the continuous nature of resistors) and electrical contacts must be at a lower temperature. Therefore, obtaining a substantially constant temperature distribution across a resistor is understood to mean across a reasonable maximum possible fraction of the resistor. A pulse is to be understood as a short duration of current flow.
The possibility of reducing the noise by trimming supports the potential advantages of using trimmable polycrystalline materials, such as polysilicon, as resistors in high-performance circuits.
In the design of integrated circuits, it is often important to obtain favorable low noise performance, within certain design and process constraints. Some typical constraints for design of an integrated resistor are:
If, in addition to these constraints it is desired that the resistor be thermally trimmable (typically involving local temperatures on the order of 500° C. and above), this is problematic, since for low noise one should use as large an area as possible. If the physical resistor is placed directly on top of the substrate, separated only by thin insulator layer(s), the power required for heating increases proportionally to the area of the resistor, which is prohibitive/problematic for practical high-volume manufacturing (due to heat distribution and layout problems). On the other hand if the large-area resistor is placed on one or more micro-platforms, there are significant advantages. The overall thermal isolation is much better, and furthermore the power required to heat the structure does not rise proportionally to the area of the resistor. The required power will rise inversely with the thermal isolation, which is dominated by the support arms, which do not need to change dramatically as the resistor area increases.
Thus, this invention proposes, as a solution, to place the large-area resistor on a micro-platform having good thermal isolation and low thermal inertia. It can be heated by a separate heater (as shown in
In a preferred embodiment, standard micro-fabrication technology such as CMOS (or BiCMOS, or others), is used to fabricate resistive and dielectric layers to form the cantilever. It is well-known that such dielectric layers as silicon oxide and silicon nitride have low thermal conductivity. Therefore high thermal isolation (approximately 20-50° K./mW) can be achieved for the type of microstructure described here.
Resistors R1 and R1h can be made, for example, from polysilicon having sheet resistance of 20-100 Ω/square, which is typical for CMOS technology. Polysilicon resistors can be thermally trimmed by heating them up to temperature higher than a certain threshold Tth, such as Tth≅500° C.
A polysilicon resistor having resistance of 10 kΩ (for example) can be readily fabricated in an area of approximately 30 μm×30 μm, if a technological process having 1 μm resolution is used. For a 0.8 μm or 0.35 μm or smaller-feature-sized process, the size of the resistor can be significantly smaller. Therefore all four resistors, two functional with resistance of, for example, 10 kΩ each, and two auxiliary, with preferably lower resistance such as approximately 1 kΩ, can be fabricated on the thermally isolated area 2 with typical area in an approximate range of 500 μm2-20,000 μm2, e.g. 50 μm×100 μm. This size is reasonable for many possible applications, and releasing of the whole structure can be done by well-known micro-machining techniques, for example chemical etching in an isotropic etching solution(s), or isotropic dry silicon etch techniques.
Since the resistor is to be heated during trimming, it needs to have a relatively constant spatial temperature distribution T(x) in order to obtain good trimming performance,. Thus, the resistor layout should be designed with this in mind. Some examples of layouts designed to obtain a relatively flat T(x) are shown in
However, the area of a micro-platform cannot be increased indefinitely, due to constraints of mechanical stress in the films composing the micro-platform, and the length of time required to etch the cavity underneath. Thus, it is further preferred to use as much of the micro-platform area as possible to house the resistor. In this invention, at least 70% of the area of the micro-platform is used for the resistor, the rest of it being reserved for heating element or elements, and surrounding insulators. Schematic top views of micro-platforms filling substantial fractions of the available area are shown in
In order to maximize the area for the functional resistor, several additional techniques can be used.
The need for flat T(x) is particularly important in the case where the resistor should take a large area. Accordingly,
Of course, it is also possible to use several micro-platforms, positioned over one or more cavities, in order to increase the amount of area for the resistor. This has the advantage of not requiring a long cavity etch, and reducing mechanical difficulties associated with large micro-platforms.
In a preferred embodiment, a single thermally-trimmable polysilicon resistor having a total area greater than 10000 μm2 is disposed on one or more micro-platforms.
The resistor may be embedded in a micro-platform, whose relative flexibility (compared to embedded in films adherent to a rigid substrate), allows bending to accommodate mechanical stresses. Placing the trimmable electronic circuit element on a micro-platform allows one to apply larger heat treatments with less potential for stress-induced damage. Of course, the micro-platform needs to be properly designed for stress accommodation.
Such low-noise trimmable resistor(s) may be used advantageously in a circuit whose performance is dependent on low-noise performance of said resistor. For example, a low-noise amplifier can benefit from adjustability of offset and gain using such low-noise adjustable resistors. In general, many analog circuits involving amplification depend on high signal-to-noise ratio (SNR), and thus the noise performance of the components comprising the circuit is critical. In a Wheatstone bridge structure with a sensor, the noise of the resistors in the Wheatstone bridge limits the SNR and stability of the entire sensor and sensor-based system. For example, a typical important limiting factor in a bolometer or thermo-anemometer is the thermal noise of an ideal or near-ideal resistor. This invention allows such components to be adjustable without degrading the overall performance of the circuit.
It will be understood that numerous modifications thereto will appear to those skilled in the art. Accordingly, the above description and accompanying drawings should be taken as illustrative of the invention and not in a limiting sense. It will further be understood that it is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features herein before set forth, and as follows in the scope of the appended claims.
This application is a continuation of international application number PCT/CA2004/000399, which claims priority under 35USC§119(e) of U.S. provisional patent application No. 60/455886 and is related to PCT patent application entitled “Bi-Directional Thermal Trimming of Electrical Resistance” having international publication number WO2004/097859 and PCT patent application entitled “Trimming Temperature Coefficients of Electronic Components and Circuits” having international publication number WO2004/097860, both filed on Mar. 19, 2004, which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CA04/00399 | Mar 2004 | US |
| Child | 11229565 | Sep 2005 | US |
