Patent Application
20060109156
This invention relates to analog-to-digital converters (ADCs), and to trimming a resistance ladder which can form part of an ADC.
ADCs in integrated circuits are well known. For example, in the book “Introduction To CMOS Op-Amps And Comparators” by R. Gregorian, John Wiley & Sons, 1999, chapter 7 at pages 255-302, which is hereby incorporated herein by reference, describes various forms and characteristics of known ADCs. Various ones of these use a resistance ladder which is supplied with a reference voltage to provide a plurality of voltages for comparison purposes in the ADC process.
By way of example, one application of an ADC is for power management and supervision functions in switch mode power supplies (SMPSs) or dc/dc converters. In such an application it may be desired to measure an SMPS output voltage accurately and to convert it to a digital value, for example with an absolute accuracy of about 0.1%, requiring a 10-bit ADC.
For example, a coarse-fine successive approximation ADC, similar to those described in the above reference, can be provided using a resistance ladder for the first or coarse stage and a capacitance ladder for the second or fine stage.
Modern CMOS integrated circuits generally provide good enough resistance and capacitance matching that 10-bit performance can be achieved without trimming, at least in terms of DNL (differential nonlinearity level) and INL (integral nonlinearity level). However, it is difficult to obtain the required absolute performance because of non-idealities that create offset and gain errors. Although some applications of ADCs are tolerant of such errors, the application of an ADC referred to above is like a digital voltmeter, and requires the absolute accuracy.
Accordingly, obtaining the desired 0.1% absolute accuracy requires auto-calibration or factory-calibration to remove offset and gain errors. Factory trim or calibration is common in the industry, using switching in or out of resistors or capacitors in discrete steps.
It can be desirable to operate an ADC from a single, e.g. positive, supply rail to convert positive voltages within an ADC range that extends down to ground or 0V. However, offset trim in the region of 0V is difficult because it requires small negative voltages as well as small positive voltages. This difficulty can be avoided, at least in the application of the ADC referred to above, by not carrying out conversions all the way to ground (0V). The ADC instead can have a zero digital code output that corresponds to a small positive voltage, for example about 100 mV, constituting the low end of the ADC range. However, this also undesirably changes the full-scale range of the ADC. Thus gain and offset trimming are not independent of one another, and calibration of the ADC can become complicated and/or inconvenient.
The invention facilitates providing a method and ADC arrangements which can avoid or reduce this disadvantage.
According to one aspect, this invention provides a circuit including a resistance ladder comprising a plurality of resistors connected in series between first and second adjustable resistances via which a voltage difference is supplied to the resistance ladder, so that taps of the resistance ladder provide respective voltage levels over a voltage range, and a control circuit for making substantially equal and opposite changes to the first and second adjustable resistances to shift the voltage range without changing a magnitude of the voltage range.
In particular, the circuit can comprise an analog-to-digital converter (ADC) and the respective voltage levels provided by taps of the resistance ladder can constitute comparison voltage levels for the ADC. Typically said plurality of resistors of the resistance ladder have equal resistances.
Each of the first and second adjustable resistances can comprise a first resistor and a plurality of second resistors for connection selectively in parallel with the first resistor. This is particularly advantageous when the circuit is an integrated circuit.
Another aspect of the invention provides an analog-to-digital converter (ADC) comprising: a circuit for producing a reference voltage relative to a common voltage; a resistance ladder comprising a plurality of resistors connected in series between first and second adjustable resistances, the reference voltage and the common voltage being applied to the resistance ladder via the first and second adjustable resistances respectively, taps of the resistance ladder providing respective comparison voltage levels over a voltage range of the ADC; and a control circuit for making substantially equal and opposite resistance changes to the first and second adjustable resistances to shift the voltage range of the ADC without changing a magnitude of the voltage range.
The circuit for producing a reference voltage relative to a common voltage can comprise an amplifier for multiplying a voltage supplied to the amplifier in accordance with a gain of the amplifier determined by a resistance ratio.
A further aspect of the invention provides a method of trimming a resistance ladder, the resistance ladder comprising a plurality of resistors connected in series and having taps providing respective voltage levels over a voltage range in response to a voltage difference supplied to the resistance ladder, the method comprising the steps of: supplying a voltage difference to the resistance ladder via first and second adjustable resistances at first and second ends of the plurality of resistors connected in series; and making substantially equal and opposite changes to the first and second adjustable resistances to shift the voltage range without changing its magnitude.
Conveniently the step of making substantially equal and opposite changes to the first and second adjustable resistances is a step in fabricating an integrated circuit including the resistance ladder.
The method can also comprise the steps of producing the voltage difference using an amplifier having a gain determined by a resistance ratio, and adjusting a resistance of at least one resistor to control the resistance ratio thereby to determine the gain of the amplifier. The resistance ladder and amplifier can be parts of an analog-to-digital converter (ADC), and said steps of making substantially equal and opposite changes to the first and second adjustable resistances and adjusting the resistance of at least one resistor can comprise independent steps of adjusting offset and gain respectively of the ADC.
The invention will be further understood from the following description by way of example with reference to the accompanying drawings, in which:
Referring to the drawings,
More particularly, as shown in
By way of example, the resistance ladder 14 comprises a chain of 16 resistors of equal resistance, which divide a full-scale voltage range of the ADC into 16 consecutive sub-ranges or coarse voltage steps. In known manner the ADC, under the control of the control unit 22, performs a binary search algorithm to determine which of these sub-ranges or coarse steps includes a sampled value of the input voltage Vin; this determines the 4 most significant bits of the digital output, and selects the respective voltage sub-range to be supplied to the capacitance array 16.
In addition, in known manner the ADC, again under the control of the control unit 22, performs a successive approximation algorithm using the capacitance array 16, comparator 20, and SAR to determine the remaining 6 bits of the digital output. The ADC operation further includes offset compensation to compensate for offset of the comparator 20, and control of the switch 19 to select between a common (e.g. zero) voltage Vssa and an analog ground reference Agnd, in known manner.
The reference voltage Vref and the relative resistances within the resistance ladder 14 thus determine the value of the input voltage Vin that corresponds to a zero digital output, the voltage difference of the input voltage Vin that corresponds to a change by one of the digital output, referred to as 1 LSB (least significant bit), and the full-scale voltage range of the ADC.
The amplifier 10 has its non-inverting input supplied with a precise and stable voltage Vbg, for example from a bandgap voltage source (not shown), and its inverting input connected via the resistor 11 to the voltage Vssa and via the resistor 12 to the output of the amplifier 10. If R1 and R2 are the resistances of the resistors 11 and 12 respectively, then the reference voltage Vref is given by the equation:
Vref=(1+R2/R1)Vbg
and (1+R2/R1) is the gain of the amplifier 10.
Thus the reference voltage Vref is controlled by trimming the ratio R2/R1. This trimming can be carried out at the wafer or package level in known manner using selectable resistors and CMOS switches, and compensates for offset in the amplifier 10 or other downstream effects in the ADC that might make the LSB size non-ideal.
The ADC of
Thus if a measurement of the ADC performance determines that the zero digital code corresponds to a voltage that is offset positively or negatively from its nominal and designed value, then the bottom resistance 27 is adjusted to reduce or increase, respectively, this voltage so that it is closer to the nominal value.
In known arrangements this would also change the total resistance of the resistance ladder 14, and hence the full-scale range and the LSB size of the ADC, thereby impairing its absolute accuracy. Correction of these would entail a further adjustment of the reference voltage Vref by further trimming of the resistor ratio R2/R1, with these two interdependent trimming processes being repeated successively until a desired accuracy is achieved. Thus in known arrangements, which do not have an adjustable top resistance, the trimming for gain and offset are not independent of one another.
The ADC of
The description below refers to specific voltages and resistances to assist in providing a full understanding, and it will be appreciated that these specific values, and other specific values given herein, are provided purely by way of example and that the invention is not limited by these in any respect.
For example, it is assumed that the resistances R2 and R1 are trimmed to provide a value of the reference voltage Vref of 2.835V. The 16 (in this example) resistors 26 can each have a resistance of 3 kΩ, and the top and bottom resistances 27 and 28 can each have a nominal resistance of about 2576.5Ω to provide the ADC with a coarse voltage step size of 0.16V, a LSB size of 2.5 mV, and a full-scale range of 2.56 V extending from a low end or zero code voltage of 0.1375V to a high end or full-scale voltage of 2.6975V.
With such an ADC it may be desired for example to provide offset trim adjustments within a range of ±½ LSB in ±¼ LSB steps. Thus the offset trim voltage is one of five values: −1.25 mV (−½ LSB), −0.625 mV (−¼ LSB), 0, +0.625 mV (+ 1/4 LSB), and +1.25 mV (+½ LSB). The whole of the full-scale range of the ADC is moved up or down by this offset trim voltage, relative to the nominal low end or zero code voltage of 0.1375V, upon adjustment of the bottom and top resistances 27 and 28 under the control of the decoder 24.
With the values given above by way of example, the offset voltage adjustment step size of 0.625 mV corresponds to a resistance change of 11.76Ω of each of the bottom and top resistances 27 and 28 in opposite directions. This is not practical to achieve with series resistors in CMOS technology, for which a unit square of low frequency polysilicon has a resistance of the order of 65Ω. However, such small resistance steps can be provided by a parallel resistor arrangement, for example as described below with reference to
The bottom resistance 27, between the voltages Vssa and Vbot, is illustrated in
For example, the resistors 32 to 36 can have resistances of 4 kΩ, 4.8 kΩ, 6 kΩ, 8 kΩ, and 11.1 kΩ respectively, so that in parallel with the 600 Ω resistor 31 they produce resistance values of about 521.7Ω, 533.3Ω, 545.5Ω, 558.1Ω, and 569.2Ω respectively. These resistance values are stepped with differences of about 11.76Ω, as required for voltage shift steps of about 0.625 mV or one quarter LSB as described above. Conversely, the resistors 42 to 46 can have resistances of 11.1 kΩ, 8 kΩ, 6 kΩ, 4.8 kΩ, and 4 kΩ respectively, so that in parallel with the 600Ω resistor 41 they produce resistance values of about 569.2Ω, 558.1Ω, 545.5Ω, 533.3Ω, and 521.7Ω respectively. Thus the resistors 42 to 46 are in a sequence reverse to that of the resistors 32 to 36.
As illustrated by way of example in
By way of example, the offset trim decoder 24 can provide the following decoding of the 3-bit OFST signal for respective offset adjustments:
For example, it may be determined that it is necessary to make a +½ LSB adjustment in order to cancel a −½ LSB of ADC offset. This means that it is necessary to shift the voltage Vbot up by ½ LSB, or about 23.5 mV. This is effected by the offset trim decoder 24 controlling the switches 38 to connect the 11.1 kΩ resistor 36 in parallel with the 600Ω resistor 31. At the same time, the offset trim decoder controls the switches 48 to connect the 4 kΩ resistor 46 in parallel with the 600Ω resistor 41, so that the full-scale voltage range of the ADC is maintained substantially constant by increasing the voltage Vtop by ½ LSB.
If required, digital offset cancellation techniques can also be used to provide +/−one LSB voltage shifts in known manner.
The parallel resistor trimming described above requires increased area and increases parasitic capacitor loading of the output of the amplifier 10 providing the ADC voltage reference Vref. These increases can be minimized by optimum selection of the arrangement and switching of the resistors constituting the bottom and top resistances 27 and 28. In other embodiments of the invention, the resistors 30 and 40 can have resistances different from one another, and either or both of them can be omitted. Further, a different trimmable resistor arrangement can be provided for each of the bottom and top resistances 27 and 28, as may be desired. For example, resistors can be provided in series and/or parallel, and can be switched individually or in combinations to provide the desired resistance trimming. However, a parallel arrangement such as that of
It can be appreciated from the above description that embodiments of the invention simplify the calibration or trimming of the ADC by making the offset trim independent of the gain trim, this being achieved by equal and opposite trimming of two resistances at opposite ends of the resistance ladder. Thus one resistance is increased and the other resistance is decreased so that a total resistance of the resistance ladder remains substantially constant, and hence offset trimming does not change the LSB voltage or the full-scale range of the ADC.
Although the invention is described above in the context of a particular form of ADC, it can be appreciated that it may be applied to other forms of ADC or to any other circuit that uses a resistance ladder to provide a plurality of voltages. For example, such other forms of ADC may include a Flash ADC, and such other circuit may include a digital-to-analog converter (DAC).
Thus although particular forms and details of an ADC are described above, it should be appreciated that these are given by way of example only, that the invention is not limited to these, and that numerous modifications, variations, and adaptations may be made without departing from the scope of the invention as defined in the claims.
This application claims the benefit of U.S. Provisional Application No. 60/628,947 filed Nov. 19, 2004, the entire contents and disclosure of which are hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60628947 | Nov 2004 | US |
