The present invention relates to switching regulators, and in particular, to systems and methods using truncated ramps in a switching regulator.
Switching regulators are used in a wide variety of electronic applications. One common application of a switching regulator is to generate a power supply voltage that supplies a regulated voltage to one or more integrated circuits (ICs).
Switching regulator 100 turns transistors Tn and Tp on and off in a controlled manner to transfer power from an input source (e.g., Vin) to the load and maintain a desired output voltage and/or current. Switching regulator 100 may sense Vout using voltage feedback circuit 121 and/or an output current using current feedback circuit 122. Controller 120 receives the voltage and/or current feedback signals and generates control signals HS and LS to turn transistors Tp and Tn on and off to maintain controlled output voltage or current.
Ramp signals are sometimes used in switching regulators to control the timing of control signals HS and LS.
Transient response is a term that describes a circuit's ability to respond to a change from steady state. In the context of switching regulators, transient response may refer to the switching regulators ability to respond to a fast change in the load current, for example. One problem with traditional switching regulators is related to the inability of typical controllers to respond to changes in the output between cycles of a ramp signal. For example, if the current into the load increases at 251 after the leading edge of triangle wave 210 crosses error signal 211, the system may not be able to respond until the next cycle of the triangle wave (e.g., at 252). As illustrated in
The present disclosure includes systems and methods that include truncated ramp in a switching regulator. In one embodiment, the present disclosure includes a circuit comprising a first switching transistor having an input terminal to receive an input voltage and an output terminal coupled to an output node, a truncated ramp generator to produce a truncated ramp signal comprising a ramp component and a constant component, a comparator to receive the truncated ramp signal and a first signal, and in accordance therewith, produce a modulation signal, wherein the first signal is based on an output voltage or an output current, and wherein the first signal intersects the constant component of the truncated ramp signal in response to a change in the output voltage or output current, and in accordance therewith, the first switching transistor changes state.
In one embodiment, the first signal is an error signal, the circuit further comprising an error amplifier having an input coupled to the output node to produce the error signal and an output coupled to an input of the comparator.
In one embodiment, the error amplifier is configured with a bandwidth so that the error signal intersects the constant component after an intersection of the error signal and the ramp component.
In one embodiment, the truncated ramp generator comprises a ramp generator to produce a ramp signal and a sample and hold circuit to receive the ramp signal and produce the truncated ramp signal.
In one embodiment, the truncated ramp generator comprises a delay circuit having an input to receive a switching signal and an output to produce a delayed switching signal, wherein the delayed switching signal produces a transition from the ramp component to the constant component.
In one embodiment, the switching signal is the modulation signal.
In one embodiment, the delay circuit is programmable.
In one embodiment, truncated ramp generator comprises an amplifier having an input coupled to receive a ramp signal, a capacitor, and a variable impedance having a first terminal coupled to an output of the amplifier, a second terminal coupled to the capacitor, and at least one control terminal couple to receive the ramp signal, and wherein the variable impedance is in a low impedance state when the magnitude of the ramp signal is below a first value, and the variable impedance is in a high impedance state when the magnitude of the ramp waveform is above the first value.
In one embodiment, the ramp truncation circuit comprises a comparator having an input coupled to receive a ramp signal, a switch having a control terminal coupled to an output of the comparator and an input terminal coupled to receive the ramp signal, and a capacitor coupled to a second terminal of the switch.
In one embodiment, the truncated ramp signal further comprises a second constant component.
In one embodiment, the truncated ramp signal further comprises a step.
In one embodiment, the constant component sets a minimum value of the truncated ramp signal.
In one embodiment, the constant component sets a maximum value of the truncated ramp signal.
In one embodiment, the truncated ramp signal is a truncated triangle waveform.
In one embodiment, the truncated ramp signal is a truncated sawtooth waveform.
In one embodiment, the constant component is programmable.
In one embodiment, the truncated ramp generator switches from a non-truncated ramp signal to a truncated ramp signal when a steady state output voltage is reached.
In one embodiment, the error signal increases in response to an increase in load current, and wherein the error signal intersects the constant component, and in accordance therewith, turns on the switching transistor to produce more current into the load.
In one embodiment, the error signal decreases in response to a decrease in load current, and wherein the error signal intersects the constant component, and in accordance therewith, turns off the switching transistor to reduce the current into the load.
In one embodiment, the present disclosure includes a method comprising receiving an input voltage on an input terminal of a first switching transistor, the switching transistor having an output terminal coupled to a output node, generating a truncated ramp signal having a ramp component and a constant component, and comparing the truncated ramp signal and a first signal, and in accordance therewith, produce a modulation signal, wherein the first signal is based on an output voltage or an output current, and wherein the first signal intersects the constant component of the truncated ramp signal in response to a change in the output voltage or output current, and in accordance therewith, the first switching transistor changes state.
In one embodiment, the first signal is an error signal, the method further comprising amplifying the output voltage in an error amplifier to produce the error signal, wherein the error amplifier is configured with a bandwidth so that the error signal intersects the constant component after an intersection of the error signal and the ramp component.
In one embodiment, generating a truncated ramp signal comprises generating a ramp signal and truncating the ramp signal at a particular value to produce the truncated ramp signal.
In one embodiment, the method further comprises switching from a non-truncated ramp signal to a truncated ramp signal when a steady state output voltage is reached.
The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present disclosure.
The present disclosure pertains to switching regulators. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
Drivers 301 and 302 turn Tp and Tn on and off. When Tp is on, Tn is off, and Vsw is equal to Vin. In this state, the ac voltage across the inductor is Vin-Vout, and the inductor current IL increases. For a buck converter architecture shown in this example, Vin is greater than Vout (Vin>Vout). When Tn is on, Tp is off, and Vsw is equal to ground. In this state, the ac voltage across the inductor is −Vout, and the inductor current IL decreases. The inductor current into the output load generates an output voltage Vout. In this example, feedback operates to maintain the output voltage at a predetermined voltage. In a voltage feedback case, a periodic (e.g., clock based) truncated ramp is compared against a signal related to the output voltage. In other embodiments, current may be used as a feedback parameter (e.g., current control mode) using a current sense circuit 320, for example. In this case, the truncated ramp is further based on an output current. Accordingly, embodiments of the disclosure may include switching regulators that sense output voltage, output current, or both.
In this example, output voltage Vout is used as feedback. A feedback circuit 322 (e.g., including a resistor divider) may receive Vout and produce a feedback signal Vfb to the input of error amplifier (ea) 311. Error amplifier 311 may also receive a reference (e.g., in this case a voltage, Vref) to produce an error signal Ve.
Embodiments of this disclosure include using a truncated ramp signal to generate control signals to drive Tp and Tn, for example. In this example, switching regulator 300 further includes a truncated ramp generator 321. Truncated ramp generator 321 generates a truncated ramp signal VTRamp that may be used in the feedback loop.
Graph 402 shows another truncated ramp signal 414 (VTRamp) comprising horizontal components 414a and 414b (i.e., steps). Introducing a step in the truncated ramp signal may improve noise immunity. In steady state, error signal 415 (Ve) crosses VTRamp at roughly the same point each cycle. In switching regulators using non-truncated ramps, noise may trigger a premature crossing, which may cause the system to switch multiple times (chatter) rather than only once. In this example, after the crossing point, step 414a in VTRamp reduces the likelihood that the system will experience unwanted multiple switching. The step may be introduced after the steady state turn and/or turn off points, for example.
In one embodiment, the switching regulator may switch from a non-truncated ramp signal as shown in graph 201 in
Referring again to
In one embodiment, truncated ramp generator 321 may include a delay circuit (not shown) having an input to receive a switching signal and an output to produce a delayed switching signal. The delayed switching signal may control a transition from the ramp component to the constant component of the truncated ramp signal. As illustrated by a specific example below, transitions of the PWM signal may be delayed and used to control truncation. In steady state, the intersection of the truncated ramp signal and a feedback signal, such as the error signal, may occur at approximately the same point in the ramp. Thus, a delayed version of the PWM signal, or another switching signal, may be used to establish an offset above or below the steady state intersection point so that large deviations in the output voltage or output current may be compensated quickly. In various embodiments, switching signals from switching nodes Vsw, PWM or nodes in the high side or low side driver paths or gate logic may be delayed to control truncation of the ramp, for example.
In one embodiment, the constant component of the truncated ramp is programmable. For instance, in some applications the intersection of the ramp with a feedback signal from the output may occur at approximately the same point in the ramp component each cycle during steady state. Accordingly, it may be desirable to configure the constant component above and/or below the intersection point to optimize response and noise performance. In some embodiments, the constant component level can be programmed. As described in an example below, a programmable delay may be used so that the transition from the ramp component to constant component may be adjusted according to the delay technique described above.
This example illustrates voltage feedback using feedback network circuit 520 that generates a voltage feedback signal Vfb. A first input of an error amplifier 521 receives Vfb and a second input of the error amplifier receives a reference voltage Vref. Error amplifier 521 produces an error signal Ve, which is coupled to an input of comparator 522. A second input of comparator 522 receives a truncated ramp signal. During steady state, Vfb is approximately equal to Vref, as shown in graph 601 in
In this example implementation, a truncated ramp signal is generated using ramp generator circuit 523 and a sample and hold circuit (S/H) 527. Ramp generator 523 may produce a ramp signal (untruncated). The ramp signal may be truncated using S/H 527. For instance, in one state, S/H 527 may pass the input ramp signal to the output. In another state, S/H 527 may sample and hold a particular value of the ramp signal. Thus, the output of S/H 527 may increase, following the ramp signal, to some value, and then remain at a constant value for some time period thereafter. An example truncated ramp signal VTRamp 612 generated by S/H 527 is illustrated in graph 602 in
As illustrated in graph 603, when PWM signal 614 is in a high state (e.g., when VTRamp is greater than Ve), low side switch Tn is on and Tp is off, and the current IL in inductor 552 decreases. Likewise, when PWM signal 614 is in a low state (e.g., when VTRamp is less than Ve), high side switch Tp is on and Tn is off, and the current IL in inductor 552 increases.
During steady state, deviations in Ve are typically small and the truncation of ramp 612 has little or no effect. However, if the current into the load suddenly increases, the feedback voltage Vfb may deviate substantially from Vref, as illustrated at 610-611, which causes Ve to increase as shown at 613a. As shown in graph 602, Ve intersects the constant component 612b of VTRamp at 652. When Ve increases above VTRamp, PWM signal 614 switches low, which turns Tp on causing the inductor current IL to increase. The duty cycle of PWM signal 614 is reduced as shown at 621, which causes Tp to turn on early. Thus, truncation effectively causes PWM signal 614 to respond faster to changes in the output and allow the system to quickly increase the inductor current in response to increases in load current, for example.
Truncation allows the system to respond faster to deviations in Vfb. Accordingly, particular embodiments may set the bandwidth of the feedback circuit 520 and error amplifier 521 to correspond with the truncation level used in the ramp waveform (e.g., the value of the constant component of the ramp). For example, typical error amplifiers may have a bandwidth corresponding to the full cycle of the ramp waveform. However, because truncation allows the system to respond faster to rapid deviations of the output current, for example, the feedback circuit 520 and error amplifier 521 may be configured with bandwidths sufficiently wide to allow Ve to move more quickly to intersect the constant component of the ramp in response to changes in the output of the switching regulator. Some applications may use resistor dividers for feedback circuit 520, but error amplifier 521 may be configured to produce an error signal that crosses the constant component 612b of ramp waveform 612 before the ramp is reset. For example, the error amplifier may be configured with a bandwidth so that the error signal crosses the constant component of the truncated ramp signal in response to a change in the load current after an intersection of the error signal and the ramp component and before a subsequent intersection. Accordingly, the bandwidth of the error amplifier may be greater than frequency of the ramp (the inverse of the ramp period) by a set value.
In one embodiment, the truncation level of the ramp is dynamic. For example, in one embodiment, the constant component 612b is generated as an offset from the intersection point 650 of VTRamp and Ve. Referring again to
The example shown in
A PWM signal is received by a delay circuit 1105. A logic circuit 1106 receives the delayed PWM signal and a transient control signal. The output of logic circuit 1106 is coupled to the SET input of an SR latch 1107. Logic circuit 1106 ensures that latch 1107 is not set during transients. Logic circuit 1106 may be an AND gate, for example. A RESET input of latch 1107 is coupled to receive CLK, and an output Q is coupled to a control input of switch 1108. Accordingly, a delayed PWM signal sets latch 1107 and closes switch 1108 to truncated the ramp signal from ramp generator 1101. In this example, CLK resets the ramp signal and opens the switch for the next cycle of the ramp.
The above description illustrates various embodiments of the present invention along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.