TTL compatible input buffer

Abstract

In general, a comparator compares the magnitude of a signal to a reference voltage, and changes its output when the latter exceeds the former. The invention concerns a reference voltage for the comparator. The reference voltage remains stable, even when the power supply voltage changes, thus keeping the switching point of the comparator constant. This constant switching point is useful in TTL logic circuits.

Description

The invention relates to input buffers for integrated circuits. In particular, the invention relates to input buffers which accommodate Transistor-Transistor Logic (TTL) levels, yet are constructed using Complementary Metal Oxide Semiconductor (CMOS) techniques.

BACKGROUND OF THE INVENTION

It is common to use a CMOS (Complementary Metal Oxide Semiconductor) inverter, such as that shown in FIG. 1, as a TTL (Transistor-Transistor Logic) input buffer. In the general case, if both transistors in FIG. 1a are sized correctly, the voltage characteristic of the inverter resembles that shown in FIG. 2. The switching point is halfway between zero and V.sub.DD, namely, at V.sub.DD /2.

If V.sub.DD changes (for example, from 5 volts to 10 volts), the switching point also changes, because the voltage characteristic changes, as indicated approximately by the phantom line 4. After the change, the switching point remains at the halfway point, at V.sub.DD /2, but its absolute value changes, from 2.5 volts to 5 volts in this example.

This change in absolute value can cause a problem when the inverter of FIG. 1a is used as an input buffer for TTL levels. For TTL levels, the transistors are constructed so that the switching point is at 1.4 volts when V.sub.DD equals 5 volts. If V.sub.DD changes, the switching point changes, as illustrated in FIG. 2. For small changes in V.sub.DD, the switching point remains close enough to 1.4 volts to be satisfactory. But if V.sub.DD changes by a large amount, such as from 5 to 10 volts as in the example above, the switching point deviates significantly from the normal TTL switching point of 1.4 volts.

Therefore, the switching point of this type of buffer is not independent of supply voltage.

OBJECTS OF THE INVENTION

It is an object of the invention to provide an improved input buffer.

It is a further object of the invention to provide an improved input buffer, in the form of an inverter which has a switching point which is relatively independent of supply voltage.

SUMMARY OF THE INVENTION

In one form of the invention, a V.sub.BE -multiplier provides the voltage reference to one differential input of a differential amplifier. The voltage reference is substantially independent of supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a-b illustrates prior-art CMOS input buffers.

FIG. 2 illustrates how the transfer characteristic of the buffers of FIGS 1a-b changes as supply voltage changes.

FIG. 3 illustrates one form of the invention.

FIG. 4 illustrates another form of the invention.

FIGS. 5 and 6 illustrate the apparatus of FIG. 3, but with the transistors replaced by switches in order to show the two different states of the apparatus.

FIG. 7 shows a V.sub.BE -multiplier, acting as bias for a class AB output stage.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 shows one form of the invention, and FIG. 4 shows a simplification which will be used for explanation. The difference between the figures stems from the fact that the components in box 10 in FIG. 3 form a "V.sub.BE -multiplier," as that term is known in the art. The particular V.sub.BE -multiplier in FIG. 3 is constructed such that the voltage drop from point 12 to V.sub.SS equals three diode drops. Accordingly, FIG. 4 replaces the V.sub.BE -multiplier with three diodes D1-D3.

V.sub.BE -multipliers will be discussed at the end of the Specification. "Diode drops" are referenced to V.sub.SS as zero. For example, point 12 in FIG. 4 is held at three diode drops: it is three diode drops above the voltage of V.sub.SS.

Two situations will be considered, namely, (1) when V.sub.IN is logic HIGH and (2) when V.sub.IN is logic LOW. The HIGH case will be considered first.

V.sub.IN is HIGH Q2 is ON, Q1 is OFF

In FIG. 4, Q1 and Q2 form a differential amplifier. The differential inputs are the respective base leads. The base of Q2 is held at three diode drops. For explanatory purposes, assume Q1 initially to be absent. V.sub.DD pulls the emitter E2 of Q2 HIGH, but no higher than one diode drop above the base (which is held at three drops), because the emitter-base junction of Q2 is a diode itself. Thus, with Q1 absent, V.sub.E2 is held at four diode drops, and Q2 is fully ON.

The situation is essentially the same if Q1 is present, but turned OFF. Q1 is OFF if V.sub.IN is at, for example, five diode drops. Such a voltage at V.sub.IN causes the base-emitter junction of

Q1 to be reverse-biased. Thus, with V.sub.IN at five diode drops, Q1 is OFF and Q2 is fully conducting.

The situation remains the same if V.sub.IN is lowered to four diode drops: the base-emitter junction of Q1 is at zero volts. Q1 is still OFF, and Q2 is still deep in conduction. The rest of the circuit will be considered in more detail, under these circumstances.

With Q2 ON, M1 is ON, M2 is OFF, M5 is OFF, V.sub.OUT is HIGH

Because Q2 is ON, input A to the differential amplifier contained within the dashed box 15 in FIG. 3 is pulled higher than input B, by one diode drop. That is, the gate of M1 (input A) is connected to the emitter E2 of Q2, and is presently pulled to four diode drops above V.sub.SS. Consequently, the difference between inputs A and B is one diode drop: A is at four drops and B is at three drops.

Thus, as shown in FIG. 5 M1 is ON and M2 is OFF. Because M2 is OFF, the gate to M5 is pulled HIGH (by M4), driving M5 OFF, pulling LOW the input to inverter INV. The output OUT is driven HIGH.

Thus, when V.sub.IN is HIGH, the output is HIGH.

V.sub.IN was assumed to be at four diode drops. If V.sub.IN is lowered further, a transition zone is approached. When V.sub.IN reaches 3 diode drops, both Q1 and Q2 have equal base voltages (3 drops each), and thus both Q1 and Q2 conduct equally. As V.sub.IN drops further, the roles of Q1 and Q2 become reversed. When V.sub.IN reaches two diode drops, the E-B junction of Q2 becomes reverse-biased, and Q2 turns OFF. At this time, the gate leads of M1 and M2 are approximately equal. As V.sub.IN is further lowered, M1 turns OFF and the output switches states. The new state will now be considered.

With Q2 OFF, M1 is OFF, M2 is ON, M5 is OFF, V.sub.OUT is LOW

Assume V.sub.IN has been lowered to zero volts. Now, the emitter E1 of Q1 can not exceed one diode drop (because the emitter-base junction is a diode itself). Since emitter E1 is connected to E2, the base-emitter junction of Q2 is reverse-biased (B2 is held at three diode drops), and Q2 is turned OFF, as shown in FIG. 6.

In addition, emitter E1 is connected to the gate of M1, pulling the gate to one diode drop above V.sub.IN (which is zero), which turns M1 OFF. However, the gate of M2 is held at three diode drops, so that M2 is ON. With M2 ON, the gate of M5 is pulled LOW, turning M5 ON, pulling HIGH the input to inverter INV, thereby driving the output OUT LOW.

Thus, when V.sub.ON is LOW, V.sub.OUT is LOW. The device of FIG. 3 is a non-inverting buffer. If inversion is desired, the output OUT can be inverted by a second inverter.

SIGNIFICANT FEATURES

1. As discussed above, input B is held at 3 diode drops above V.sub.SS. (One diode drop will be assumed to equal 0.7 volts.) When input A is at one diode drop above B (namely, at 2.8 or more volts above V.sub.SS), output, V.sub.OUT is HIGH. When input A is at one diode drop below B (namely, at or below 1.4 volts above V.sub.SS), V.sub.OUT is LOW. Therefore, the switching points for V.sub.IN are set at two and four diode drops, or about 1.4 and 2.8 volts. See Frederiksen, Intuitive Operational Amplifiers (McGraw-Hill 1988) ISBN 0-07-021966-4, page 13. This book is incorporated by reference.

2. These switching points of Q1 and Q2 were chosen for ease of illustration. In the more general case, these switching points are (V.sub.E3 +one diode drop) and (V.sub.E3 -one diode drop). Since the value of V.sub.E3 is determined by the values of R1 and R2, because of the V.sub.BE multiplier effect (discussed below), the switching points can be selected at will. If V.sub.E3 is set to 1.4 volts, the switching points are then set at (1.4+0.7, or 2.1 volts) and (1.4-0.7, or 0.9 volts).

3. A V.sub.BE -multiplier was discussed above. FIG. 7 shows such a multiplier. It is known that I.sub.R =V.sub.BE1 /R.sub.1. It is further known that V.sub.BB =I.sub.R (R.sub.1 +R.sub.2). Consequently, by substituting the former equation into the latter and factoring, V.sub.BB =V.sub.BE1 (1+R.sub.2 /R.sub.1). Thus, the circuit multiplies V.sub.BE1 by the quantity (1+R.sub.2 /R.sub.1). It is a "V.sub.BE -multiplier."

In FIG. 3, V.sub.EB of Q3 will equal one diode drop, because Q3 is biased heavily into conduction. Thus, the gate voltage will be held at three diode drops above V.sub.SS, because the quantity (1+R.sub.2 /R.sub.1) equals 3, because R.sub.2 is twice R.sub.1 in value. See Sedra and Smith, Microelectronic Circuits (Holt, Rhinehart & Winston 1987), ISBN 0-03-007328-6, pages 566-568. This book is incorporated by reference.

4. In contrast to the CMOS inverter of FIG. 1, the switching point does not change with supply voltage. For example, with the invention, if V.sub.DD in FIG. 3 changes from 5 volts to ten volts, the switching point will not change by more than about four percent. In contrast, with the prior-art CMOS inverter, the doubling of the supply voltage doubled the switching point.

The primary reason for the difference is the stability of the reference voltage in the invention. The reference voltage is that at the base of Q2. The reference voltage is supplied by the V.sub.BE -multiplier. The only term in the equation for the V.sub.BE -multiplier which could be affected by a rise in V.sub.DD is V.sub.EB of Q3. However, as an elementary knowledge of transistor operation shows, doubling of V.sub.DD does not significantly change V.sub.BE. (V.sub.BE will not change by more than about 3 percent if V.sub.DD doubles.) V.sub.BE can thus be termed substantially independent of changes in supply voltage, V.sub.DD.

5. Diodes can actually be used to implement the invention, as shown in FIG. 4, instead of the V.sub.BE multiplier.

6. The output stage, comprising M5 and the inverter INV in FIG. 3, is controlled by the switching state of M2. However, if the gate of M5 were connected to the drain of M1 instead of M2, the apparatus would be a non-inverting buffer, instead of the inverting buffer discussed above.

Numerous substitutions and modifications can be undertaken without departing from the true spirit and scope of the invention. What is desired to be secured by Letters Patent is the Invention as defined in the following claims.

Claims

1. An input buffer for an integrated circuit, comprising:

a) a first differential amplifier stage, comprising

i) a pair of bipolar junction transistors (Q1 and Q2) whose emitters are coupled together, and

ii) a first constant source (I1) in series with the emitters;

b) a second differential amplifier stage, comprising

i) a pair of field-effect transistors (M1 and M2) whose sources are coupled together,

ii) a second constant current source (I2) in series with the sources, and

iii) a connection between the gate of one of the field-effect transistors and the coupled emitters;

c) a V.sub.BE -multiplier, which provides a reference voltage to both the gate of the other of the field-effect transistors and one of the bipolar junction transistors; and

d) an output stage whose state is controlled by the state of either the one or the other field-effect transistors.