Claims
- 1. An input buffer, comprising:
- a first PMOS transistor having a drain terminal, a source terminal receiving a positive power supply voltage, and a gate terminal coupled to receive an input signal;
- means for receiving a reference voltage which is insensitive to supply voltage fluctuations and for providing on an output lead a control voltage in accordance with said reference voltage;
- a second PMOS transistor having a drain terminal, a source terminal connected to said drain terminal of said first PMOS transistor, and a gate terminal coupled to receive said control voltage; and
- an NMOS transistor having a drain terminal connected to said drain terminal of said second PMOS transistor, a gate terminal coupled to receive said input signal, said drain terminal of said NMOS transistor providing an output signal of said input buffer.
- 2. An input buffer as in claim 1, further comprising a resistor connected between said output lead of said means for receiving and said gate terminal of said second PMOS transistor.
- 3. A method for providing an input, buffer, comprising the steps of:
- providing a first PMOS transistor having a drain terminal, a source terminal receiving a positive power supply voltage, and a gate terminal coupled to receive an input signal;
- receiving a reference voltage which is insensitive to supply voltage variations and providing on an output lead a control voltage in accordance with said reference voltage;
- providing a second PMOS transistor having a drain terminal, a source terminal connected to said drain terminal of said first PMOS transistor, and a gate terminal coupled to receive said control voltage; and
- providing an NMOS transistor having a drain terminal connected to said drain terminal of said second PMOS transistor, a gate terminal coupled to receive said input signal, said drain terminal of said NMOS transistor providing an output signal of said input buffer.
- 4. A method as in claim 3, further comprising the step of providing a resistor connected between said output lead and said gate terminal of said second PMOS transistor.
- 5. An input buffer as in claim 1, further comprising a circuit coupling said gate terminal of said second PMOS transistor to a voltage fluctuation in a common ground voltage.
- 6. A method as in claim 3, further comprising the step of providing a circuit coupling said gate terminal of said second PMOS transistor to a voltage fluctuation in a common ground voltage.
- 7. An input buffer as in claim 1, wherein said reference voltage is independent of operating temperature.
- 8. A method as in claim 3, wherein said reference voltage is independent of operating temperature.
Parent Case Info
This application is a division of application Ser. No. 07/929,872, filed Aug. 11, 1992 now U.S. Pat. No. 5,376,843.
US Referenced Citations (7)
Divisions (1)
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Number |
Date |
Country |
Parent |
929872 |
Aug 1992 |
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