As systems, such as computer systems, continue to evolve, the systems operate at increasingly higher speeds. As operating speeds increase, it is generally desired that the timing control signals communicated within the system improve in accuracy. Clock signals, which are employed to synchronize signals are generally designed to reach a destination device or location at the same time. Accordingly, the propagation delay time (i.e., the time it takes for each clock signal to travel along the respective transmission line) is calculated to synchronize the arrival of the clock signals at the destination device or location. Delay lines are typically used to assist in timing the transmission of clock signals between two points without generally requiring a large amount of physical space within the system or circuit being designed.
Typical embedded delay lines are routed through the base material (e.g. fiberglass or other insulator) between two reference planes held in a constant potential, for example, at ground. In such situations, the waves or signals produced are generally transverse electromagnetic (TEM) waves and the propagation delay is generally constant along a delay line irregardless of the geometry or positioning of the delay line between the reference planes. Since the geometry and positioning of the delay line does not substantially affect the propagation delay, the propagation delay along the delay line is primarily dependent upon the length of the delay line and the base material used.
However, the implementation of a propagation delay along calculated lengths of delay lines does not always produce actual results within the tolerances of high speed systems. In addition, the propagation delay of the embedded delay lines are not typically adjustable after the initial manufacture of a system including the delay line. As a result, delay line systems are often remanufactured with adjustments being made in an iterative process based on propagation delay testing until a desired propagation delay is achieved. In some instances, this process is both time consuming and expensive. In addition, systems and electronic component parameters can change over the manufacturing life of the system product, which in some circumstance may cause clock signals to be desynchronized.
One aspect of the present invention relates to a tunable delay line system including a stripline and a plurality of cross-over lines. The stripline defines a propagation delay characteristic. The plurality of cross-over lines are each spaced from and extend with an orientation that is nonparallel with the stripline. Each of the plurality of cross-over lines is configured to be selectively grounded to alter the propagation delay characteristic of the stripline.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
According to one embodiment, a tunable, embedded delay line or stripline utilizes cross-over lines embedded between the delay line and a reference plane and configured to be selectively grounded to adjust signal delay along the delay line. In one example of this embodiment, one or more of the cross-over lines are grounded to increase the capacitance of the delay line without generally effecting the inductance of the delay line. Changing the capacitance without substantially changing the inductance alters the delay along the delay line. Consequently, the more cross-over lines that are grounded, the more the propagation delay along the delay line is adjusted. Conversely, if no cross-over lines are grounded, the cross-over lines are virtually transparent to the delay line and do not substantially affect the propagation delay. In this respect, following initial design and manufacture of a circuit board, the propagation delay can be tuned or altered to more closely match the desired timing or delay of clock signals in the circuit by grounding various numbers of the cross-over lines. Accordingly, by more closely tuning the propagation delay to match other signal speeds or clock specifications, a more reliable delay line circuit can be provided.
Turning to the figures,
First and second reference planes 12 and 14 are spaced from one another, and in one embodiment, extend generally parallel to one another. Stripline 16 is an elongated trace extending between the first and second reference planes 12 and 14. Each of the plurality of cross-over lines 18 extends in a direction generally non-parallel to stripline 16 between stripline 16 and one of first and second reference planes 12 and 14. As illustrated in
In one embodiment, first and second reference planes 12 and 14 are any suitable reference planes, such as copper plates, held to a constant potential. In one embodiment, first and second reference planes 12 and 14 are held at ground and, therefore, are otherwise referred to as first and second ground planes 12 and 14.
Stripline 16 is a suitable signal conductor, such as a trace, wire, etc., configured to facilitate signal travel. In one example, stripline 16 is a copper trace. Stripline 16 is positioned between first and second reference planes 12 and 14. More specifically, as depicted in
Each of the plurality of cross-over lines 18 is a wire, trace, or other suitable conductor and extends between first and second reference planes 12 and 14. In one embodiment, each cross-over line 18 extends with an orientation generally non-parallel to the extension of stripline 16. In one example of this embodiment, each cross-over line 18 extends with an orientation generally perpendicular to the extension of stripline 16 and, as such, is a transverse line 18. Although referred to throughout the remainder of the specification as transverse lines 18 for clarity, it should be understood that other non-parallel cross-over lines 18 could alternatively or additionally be utilized.
In one embodiment, as depicted in
Insulating substrate 20 substantially surrounds each of first reference plane 12, second reference plane 14, stripline 16, and the plurality of transverse lines 18. In one embodiment, insulating substrate 20 is formed of fiberglass, such as FR-4, or another suitable insulating substrate. In one example, as depicted in
In this respect, transverse lines 18 are electrically floating within insulating substrate 20 and are not initially magnetically or electrically coupled to reference planes 12 or 14 or to stripline 16. In this state, transverse lines 18 are neither electrostatically nor magnetically coupled to stripline 16. Also, floating transverse lines 18 do not substantially affect the propagation delay along stripline 16. Otherwise stated, when uncoupled from reference planes 12 or 14, transverse lines 16 are generally electrically transparent to stripline 16. In one embodiment, delay line system 10 with transparent transverse lines 18 functions similar to delay line systems that do not incorporate transverse lines 18. As such, the propagation delay along stripline 16 can be generally expressed by one of the following Equations I or II:
tp=√{square root over (με)} Equation I
where
where
In the case of transparent transverse lines 18, the propagation delay per unit length expressed by Equation I is generally equal to the propagation delay expressed by Equation II. The delay expressed in Equation I is based solely on the properties of insulating substrate 20. Accordingly, the propagation delay per unit length tp may be directly provided by the substrate manufacturer. For example, FR4 fiberglass generally has a propagation delay tp of 180 pico seconds/inch. Equation II expresses the delay based on properties of stripline 16. However, since inductance and capacitance of stripline 16 are inversely proportional when transverse lines 18 are transparent, geometry changes to stripline 16 and its position between reference planes 12 and 14 do not generally alter the delay calculated using Equation II. As such, neither width W nor or thickness T of stripline 16 as depicted in
In one embodiment, as depicted in
Grounded transverse lines 18 alter the capacitance while maintaining inductance of stripline 16. In particular, capacitance is generally added to stripline 16 by placing stripline 16 in the proximity of any metal object. Conversely, inductance is generally altered by coupling wires or traces that have a parallel orientation with respect to one another. Therefore, by placing transverse lines 18 near stripline 16 where transverse lines 18 are generally perpendicular rather than parallel to stripline 16, grounded transverse lines 18 alter the capacitance but do not substantially alter the inductance of stripline 16. Accordingly, by maintaining the inductance while altering the capacitance of stripline 16, the delay along stripline 16 is effectively altered as evident by Equation II. Since the inversely proportional relationship of capacitance and inductance is broken by grounding at least one transverse line 18, the positioning and geometry of stripline 16 and transverse lines 18 comes into play in determining propagation delay along stripline 16.
With this in mind, when at least one transverse line is grounded, Equation I based on the permeability and permittivity of insulating substrate 20 generally no longer holds true. In particular, Equation I is based upon stripline 16 being placed between solid references planes rather than the slotted reference plane created by grounding transverse lines 18. As such, following initial manufacture of delay circuit 10, connectors 40 are added as needed to ground individual transverse lines 18 to tune or adjust the propagation delay of stripline 16 to a desired time (e.g., a time matching other clock signals). In one embodiment, each transverse line 18 that is grounded increases the capacitance and, therefore, increases the propagation delay along stripline 16. Accordingly, the propagation delay of stripline 16 when transverse lines 18 are grounded depends upon the geometry and positioning of stripline 16 and transverse lines 18.
For example, when transverse lines 18 are not grounded or, in other words, are transparent, the capacitance C along stripline 16 is generally expressed by the following Equation III:
where
where
As described above, when transverse lines 18 are grounded the capacitance of stripline 16 generally increases. Therefore, assuming each of transverse lines 18 has a similar cross-sectional area and are each spaced a distance equal to the width of each transverse line 18, the increased capacitance upon grounding of transverse lines 18 is expressed by Equation V:
where
where
where
Accordingly, the ratio of the distance between stripline 16 and ground plane 12 or 14 to the distance between stripline 16 and transverse lines 18 (i.e., h/y) determines the amount of propagation delay change created by grounding transverse lines 18 as illustrated in the examples provided in the below Table I.
As such, where h/y is equal to 6, when transverse lines 18 are grounded as described for this example, the propagation delay of stripline 16 is doubled. In other embodiments, different numbers of transverse lines 18 at are grounded altering the spacing of the grounded transverse lines 18 and affecting the propagation delay in a way which is different than that expressed by the above equations and related discussion. Similar changes to the propagation delay characteristics expressed by the above equations would be effectuated when striplines 16 and/or transverse lines 18 have different geometries or spacing within delay line circuit 10 as compared to those values assumed above.
In addition, the tunable nature of stripline 16 within embodiments of delay line system 10 allows the total delay time of stripline 16 to be more closely matched or optimized to the desired time than is generally obtainable for typical embedded delay lines based upon design calculations alone. Moreover, the tunable nature of stripline 16 with transverse lines 18 generally can provide for a less expensive product by decreasing or eliminating the iterative manufacturing runs often utilized to optimize delay of typical, embedded, non-adjustable delay lines. Use of embedded delay lines also can provide additional tolerance to a designer than is generally available with use of external or removable delay lines.
One embodiment of a method of providing and utilizing delay line system 10 is generally illustrated at 50 in the flow chart of
At 54, based on the design of delay line system 10 provided at 52, delay circuit 10 is manufactured. Although the designer's calculations are configured to provide stripline 16 having the desired propagation delay, variables and manufacturing tolerances usually provide stripline 16 with a delay slightly greater than or less than the total desired propagation delay. Therefore, embodiments of delay line system 10 are provided with transverse lines 18 to permit optimization or tuning of stripline delay after the initial manufacture of delay line system 10.
At 56, following manufacture of delay line system 10, delay line system 10 is tested in a suitable manner to determine the actual delay along stripline 16. At 58, it is determined if the actual propagation delay along stripline 16 is satisfactory. More particularly, the actual propagation delay along stripline 16 is compared with the desired delay and/or an actual clock time or synchronous signal delay to determine whether the difference between the two times is within allowable tolerances for the circuited system including delay line system 10. For example, if the propagation delay along stripline 16 is determined to be too short as compared to the actual desired propagation delay, the propagation delay of the stripline 16 will be increased during tuning.
If the propagation delay is determined to be satisfactory, that is if the propagation delay meets the desired propagation delay of delay line system 10 and is within the tolerances allowed for delay line system 10, then stripline 16 is satisfactory as denoted as “YES” in
Conversely, at 58, if it is determined that the propagation delay of stripline 16 is unsatisfactory as denoted as “NO” in
Following grounding of a estimated number of transverse lines 18, process elements 58 and 62 are repeated until the actual propagation delay of stripline 16 is considered to be satisfactory. Once considered to be satisfactory, process element 60 is performed as described above. In one embodiment, if too many transverse lines 18 were coupled to a reference plane 12 or 14 at 62, a subsequent process element 62 can also include decoupling of one or more transverse lines 18 from the reference plane 12 or 14. In this iterative process, the propagation delay of stripline 16 is gradually adjusted until it is found to be satisfactory without generally requiring the manufacture of a new circuit system or delay line system 10. As described above, this method allows the propagation delay of stripline 16 to be adjusted without requiring additional manufacturing and without the use of external striplines. In one embodiment, stripline 16 can also be tuned or re-tuned after a period of use to account for changes in the system and/or associated electronic components that occur after use.
In one embodiment, delay line system 10 is part of a computer system, such as computer system 120 generally illustrated in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
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