In the connected world, people create, transport, store, and consume vast amount of data from making a phone call, using the facsimile machine, and using the internet to name a few. We treat the technology that keeps people connected as ubiquitous and always available. Some of these technologies to transport the vast amount of data involve optics or lasers. One type of laser is called vertical cavity surface emitting laser (VCSEL) and is one of the technological components needed for the connected world. Market requirements demand that VCSEL manufacturability improves and price decreases.
VCSELs represent a relatively new class of semiconductor lasers. While there are many variations of VCSELs, one common characteristic is that they emit light perpendicular to a wafer's surface. In comparison to edge emitting lasers, this common VCSEL characteristic enables improved testing, improved manufacturing yield, and lowered cost. VCSELs can be formed from a wide range of material systems, e.g. material combinations and structures, to produce specific characteristics. In particular, the various material systems can be tailored to produce different laser wavelength.
As VCSELs enter new markets and proliferate in existing markets, the requirements for better performance, manufacturing yield, lower cost, as well as growing system requirements stimulate developments for new structures and material systems. In particular, long-wavelength (1000 nm to 2000 nm) VCSEL exists but continue to be a large area for research and product development.
The present invention provides a vertical cavity surface emitting laser system including providing an epitaxially grown bottom spacer layer, providing an active layer on the epitaxially grown bottom spacer layer, providing a top spacer layer on the active layer, and etching a part of the epitaxially grown top spacer layer on a side opposite the active layer.
Certain embodiments of the invention have other configurations in addition to or in place of those mentioned above. The configurations will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention, and it is to be understood that other embodiments would be evident based on the present disclosure and that process or mechanical changes may be made without departing from the scope of the present invention.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known structures, configurations, and process steps are not disclosed in detail.
Likewise, the drawings showing embodiments of the device are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGs.
Similarly, although the sectional views in the drawings for ease of description show the exit ends of orifices as oriented upward, this arrangement in the FIGs. is arbitrary and is not intended to suggest that the delivery path should necessarily be in an upward direction. Generally, the device can be operated in any orientation. The same numbers are used in all the drawing FIGs. to relate to the same elements.
The term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure. The term “on” refers to direct contact between one element and another rather than referring to juxtaposition.
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The tunable long-wavelength VCSEL system 100 includes a first wavelength structure 102, a second wavelength structure 104, a third wavelength structure 106, and a fourth wavelength structure 108 with each emitting photons of different wavelengths. The first wavelength structure 102, the second wavelength structure 104, the third wavelength structure 106, and the fourth wavelength structure 108 include an active layer 110, a bottom spacer layer 112, and a bottom mirror 114. The bottom mirror 114 is above a substrate 116, such as a silicon substrate. The substrate 116 is representative of a single VCSEL substrate, a wafer, or a number of wafers. The active layer 110 is above the bottom spacer layer 112, wherein the bottom spacer layer 112 is above the bottom mirror 114.
The first wavelength structure 102 also includes a first top mirror 118 on a first top spacer layer 120, wherein the first top spacer layer 120 is above the active layer 110. A first optical cavity 122 is a region of the first wavelength structure 102 between the first top mirror 118 and the bottom mirror 114. The length of the first optical cavity 122 and the active layer 110 substantially determines a first wavelength emitted from the first wavelength structure 102. The first wavelength may be tuned to a desired value by varying the height of the first top spacer layer 120. The length of the first optical cavity 122 must be approximately a multiple of half of the first wavelength.
The first top spacer layer 120 is doped to a type complementary to the bottom spacer layer 112, such as the first top spacer layer 120 is n-type and the bottom spacer layer 112 is p-type. The electrons and holes from the first top spacer layer 120 and the bottom spacer layer 112, respectively, recombine in the active layer 110 resulting in photon emissions substantially of the first wavelength.
In a similar manner to the first wavelength structure 102, the second wavelength structure 104 includes a second top mirror 124 over a second optical cavity 126, wherein the second optical cavity 126 includes a second top spacer layer 128. The second wavelength structure 104 emits photons substantially of a second wavelength and may be tuned by varying the height of the second top spacer layer 128.
In a similar manner to the first wavelength structure 102, the third wavelength structure 106 includes a third top mirror 130 over a third optical cavity 132, wherein the third optical cavity 132 includes a third top spacer layer 134. The third wavelength structure 106 emits photons substantially of a third wavelength and may be tuned by varying the height of the third top spacer layer 134.
In a similar manner to the first wavelength structure 102, the fourth wavelength structure 108 includes a fourth top mirror 136 over a fourth optical cavity 138, wherein the fourth optical cavity 138 includes a fourth top spacer layer 140. The fourth wavelength structure 108 emits photons substantially of a fourth wavelength (not shown) and may be tuned by varying the height of the fourth top spacer layer 140.
The lengths of the first optical cavity 122, the second optical cavity 126, the third optical cavity 132, and the fourth optical cavity 138 are different resulting in a different wavelength generated by each optical cavity.
For illustrative purposes, the tunable long-wavelength VCSEL system 100 is shown with four wavelength structures providing four different wavelengths, although it is understood the number of wavelength structures and the number of wavelengths may differ, as well. It is also understood that the lengths of the first optical cavity 122, the second optical cavity 126, the third optical cavity 132, and the fourth optical cavity 138 may be in any relationship to each other.
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Some sacrificial etch stop layers (not shown) may be grown on the formation substrate 202 to facilitate ease of removal of the formation substrate 202 at a later stage in the process. An epitaxially grown top spacer layer 204, such as an InP or an InP-based material, is epitaxially grown on the sacrificial etch stop layers and above the formation substrate 202. The epitaxially grown top spacer layer 204 is shown prior to selective etching to form the four different regions. Selectively etching a first part of the epitaxially grown top spacer layer 204 forms the first top spacer layer 120. Similarly, selectively etching a second part of the epitaxially grown top spacer layer 204 forms the second top spacer layer 128. Similarly, selectively etching a third part of the epitaxially grown top spacer layer 204 forms the third top spacer layer 134. Similarly, selectively etching a fourth part of the epitaxially grown top spacer layer 204 forms the fourth top spacer layer 140.
It has been discovered that the present invention provides previously unachievable tight control over uniformity and thickness of the optical cavity lengths. The epitaxial growth allows tight control of the height of the epitaxially grown top spacer layer 204 such that the thickness variation is about or less than within 1% across a wafer 116.
Since etching uniformly etches the epitaxially grown top spacer layer 204, this means that all tunable long-wavelength VCSEL systems 100 from the same wafer specified to have the same wavelengths would have wavelengths about or less than within 1% of each other.
It has also been discovered that the present invention provides tight control of the height of the epitaxially grown top spacer layer 204 such that the thickness variation is within about 1% across all wafers 116.
This means that all tunable long-wavelength VCSEL systems 100 from all wafers 116 specified to have the same wavelengths would have wavelengths within 1% of each other.
The epitaxially grown top spacer layer 204 is doped forming an electrically conductive layer, such as n-type, providing an electrical connection for an external bias contact (not shown). The epitaxially grown top spacer layer 204 is grown to a predetermined height including the largest height of the first top spacer layer 120, the second top spacer layer 128, the third top spacer layer 134, and the fourth top spacer layer 140.
For illustrative purposes, the epitaxially grown top spacer layer 204 is shown as a single layer, although it is understood that the epitaxially grown top spacer layer 204 may include any number of stratified layers. It is also understood that any of the stratified layers of the epitaxially grown top spacer layer 204 may be doped differently, such as different doping concentration or different dopant type.
The active layer 110 is grown on the epitaxially grown top spacer layer 204, wherein the active layer 110 is typically intrinsic or very minimally doped. The active layer 110 includes one or more quantum wells (not shown). The quantum wells, which typically include a quantum well layer (not shown), sandwiched by a pair of barrier layers (not shown), are the layers into which carriers, such as electrons and holes, are injected. The electrons and holes recombine in the active layer 110 and emit photons at a wavelength determined by the material layers in the quantum well. The quantum well layer includes a low band gap semiconductor material, while the barrier layer has a band gap higher than the band gap of the quantum well layer. When the device is subject to forward bias, electrons and holes are injected into and trapped in the quantum well layer and recombined to emit coherent light at a particular wavelength.
For illustrative purposes, the active layer 110 may be an indium phosphide based, such as the material pair for the quantum well layer and the barrier layer of InGaAsP and InGaAsP, respectively, or of InAlGaAs and InP, respectively. The materials used for the quantum well layer and the barrier layer provide lattice matching between these layers as well as with the bottom spacer layer 112 and the epitaxially grown top spacer layer 204. Although it is also understood the active layer 110 may include other active material, such as quantum wires or quantum dots.
The bottom spacer layer 112 is grown on the active layer 110. The bottom spacer layer 112 is doped to a type complementary to the epitaxially grown top spacer layer 204. The bottom spacer layer 112 forms an electrically conductive layer, such as p-type, providing an electrical connection for an external bias contact (not shown). For illustrative purposes, the bottom spacer layer 112 is shown as a single layer, although it is understood that the bottom spacer layer 112 may include any number of stratified layers. It is also understood that any of the stratified layers of the bottom spacer layer 112 may be doped differently, such as different doping concentration or different dopant type. Also for illustrative purposes, the epitaxially grown top spacer layer 204 is described doped as n-type resulting in the bottom spacer layer 112 doped as p-type, although it is understood the doping type may differ, as well.
The bottom mirror 114, such as a dielectric mirror, is deposited on the bottom spacer layer 112. For illustrative purposes, the bottom mirror 114 is shown as a dielectric mirror, although it is understood that the bottom mirror 114 may be constructed of other materials, such as semiconductor materials that may be lattice matched to the material of the bottom spacer layer 112. The semiconductor materials may be grown on the bottom spacer layer 112.
The bottom mirror 114 is formed of multiple layer pairs of complementary refractive material. The multiple layer pairs create an alternating structure where each layer pair includes a high refractive layer (not shown) and a low refractive layer (not shown). Such a complementary layer pair can be made from a number of different combinations of materials including semiconductor layers, dielectric materials such as TiO2 (titanium dioxide) for the high refractive layer and SiO2 (silicon dioxide) for the low refractive layer, or hybrid combinations of semiconductor, dielectric and metal layers. Materials and construction determine the type of reflector such as a “dielectric” distributed Bragg reflector (DBR) or a semiconductor DBR or a metal DBR.
For illustrative purpose, the present invention discloses the bottom mirror 114 as a dielectric DBR, but it is understood that the present invention can be implemented with other types of DBR, such as a semiconductor or metal DBR. It is further understood that different compounds such as quaternary compounds of indium gallium aluminum arsenide (InGaAlAs), or indium gallium aluminum arsenide phosphide (InGaAlAsP), or aluminum gallium arsenide antimonide (AlGaAsSb), and aluminum gallium phosphide antimonide (AlGaPSb) may be used as the high refractive layer 702 in combination with the low refractive layer 704 such as binary indium phosphide layers, ternary indium/aluminun/arsenic (InAlAs), aluminum/arsenic/antimony (AlAsSb) or aluminum/phosphorous/antimony (AIPSb) layers.
Bonding metal layer (not shown), such as palladium (Pa) or tantalum (Ta) based material, is applied on the bottom mirror 114 or on the substrate 116 with a physical vapor deposition (PVD) or a similar process. The substrate 116 attaches to the bottom mirror 114 on a side opposite the bottom spacer layer 112. The substrate 116 may be used to provide a platform to form an array of the tunable long-wavelength VCSEL system 100.
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For dielectric mirrors, dielectric materials may be deposited on the first top spacer layer 120, the second top spacer layer 128, the third top spacer layer 134, and the fourth top spacer layer 140 to a predetermined height. Dielectric curvatures resulting from the different heights of the first top spacer layer 120, the second top spacer layer 128, the third top spacer layer 134, and the fourth top spacer layer 140 are minimal.
Other materials, such as semiconductor materials that are lattice matched to the epitaxially grown top spacer layer 204 of
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It has been discovered that the present invention thus has numerous aspects.
One aspect is that the present invention is tuning the cavity length, which may be tuned by selectively etching epitaxially grown multi-layers, to result in different Fabry-Perot resonator/cavity lengths for different wavelengths; this can be done within the wafer (to adjust wavelength uniformity within a wafer), or on a smaller scale as within a chip (e.g. for WDM applications). When increasing the VCSEL cavity length (e.g. to several wavelengths), the tuning etch depth(s) for a given set of resonance wavelengths also increases, which results in a more controllable and manufacturable tuning process.
For a long cavity device, asymmetric placement of the quantum wells (QWs on the opposite side of the etchable tuning layers of the cavity) is well suited for this application; this is because the optical standing wave pattern around the quantum wells changes little as the cavity length changes. That fact provides little laser threshold variation for a wide tuning range, while also providing reasonably thick layers to be etched for tuning, easing manufacturing concerns of controllably etching very thin layers. For high device density applications, this approach is limited by the spatial resolution of the selective tuning etch, allowing for a high laser device density within a chip.
These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
Thus, it has been discovered that the tunable long-wavelength VCSEL system with multiple wavelengths generation method and apparatus of the present invention furnish important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for VCSEL design, manufacturing, and operation. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing VCSEL devices that are fully compatible with conventional manufacturing processes and technologies.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Number | Date | Country | |
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Parent | 11207481 | Aug 2005 | US |
Child | 12143646 | US |