Claims
- 1. A method for selecting a multiple frequency band RF signal and reducing the number of components in a RF system comprising of
An amplifier for each frequency band with output connected to the input of an image filter for each frequency band, the output of said image filters connected to input of a buffer stage for each frequency band, and the output of each said buffer stage connected together. A mechanism to power down the buffer stages in order to select a frequency band:
- 2. The method of claim 1 wherein the receiver architecture is a superheterodyne type.
- 3. The method of claim 1 wherein the receiver architecture is a low-intermediate frequency type.
- 4. The method of claim 1 wherein the receiver architecture is a direct conversion type.
- 5. The method of claim 1 wherein the receiver architecture is a quasi-direct conversion type.
- 6. The method of claim 1 wherein the output of said buffer stages is connected to the input of a mixer.
- 7. The method of claim 1 wherein the LNA of the non-selected frequency band can be powered down to improve isolation of the non-selected frequency band.
- 8. The method of claim 1 wherein the buffer stages comprise of emitter follower circuits.
- 9. The method of claim 1 wherein the buffer stages comprise of source follower circuits.
- 10. The method of claim 1 wherein the buffer stages comprise of a low noise amplifier with power down capability.
- 11. The method of claim 1 wherein the buffer stages comprise of any known amplifier topology.
- 12. The method of claim 1 wherein the number of selectable frequency bands is two.
- 13. The method of claim 1 wherein the number of selectable frequency bands is an integer N, where N>1.
- 14. The method of claim 1 wherein the said image filters are external components to the RF chip.
- 15. The method of claim 1 wherein the said image filters are integrated resonant elements on the RF chip.
- 16. The method of claim 1 wherein the receiver is implemented with CMOS technology.
- 17. The method of claim 1 wherein the receiver is implemented in bipolar, BiCMOS, and SiGe technologies.
REFERENCES
[0001] U.S. Pat. No. 6,064,866, May 16, 2000, Lange.
[0002] U.S. Pat. No. 4,972,509, Nov. 20, 1990, Maejima.
Provisional Applications (1)
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Number |
Date |
Country |
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60431977 |
Dec 2002 |
US |