Patent Grant
7671663
The present invention is directed, in general, to microelectronics and, more specifically, to a tunable voltage controller, a method of operating a tunable voltage controller and an integrated circuit employing the controller or the method.
Supplying or removing power, either partially or completely, from a block of circuitry may be controlled by header or footer circuits. The header circuit forms a controllable switch between a positive supply voltage and a block of sub-circuits. Similarly, the footer circuit forms a controllable switch between a negative supply voltage and the sub-circuit block. Activation of the header or footer circuits allows a virtual operating supply voltage to be connected to the sub-circuit block. Deactivation of the header or footer circuits provides a standby voltage for the sub-circuit block.
A conventional approach to providing an operating virtual voltage to the sub-circuit uses a conducting header or footer MOS transistor. Then, the forward voltage drop of a separate, external junction diode that is parallel-connected with the MOS transistor is used to provide a standby voltage for the sub-circuit when the operating voltage MOS transistor is not conducting. Alternatively, another parallel MOS transistor connected as a diode can be used to provide a standby voltage for the sub-circuit when the operating voltage MOS transistor is not conducting. However, the voltage drop obtained with either the external junction diode or the diode-connected transistor is usually not optimal, especially over a range of fabrication process variations and for different applications.
Accordingly, what is needed in the art is a more effective way of obtaining a voltage, such as a standby voltage, that is tunable and also maintains the power and area advantages of a diode-connected transistor.
To address the above-discussed deficiencies of the prior art, the present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a biasing unit configured to adjust the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.
In another aspect, the present invention provides a method of operating a tunable voltage controller for use with a sub-circuit. The method includes providing a voltage for the sub-circuit by employing a diode-connected MOS transistor contained in a doped well of a substrate. The method also includes adjusting the voltage by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source.
The present invention also provides, in yet another aspect, an integrated circuit. The integrated circuit includes a voltage supply bus and a MOS transistor switch connected between the voltage supply bus and a sub-circuit. The integrated circuit also includes a tunable voltage controller parallel connected with the MOS transistor switch to the sub-circuit. The tunable voltage controller has a diode-connected MOS transistor contained in a doped well of a substrate and a biasing unit that selectively connects the doped well to one of a plurality of voltage sources or to a variable voltage source.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The tunable voltage controller 115 includes a diode-connected PMOS transistor Q2 and a biasing unit 120. In the illustrated embodiment, the diode-connected PMOS transistor Q2 is contained in an N-WELL 116, which is electrically isolated from a substrate containing the PMOS transistor Q2 and the N-WELL 116. Additionally, the biasing unit 120 employs a collection of fusible links that are configured to provide hard-wired connections between the N-WELL 116 and a plurality of voltage sources.
The biasing unit 120 includes a first fusible link 121a that connects the N-WELL 116 to a source of the diode-connected PMOS transistor Q2, wherein the source is also connected to the header supply voltage Vdd, as shown. A second fusible link 121b is connected to a drain of the diode-connected PMOS transistor Q2, and a third fusible link 121c is connected to an input/output supply voltage VddI/O that is associated with the sub-circuit block 105. The second and third fusible links 121b, 121c have been opened since only one fusible link (corresponding to only one of the plurality of available biasing voltage sources) may be connected at any one time to the diode-connected PMOS transistor Q2. Selection of an appropriate biasing voltage thereby allows tuning of a standby voltage as the header virtual supply voltage VHV for the sub-circuit block 105 during deactivation of the PMOS transistor switch Q1.
In
The footer supply 160 includes an NMOS transistor switch Q1 and a tunable voltage controller 165. The NMOS transistor switch Q1 is coupled to the footer supply voltage Vss and provides an operating voltage as the footer virtual supply voltage VFV for the sub-circuit block 155 during switch activation. Switch activation is provided by another activation signal AS2, which has an opposite polarity compared to the activation signal AS1 needed for activation of the PMOS transistor switch Q1 employed in
The tunable voltage controller 165 includes a diode-connected PMOS transistor Q2 and a biasing unit 170. In the illustrated embodiment, the diode-connected PMOS transistor Q2 is contained in an N-WELL 166, which is electrically isolated from a substrate containing the PMOS transistor Q2 and the N-WELL 166. Additionally, the biasing unit 170 employs a switching unit 171 (herein shown symbolically) to selectively connect the N-WELL 166 to one of several discrete biasing voltages. This arrangement provides a “step-wise” variable biasing voltage source.
In an alternative embodiment, the switching unit 171 may be configured to employ a continuously variable biasing voltage source that provides a continuous range of biasing voltages to the N-WELL 166. In either embodiment, the step-wise variable biasing voltage source or the continuously variable voltage biasing source may provide multiple voltage adjustments during regular or standby operation of a sub-circuit block as may be appropriate to a particular application.
In the illustrated embodiment of
In each of the integrated circuits 100, 150, the biasing units 120, 170 respectively connect the N-WELL to a biasing voltage source that tunes a voltage drop across the diode-connected PMOS transistor Q2. This thereby respectively adjusts the standby voltage for the sub-circuit blocks 105, 155 during deactivation of the MOS transistor switch Q1. For a lowest voltage drop (and therefore the highest standby voltage) the respective N-WELL is connected to the respective source of the diode-connected PMOS transistor Q2. This will forward bias the p-n junction in a way that contributes to a limiting of the voltage drop.
For a larger voltage drop, the respective N-WELL and drain of the diode-connected PMOS transistor Q2 may be connected. This eliminates the forward-biased p-n junction and also raises the threshold voltage Vt of the diode-connected PMOS transistor Q2. The voltage drop may be increased further by connecting the respective N-WELL to the supply voltage Vdd or even farther by connecting the respective N-WELL to the input/output supply voltage VddI/O, when available.
Therefore, a fusible link may be employed after fabrication for a single adjustment in the voltage drop across the diode-connected MOS transistor to allow for process or other variations. Additionally, a mask selection for a particular application requirement may also be employed to provide a hard-wired connection of a doped well containing the diode-connected MOS transistor to a biasing voltage source. Alternatively, multiple adjustments of the voltage drop across the diode-connected MOS transistor may be provided during either regular or standby operation.
The voltage is adjusted by selectively connecting the doped well to one of a plurality of voltage sources or to a variable voltage source, in a step 215. The step 215 allows tuning a voltage drop across the diode-connected MOS transistor and thereby adjusting the voltage for the sub-circuit. In one embodiment, one of the plurality of voltage sources or the variable voltage source employs a drain of the diode-connected MOS transistor. In another embodiment, one of the plurality of voltage sources or the variable voltage source employs a source of the diode-connected MOS transistor. In alternative embodiments, one of the plurality of voltage sources or the variable voltage source employs a supply voltage or an input/output supply voltage associated with the sub-circuit.
In a decisional step 220, it is determined whether a single voltage adjustment is to be made for the sub-circuit. If a single voltage adjustment is to be made, a hard-wired connection is made between the doped well and one of the plurality of voltage sources in a step 225. In one embodiment, the hard-wired connection employs a fusible link. The method 200 then ends in a step 235. If more than a single voltage adjustment is to be made, the variable voltage source is employed to permit connecting the doped well to more than one voltage in a step 230. The method again ends in the step 235.
While the method disclosed herein has been described and shown with reference to particular steps performed in a particular order, it will be understood that these steps may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order or the grouping of the steps is not a limitation of the present invention.
In summary, embodiments of the present invention employing a tunable voltage controller, a method of operating a tunable voltage controller and an integrated circuit employing the controller or the method have been presented. These embodiments provide a standby voltage for a sub-circuit and include an exemplary PMOS transistor connected as a diode, which has the option of connecting its associated N-WELL to different biasing voltage sources. This allows adjustment of the threshold voltage of the PMOS transistor, the voltage drop across it and the corresponding voltage provided to the sub-circuit. Of course, other embodiments of the present invention may employ a diode-connected NMOS transistor with an isolated P-WELL, where appropriate.
Using back gate bias to adjust the threshold voltage of a diode-connected MOS transistor allows use of a smaller area than employing multiple junction diodes. Additionally, embodiments of the diode-connected MOS transistor also typically require smaller area and overhead power as compared to using a low dropout (LDO) regulator. Also, extending the back gate bias to include connecting the back gate to the MOS transistor source provides a lower voltage drop than previous diode connections.
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6049245 | Son et al. | Apr 2000 | A |
| 6097113 | Teraoka et al. | Aug 2000 | A |
| 6466077 | Miyazaki et al. | Oct 2002 | B1 |
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| Number | Date | Country | |
|---|---|---|---|
| 20080136497 A1 | Jun 2008 | US |
